Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #ifndef MDSS_MDP_H |
| 16 | #define MDSS_MDP_H |
| 17 | |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/msm_mdp.h> |
| 20 | #include <linux/msm_mdp_ext.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/notifier.h> |
| 23 | #include <linux/irqreturn.h> |
| 24 | #include <linux/kref.h> |
| 25 | #include <linux/kthread.h> |
| 26 | |
| 27 | #include "mdss.h" |
| 28 | #include "mdss_mdp_hwio.h" |
| 29 | #include "mdss_fb.h" |
| 30 | #include "mdss_mdp_cdm.h" |
| 31 | |
| 32 | #define MDSS_MDP_DEFAULT_INTR_MASK 0 |
| 33 | |
| 34 | #define PHASE_STEP_SHIFT 21 |
| 35 | #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) |
| 36 | #define PHASE_RESIDUAL 15 |
| 37 | #define MAX_LINE_BUFFER_WIDTH 2048 |
| 38 | #define MAX_MIXER_HEIGHT 0xFFFF |
| 39 | #define MAX_IMG_WIDTH 0x3FFF |
| 40 | #define MAX_IMG_HEIGHT 0x3FFF |
| 41 | #define AHB_CLK_OFFSET 0x2B4 |
| 42 | #define MAX_DST_H MAX_MIXER_HEIGHT |
| 43 | #define MAX_DOWNSCALE_RATIO 4 |
| 44 | #define MAX_UPSCALE_RATIO 20 |
| 45 | #define MAX_DECIMATION 4 |
| 46 | #define MDP_MIN_VBP 4 |
| 47 | #define MAX_FREE_LIST_SIZE 12 |
| 48 | #define OVERLAY_MAX 10 |
| 49 | |
| 50 | #define VALID_ROT_WB_FORMAT BIT(0) |
| 51 | #define VALID_MDP_WB_INTF_FORMAT BIT(1) |
| 52 | #define VALID_MDP_CURSOR_FORMAT BIT(2) |
| 53 | |
| 54 | #define C3_ALPHA 3 /* alpha */ |
| 55 | #define C2_R_Cr 2 /* R/Cr */ |
| 56 | #define C1_B_Cb 1 /* B/Cb */ |
| 57 | #define C0_G_Y 0 /* G/luma */ |
| 58 | |
| 59 | /* wait for at most 2 vsync for lowest refresh rate (24hz) */ |
| 60 | #define KOFF_TIMEOUT_MS 84 |
| 61 | #define KOFF_TIMEOUT msecs_to_jiffies(KOFF_TIMEOUT_MS) |
| 62 | |
| 63 | #define OVERFETCH_DISABLE_TOP BIT(0) |
| 64 | #define OVERFETCH_DISABLE_BOTTOM BIT(1) |
| 65 | #define OVERFETCH_DISABLE_LEFT BIT(2) |
| 66 | #define OVERFETCH_DISABLE_RIGHT BIT(3) |
| 67 | |
| 68 | #define MDSS_MDP_CDP_ENABLE BIT(0) |
| 69 | #define MDSS_MDP_CDP_ENABLE_UBWCMETA BIT(1) |
| 70 | #define MDSS_MDP_CDP_AMORTIZED BIT(2) |
| 71 | #define MDSS_MDP_CDP_AHEAD_64 BIT(3) |
| 72 | |
| 73 | #define PERF_STATUS_DONE 0 |
| 74 | #define PERF_STATUS_BUSY 1 |
| 75 | |
| 76 | #define PERF_CALC_PIPE_APPLY_CLK_FUDGE BIT(0) |
| 77 | #define PERF_CALC_PIPE_SINGLE_LAYER BIT(1) |
| 78 | #define PERF_CALC_PIPE_CALC_SMP_SIZE BIT(2) |
| 79 | |
| 80 | #define PERF_SINGLE_PIPE_BW_FLOOR 1200000000 |
| 81 | #define CURSOR_PIPE_LEFT 0 |
| 82 | #define CURSOR_PIPE_RIGHT 1 |
| 83 | |
| 84 | #define MASTER_CTX 0 |
| 85 | #define SLAVE_CTX 1 |
| 86 | |
| 87 | #define XIN_HALT_TIMEOUT_US 0x4000 |
| 88 | |
| 89 | #define MAX_LAYER_COUNT 0xC |
| 90 | |
| 91 | /* hw cursor can only be setup in highest mixer stage */ |
| 92 | #define HW_CURSOR_STAGE(mdata) \ |
| 93 | (((mdata)->max_target_zorder + MDSS_MDP_STAGE_0) - 1) |
| 94 | |
| 95 | #define BITS_TO_BYTES(x) DIV_ROUND_UP(x, BITS_PER_BYTE) |
| 96 | |
| 97 | enum mdss_mdp_perf_state_type { |
| 98 | PERF_SW_COMMIT_STATE = 0, |
| 99 | PERF_HW_MDP_STATE, |
| 100 | }; |
| 101 | |
| 102 | enum mdss_mdp_block_power_state { |
| 103 | MDP_BLOCK_POWER_OFF = 0, |
| 104 | MDP_BLOCK_POWER_ON = 1, |
| 105 | }; |
| 106 | |
| 107 | enum mdss_mdp_mixer_type { |
| 108 | MDSS_MDP_MIXER_TYPE_UNUSED, |
| 109 | MDSS_MDP_MIXER_TYPE_INTF, |
| 110 | MDSS_MDP_MIXER_TYPE_WRITEBACK, |
| 111 | }; |
| 112 | |
| 113 | enum mdss_mdp_mixer_mux { |
| 114 | MDSS_MDP_MIXER_MUX_DEFAULT, |
| 115 | MDSS_MDP_MIXER_MUX_LEFT, |
| 116 | MDSS_MDP_MIXER_MUX_RIGHT, |
| 117 | }; |
| 118 | |
| 119 | enum mdss_sd_transition { |
| 120 | SD_TRANSITION_NONE, |
| 121 | SD_TRANSITION_SECURE_TO_NON_SECURE, |
| 122 | SD_TRANSITION_NON_SECURE_TO_SECURE |
| 123 | }; |
| 124 | |
| 125 | static inline enum mdss_mdp_sspp_index get_pipe_num_from_ndx(u32 ndx) |
| 126 | { |
| 127 | u32 id; |
| 128 | |
| 129 | if (unlikely(!ndx)) |
| 130 | return MDSS_MDP_MAX_SSPP; |
| 131 | |
| 132 | id = fls(ndx) - 1; |
| 133 | |
| 134 | if (unlikely(ndx ^ BIT(id))) |
| 135 | return MDSS_MDP_MAX_SSPP; |
| 136 | |
| 137 | return id; |
| 138 | } |
| 139 | |
| 140 | static inline enum mdss_mdp_pipe_type |
| 141 | get_pipe_type_from_num(enum mdss_mdp_sspp_index pnum) |
| 142 | { |
| 143 | enum mdss_mdp_pipe_type ptype; |
| 144 | |
| 145 | switch (pnum) { |
| 146 | case MDSS_MDP_SSPP_VIG0: |
| 147 | case MDSS_MDP_SSPP_VIG1: |
| 148 | case MDSS_MDP_SSPP_VIG2: |
| 149 | case MDSS_MDP_SSPP_VIG3: |
| 150 | ptype = MDSS_MDP_PIPE_TYPE_VIG; |
| 151 | break; |
| 152 | case MDSS_MDP_SSPP_RGB0: |
| 153 | case MDSS_MDP_SSPP_RGB1: |
| 154 | case MDSS_MDP_SSPP_RGB2: |
| 155 | case MDSS_MDP_SSPP_RGB3: |
| 156 | ptype = MDSS_MDP_PIPE_TYPE_RGB; |
| 157 | break; |
| 158 | case MDSS_MDP_SSPP_DMA0: |
| 159 | case MDSS_MDP_SSPP_DMA1: |
| 160 | case MDSS_MDP_SSPP_DMA2: |
| 161 | case MDSS_MDP_SSPP_DMA3: |
| 162 | ptype = MDSS_MDP_PIPE_TYPE_DMA; |
| 163 | break; |
| 164 | case MDSS_MDP_SSPP_CURSOR0: |
| 165 | case MDSS_MDP_SSPP_CURSOR1: |
| 166 | ptype = MDSS_MDP_PIPE_TYPE_CURSOR; |
| 167 | break; |
| 168 | default: |
| 169 | ptype = MDSS_MDP_PIPE_TYPE_INVALID; |
| 170 | break; |
| 171 | } |
| 172 | |
| 173 | return ptype; |
| 174 | } |
| 175 | |
| 176 | static inline enum mdss_mdp_pipe_type get_pipe_type_from_ndx(u32 ndx) |
| 177 | { |
| 178 | enum mdss_mdp_sspp_index pnum; |
| 179 | |
| 180 | pnum = get_pipe_num_from_ndx(ndx); |
| 181 | |
| 182 | return get_pipe_type_from_num(pnum); |
| 183 | } |
| 184 | |
| 185 | enum mdss_mdp_block_type { |
| 186 | MDSS_MDP_BLOCK_UNUSED, |
| 187 | MDSS_MDP_BLOCK_SSPP, |
| 188 | MDSS_MDP_BLOCK_MIXER, |
| 189 | MDSS_MDP_BLOCK_DSPP, |
| 190 | MDSS_MDP_BLOCK_WB, |
| 191 | MDSS_MDP_BLOCK_CDM, |
| 192 | MDSS_MDP_BLOCK_SSPP_10, |
| 193 | MDSS_MDP_BLOCK_MAX |
| 194 | }; |
| 195 | |
| 196 | enum mdss_mdp_csc_type { |
| 197 | MDSS_MDP_CSC_YUV2RGB_601L, |
| 198 | MDSS_MDP_CSC_YUV2RGB_601FR, |
| 199 | MDSS_MDP_CSC_YUV2RGB_709L, |
| 200 | MDSS_MDP_CSC_YUV2RGB_2020L, |
| 201 | MDSS_MDP_CSC_YUV2RGB_2020FR, |
| 202 | MDSS_MDP_CSC_RGB2YUV_601L, |
| 203 | MDSS_MDP_CSC_RGB2YUV_601FR, |
| 204 | MDSS_MDP_CSC_RGB2YUV_709L, |
| 205 | MDSS_MDP_CSC_RGB2YUV_2020L, |
| 206 | MDSS_MDP_CSC_RGB2YUV_2020FR, |
| 207 | MDSS_MDP_CSC_YUV2YUV, |
| 208 | MDSS_MDP_CSC_RGB2RGB, |
| 209 | MDSS_MDP_MAX_CSC |
| 210 | }; |
| 211 | |
| 212 | enum mdp_wfd_blk_type { |
| 213 | MDSS_MDP_WFD_SHARED = 0, |
| 214 | MDSS_MDP_WFD_INTERFACE, |
| 215 | MDSS_MDP_WFD_DEDICATED, |
| 216 | }; |
| 217 | |
| 218 | enum mdss_mdp_reg_bus_cfg { |
| 219 | REG_CLK_CFG_OFF, |
| 220 | REG_CLK_CFG_LOW, |
| 221 | REG_CLK_CFG_HIGH, |
| 222 | }; |
| 223 | |
| 224 | enum mdss_mdp_panic_signal_type { |
| 225 | MDSS_MDP_PANIC_NONE, |
| 226 | MDSS_MDP_PANIC_COMMON_REG_CFG, |
| 227 | MDSS_MDP_PANIC_PER_PIPE_CFG, |
| 228 | }; |
| 229 | |
| 230 | enum mdss_mdp_fetch_type { |
| 231 | MDSS_MDP_FETCH_LINEAR, |
| 232 | MDSS_MDP_FETCH_TILE, |
| 233 | MDSS_MDP_FETCH_UBWC, |
| 234 | }; |
| 235 | |
| 236 | /** |
| 237 | * enum mdp_commit_stage_type - Indicate different commit stages |
| 238 | * |
| 239 | * @MDP_COMMIT_STATE_WAIT_FOR_PINGPONG: At the stage of being ready to |
| 240 | * wait for pingpong buffer. |
| 241 | * @MDP_COMMIT_STATE_PINGPONG_DONE: At the stage that pingpong |
| 242 | * buffer is ready. |
| 243 | */ |
| 244 | enum mdp_commit_stage_type { |
| 245 | MDP_COMMIT_STAGE_SETUP_DONE, |
| 246 | MDP_COMMIT_STAGE_READY_FOR_KICKOFF, |
| 247 | }; |
| 248 | |
| 249 | struct mdss_mdp_ctl; |
| 250 | typedef void (*mdp_vsync_handler_t)(struct mdss_mdp_ctl *, ktime_t); |
| 251 | |
| 252 | struct mdss_mdp_vsync_handler { |
| 253 | bool enabled; |
| 254 | bool cmd_post_flush; |
| 255 | mdp_vsync_handler_t vsync_handler; |
| 256 | struct list_head list; |
| 257 | }; |
| 258 | |
| 259 | struct mdss_mdp_lineptr_handler { |
| 260 | bool enabled; |
| 261 | mdp_vsync_handler_t lineptr_handler; |
| 262 | struct list_head list; |
| 263 | }; |
| 264 | |
| 265 | enum mdss_mdp_wb_ctl_type { |
| 266 | MDSS_MDP_WB_CTL_TYPE_BLOCK = 1, |
| 267 | MDSS_MDP_WB_CTL_TYPE_LINE |
| 268 | }; |
| 269 | |
| 270 | enum mdss_mdp_bw_vote_mode { |
| 271 | MDSS_MDP_BW_MODE_SINGLE_LAYER, |
| 272 | MDSS_MDP_BW_MODE_SINGLE_IF, |
| 273 | MDSS_MDP_BW_MODE_MAX |
| 274 | }; |
| 275 | |
| 276 | enum mdp_wb_blk_caps { |
| 277 | MDSS_MDP_WB_WFD = BIT(0), |
| 278 | MDSS_MDP_WB_ROTATOR = BIT(1), |
| 279 | MDSS_MDP_WB_INTF = BIT(2), |
| 280 | MDSS_MDP_WB_UBWC = BIT(3), |
| 281 | }; |
| 282 | |
| 283 | /** |
| 284 | * enum perf_calc_vote_mode - enum to decide if mdss_mdp_get_bw_vote_mode |
| 285 | * function needs an extra efficiency factor. |
| 286 | * |
| 287 | * @PERF_CALC_VOTE_MODE_PER_PIPE: used to check if efficiency factor is needed |
| 288 | * based on the pipe properties. |
| 289 | * @PERF_CALC_VOTE_MODE_CTL: used to check if efficiency factor is needed based |
| 290 | * on the controller properties. |
| 291 | * @PERF_CALC_VOTE_MODE_MAX: used to check if efficiency factor is need to vote |
| 292 | * max MDP bandwidth. |
| 293 | * |
| 294 | * Depending upon the properties of each specific object (determined |
| 295 | * by this enum), driver decides if the mode to vote needs an |
| 296 | * extra factor. |
| 297 | */ |
| 298 | enum perf_calc_vote_mode { |
| 299 | PERF_CALC_VOTE_MODE_PER_PIPE, |
| 300 | PERF_CALC_VOTE_MODE_CTL, |
| 301 | PERF_CALC_VOTE_MODE_MAX, |
| 302 | }; |
| 303 | |
| 304 | struct mdss_mdp_perf_params { |
| 305 | u64 bw_overlap; |
| 306 | u64 bw_overlap_nocr; |
| 307 | u64 bw_writeback; |
| 308 | u64 bw_prefill; |
| 309 | u64 max_per_pipe_ib; |
| 310 | u32 prefill_bytes; |
| 311 | u64 bw_ctl; |
| 312 | u32 mdp_clk_rate; |
| 313 | DECLARE_BITMAP(bw_vote_mode, MDSS_MDP_BW_MODE_MAX); |
| 314 | }; |
| 315 | |
| 316 | struct mdss_mdp_writeback { |
| 317 | u32 num; |
| 318 | char __iomem *base; |
| 319 | u32 caps; |
| 320 | struct kref kref; |
| 321 | u8 supported_input_formats[BITS_TO_BYTES(MDP_IMGTYPE_LIMIT1)]; |
| 322 | u8 supported_output_formats[BITS_TO_BYTES(MDP_IMGTYPE_LIMIT1)]; |
| 323 | }; |
| 324 | |
| 325 | struct mdss_mdp_ctl_intfs_ops { |
| 326 | int (*start_fnc)(struct mdss_mdp_ctl *ctl); |
| 327 | int (*stop_fnc)(struct mdss_mdp_ctl *ctl, int panel_power_state); |
| 328 | int (*prepare_fnc)(struct mdss_mdp_ctl *ctl, void *arg); |
| 329 | int (*display_fnc)(struct mdss_mdp_ctl *ctl, void *arg); |
| 330 | int (*wait_fnc)(struct mdss_mdp_ctl *ctl, void *arg); |
| 331 | int (*wait_vsync_fnc)(struct mdss_mdp_ctl *ctl); |
| 332 | int (*wait_pingpong)(struct mdss_mdp_ctl *ctl, void *arg); |
| 333 | u32 (*read_line_cnt_fnc)(struct mdss_mdp_ctl *); |
| 334 | int (*add_vsync_handler)(struct mdss_mdp_ctl *, |
| 335 | struct mdss_mdp_vsync_handler *); |
| 336 | int (*remove_vsync_handler)(struct mdss_mdp_ctl *, |
| 337 | struct mdss_mdp_vsync_handler *); |
| 338 | int (*config_fps_fnc)(struct mdss_mdp_ctl *ctl, int new_fps); |
| 339 | int (*restore_fnc)(struct mdss_mdp_ctl *ctl, bool locked); |
| 340 | int (*early_wake_up_fnc)(struct mdss_mdp_ctl *ctl); |
| 341 | |
| 342 | /* |
| 343 | * reconfigure interface for new resolution, called before (pre=1) |
| 344 | * and after interface has been reconfigured (pre=0) |
| 345 | */ |
| 346 | int (*reconfigure)(struct mdss_mdp_ctl *ctl, |
| 347 | enum dynamic_switch_modes mode, bool pre); |
| 348 | /* called before do any register programming from commit thread */ |
| 349 | void (*pre_programming)(struct mdss_mdp_ctl *ctl); |
| 350 | |
| 351 | /* to update lineptr, [1..yres] - enable, 0 - disable */ |
| 352 | int (*update_lineptr)(struct mdss_mdp_ctl *ctl, bool enable); |
| 353 | }; |
| 354 | |
| 355 | /* FRC info used for Deterministic Frame Rate Control */ |
| 356 | #define FRC_CADENCE_22_RATIO 2000000000u /* 30fps -> 60fps, 29.97 -> 59.94 */ |
| 357 | #define FRC_CADENCE_22_RATIO_LOW 1940000000u |
| 358 | #define FRC_CADENCE_22_RATIO_HIGH 2060000000u |
| 359 | |
| 360 | #define FRC_CADENCE_23_RATIO 2500000000u /* 24fps -> 60fps, 23.976 -> 59.94 */ |
| 361 | #define FRC_CADENCE_23_RATIO_LOW 2450000000u |
| 362 | #define FRC_CADENCE_23_RATIO_HIGH 2550000000u |
| 363 | |
| 364 | #define FRC_CADENCE_23223_RATIO 2400000000u /* 25fps -> 60fps */ |
| 365 | #define FRC_CADENCE_23223_RATIO_LOW 2360000000u |
| 366 | #define FRC_CADENCE_23223_RATIO_HIGH 2440000000u |
| 367 | |
| 368 | #define FRC_VIDEO_TS_DELTA_THRESHOLD_US (16666 * 10) /* 10 frames at 60fps */ |
| 369 | |
| 370 | /* |
| 371 | * In current FRC design, the minimum video fps change we can support is 24fps |
| 372 | * to 25fps, so the timestamp delta per frame is 1667. Use this threshold to |
| 373 | * catch this case and ignore more trivial video fps variations. |
| 374 | */ |
| 375 | #define FRC_VIDEO_FPS_CHANGE_THRESHOLD_US 1667 |
| 376 | |
| 377 | /* how many samples we need for video |
| 378 | * fps calculation |
| 379 | */ |
| 380 | #define FRC_VIDEO_FPS_DETECT_WINDOW 32 |
| 381 | |
| 382 | /* |
| 383 | * Experimental value. Mininum vsync counts during video's single update could |
| 384 | * be thought of as pause. If video fps is 10fps and display is 60fps, every |
| 385 | * video frame should arrive per 6 vsync, and add 2 more vsync delay, each frame |
| 386 | * should arrive in at most 8 vsync interval, otherwise it's considered as a |
| 387 | * pause. This value might need tuning in some cases. |
| 388 | */ |
| 389 | #define FRC_VIDEO_PAUSE_THRESHOLD 8 |
| 390 | |
| 391 | #define FRC_MAX_VIDEO_DROPPING_CNT 10 /* how many drops before we disable FRC */ |
| 392 | #define FRC_VIDEO_DROP_TOLERANCE_WINDOW 1000 /* how many frames to count drop */ |
| 393 | |
| 394 | /* DONOT change the definition order. __check_known_cadence depends on it */ |
| 395 | enum { |
| 396 | FRC_CADENCE_NONE = 0, /* Waiting for samples to compute cadence */ |
| 397 | FRC_CADENCE_23, |
| 398 | FRC_CADENCE_22, |
| 399 | FRC_CADENCE_23223, |
| 400 | FRC_CADENCE_FREE_RUN, /* No extra repeat, but wait for changes */ |
| 401 | FRC_CADENCE_DISABLE, /* FRC disabled, no extra repeat */ |
| 402 | }; |
| 403 | #define FRC_MAX_SUPPORT_CADENCE FRC_CADENCE_FREE_RUN |
| 404 | |
| 405 | #define FRC_CADENCE_SEQUENCE_MAX_LEN 5 /* 5 -> 23223 */ |
| 406 | #define FRC_CADENCE_SEQUENCE_MAX_RETRY 5 /* max retry of matching sequence */ |
| 407 | |
| 408 | /* sequence generator for pre-defined cadence */ |
| 409 | struct mdss_mdp_frc_seq_gen { |
| 410 | int seq[FRC_CADENCE_SEQUENCE_MAX_LEN]; |
| 411 | int cache[FRC_CADENCE_SEQUENCE_MAX_LEN]; /* 0 -> this slot is empty */ |
| 412 | int len; |
| 413 | int pos; /* current position in seq, < 0 -> pattern not matched */ |
| 414 | int base; |
| 415 | int retry; |
| 416 | }; |
| 417 | |
| 418 | struct mdss_mdp_frc_data { |
| 419 | u32 frame_cnt; /* video frame count */ |
| 420 | s64 timestamp; /* video timestamp in millisecond */ |
| 421 | }; |
| 422 | |
| 423 | struct mdss_mdp_frc_video_stat { |
| 424 | u32 frame_cnt; /* video frame count */ |
| 425 | s64 timestamp; /* video timestamp in millisecond */ |
| 426 | s64 last_delta; |
| 427 | }; |
| 428 | |
| 429 | struct mdss_mdp_frc_drop_stat { |
| 430 | u32 drop_cnt; /* how many video buffer drop */ |
| 431 | u32 frame_cnt; /* the first frame cnt where drop happens */ |
| 432 | }; |
| 433 | |
| 434 | /* how many samples at least we need for |
| 435 | * cadence detection |
| 436 | */ |
| 437 | #define FRC_CADENCE_DETECT_WINDOW 6 |
| 438 | |
| 439 | struct mdss_mdp_frc_cadence_calc { |
| 440 | struct mdss_mdp_frc_data samples[FRC_CADENCE_DETECT_WINDOW]; |
| 441 | int sample_cnt; |
| 442 | }; |
| 443 | |
| 444 | struct mdss_mdp_frc_info { |
| 445 | u32 cadence_id; /* patterns such as 22/23/23223 */ |
| 446 | u32 display_fp1000s; |
| 447 | u32 last_vsync_cnt; /* vsync when we kicked off last frame */ |
| 448 | u32 last_repeat; /* how many times last frame was repeated */ |
| 449 | u32 base_vsync_cnt; |
| 450 | struct mdss_mdp_frc_data cur_frc; |
| 451 | struct mdss_mdp_frc_data last_frc; |
| 452 | struct mdss_mdp_frc_data base_frc; |
| 453 | struct mdss_mdp_frc_video_stat video_stat; |
| 454 | struct mdss_mdp_frc_drop_stat drop_stat; |
| 455 | struct mdss_mdp_frc_cadence_calc calc; |
| 456 | struct mdss_mdp_frc_seq_gen gen; |
| 457 | }; |
| 458 | |
| 459 | /* |
| 460 | * FSM used in deterministic frame rate control: |
| 461 | * |
| 462 | * +----------------+ +----------------+ |
| 463 | * | +------------+ | too many drops | +------------+ | |
| 464 | * +--------> | INIT | +----------------------> | DISABLE | | |
| 465 | * | | +------------+ <-----------+ | +------------+ | |
| 466 | * | +----------------+ | +----------------+ |
| 467 | * | | | | |
| 468 | * | | | | change |
| 469 | * | frame| |change +----------------+ |
| 470 | * | | | | |
| 471 | * | | | | |
| 472 | * | +--v--------+----+ +-----+----------+ |
| 473 | * change| | | not supported | | |
| 474 | * | | CADENCE_DETECT +----------------------> FREE_RUN | |
| 475 | * | | | | | |
| 476 | * | +-------+--------+ +----------------+ |
| 477 | * | | |
| 478 | * | | |
| 479 | * | |cadence detected |
| 480 | * | | |
| 481 | * | | |
| 482 | * | +-------v--------+ +----------------------------+ |
| 483 | * | | | |Events: | |
| 484 | * +--------+ SEQ_MATCH | | 1. change: some changes | |
| 485 | * | | | | might change cadence like | |
| 486 | * | +-------+--------+ | video/display fps. | |
| 487 | * | | | 2. frame: video frame with| |
| 488 | * | |sequence matched | correct FRC info. | |
| 489 | * | | | 3. in other states than | |
| 490 | * | +-------v--------+ | INIT frame event doesn't | |
| 491 | * | | | | make any state change. | |
| 492 | * | | | +----------------------------+ |
| 493 | * +--------+ READY | |
| 494 | * | | |
| 495 | * +----------------+ |
| 496 | */ |
| 497 | enum mdss_mdp_frc_state_type { |
| 498 | FRC_STATE_INIT = 0, /* INIT state waiting for frames */ |
| 499 | FRC_STATE_CADENCE_DETECT, /* state to detect cadence ID */ |
| 500 | FRC_STATE_SEQ_MATCH, /* state to find start pos in cadence sequence */ |
| 501 | FRC_STATE_FREERUN, /* state has no extra repeat but might be changed */ |
| 502 | FRC_STATE_READY, /* state ready to do FRC */ |
| 503 | FRC_STATE_DISABLE, /* state in which FRC is disabled */ |
| 504 | FRC_STATE_MAX, |
| 505 | }; |
| 506 | |
| 507 | struct mdss_mdp_frc_fsm; |
| 508 | |
| 509 | struct mdss_mdp_frc_fsm_ops { |
| 510 | /* preprocess incoming FRC info like checking fps changes */ |
| 511 | void (*pre_frc)(struct mdss_mdp_frc_fsm *frc_fsm, void *arg); |
| 512 | /* deterministic frame rate control like delaying frame's display */ |
| 513 | void (*do_frc)(struct mdss_mdp_frc_fsm *frc_fsm, void *arg); |
| 514 | /* post-operations after FRC like saving past info */ |
| 515 | void (*post_frc)(struct mdss_mdp_frc_fsm *frc_fsm, void *arg); |
| 516 | }; |
| 517 | |
| 518 | struct mdss_mdp_frc_fsm_cbs { |
| 519 | /* callback used once updating FRC FSM's state */ |
| 520 | void (*update_state_cb)(struct mdss_mdp_frc_fsm *frc_fsm); |
| 521 | }; |
| 522 | |
| 523 | struct mdss_mdp_frc_fsm_state { |
| 524 | char *name; /* debug name of current state */ |
| 525 | enum mdss_mdp_frc_state_type state; /* current state type */ |
| 526 | struct mdss_mdp_frc_fsm_ops ops; /* operations of curent state */ |
| 527 | }; |
| 528 | |
| 529 | struct mdss_mdp_frc_fsm { |
| 530 | bool enable; /* whether FRC is running */ |
| 531 | struct mdss_mdp_frc_fsm_state state; /* current state */ |
| 532 | struct mdss_mdp_frc_fsm_state to_state; /* state to set */ |
| 533 | struct mdss_mdp_frc_fsm_cbs cbs; |
| 534 | struct mdss_mdp_frc_info frc_info; |
| 535 | }; |
| 536 | |
| 537 | struct mdss_mdp_ctl { |
| 538 | u32 num; |
| 539 | char __iomem *base; |
| 540 | |
| 541 | u32 ref_cnt; |
| 542 | int power_state; |
| 543 | |
| 544 | u32 intf_num; |
| 545 | u32 slave_intf_num; /* ping-pong split */ |
| 546 | u32 intf_type; |
| 547 | |
| 548 | /* |
| 549 | * false: for sctl in DUAL_LM_DUAL_DISPLAY |
| 550 | * true: everything else |
| 551 | */ |
| 552 | bool is_master; |
| 553 | |
| 554 | u32 opmode; |
| 555 | u32 flush_bits; |
| 556 | u32 flush_reg_data; |
| 557 | |
| 558 | bool split_flush_en; |
| 559 | bool is_video_mode; |
| 560 | u32 play_cnt; |
| 561 | u32 vsync_cnt; |
| 562 | u32 underrun_cnt; |
| 563 | |
| 564 | struct work_struct cpu_pm_work; |
| 565 | int autorefresh_frame_cnt; |
| 566 | |
| 567 | u16 width; |
| 568 | u16 height; |
| 569 | u16 border_x_off; |
| 570 | u16 border_y_off; |
| 571 | bool is_secure; |
| 572 | |
| 573 | /* used for WFD */ |
| 574 | u32 dst_format; |
| 575 | enum mdss_mdp_csc_type csc_type; |
| 576 | struct mult_factor dst_comp_ratio; |
| 577 | |
| 578 | u32 clk_rate; |
| 579 | int force_screen_state; |
| 580 | struct mdss_mdp_perf_params cur_perf; |
| 581 | struct mdss_mdp_perf_params new_perf; |
| 582 | u32 perf_transaction_status; |
| 583 | bool perf_release_ctl_bw; |
| 584 | u64 bw_pending; |
| 585 | bool disable_prefill; |
| 586 | |
| 587 | bool traffic_shaper_enabled; |
| 588 | u32 traffic_shaper_mdp_clk; |
| 589 | |
| 590 | struct mdss_data_type *mdata; |
| 591 | struct msm_fb_data_type *mfd; |
| 592 | struct mdss_mdp_mixer *mixer_left; |
| 593 | struct mdss_mdp_mixer *mixer_right; |
| 594 | struct mdss_mdp_cdm *cdm; |
| 595 | struct mutex lock; |
| 596 | struct mutex offlock; |
| 597 | struct mutex flush_lock; |
| 598 | struct mutex *shared_lock; |
| 599 | struct mutex rsrc_lock; |
| 600 | spinlock_t spin_lock; |
| 601 | |
| 602 | struct mdss_panel_data *panel_data; |
| 603 | struct mdss_mdp_vsync_handler vsync_handler; |
| 604 | struct mdss_mdp_vsync_handler recover_underrun_handler; |
| 605 | struct work_struct recover_work; |
| 606 | struct work_struct remove_underrun_handler; |
| 607 | |
| 608 | struct mdss_mdp_lineptr_handler lineptr_handler; |
| 609 | |
| 610 | /* |
| 611 | * This ROI is aligned to as per following guidelines and |
| 612 | * sent to the panel driver. |
| 613 | * |
| 614 | * 1. DUAL_LM_DUAL_DISPLAY |
| 615 | * Panel = 1440x2560 |
| 616 | * CTL0 = 720x2560 (LM0=720x2560) |
| 617 | * CTL1 = 720x2560 (LM1=720x2560) |
| 618 | * Both CTL's ROI will be (0-719)x(0-2599) |
| 619 | * 2. DUAL_LM_SINGLE_DISPLAY |
| 620 | * Panel = 1440x2560 |
| 621 | * CTL0 = 1440x2560 (LM0=720x2560 and LM1=720x2560) |
| 622 | * CTL0's ROI will be (0-1429)x(0-2599) |
| 623 | * 3. SINGLE_LM_SINGLE_DISPLAY |
| 624 | * Panel = 1080x1920 |
| 625 | * CTL0 = 1080x1920 (LM0=1080x1920) |
| 626 | * CTL0's ROI will be (0-1079)x(0-1919) |
| 627 | */ |
| 628 | struct mdss_rect roi; |
| 629 | struct mdss_rect roi_bkup; |
| 630 | |
| 631 | struct blocking_notifier_head notifier_head; |
| 632 | |
| 633 | void *priv_data; |
| 634 | void *intf_ctx[2]; |
| 635 | u32 wb_type; |
| 636 | |
| 637 | struct mdss_mdp_writeback *wb; |
| 638 | |
| 639 | struct mdss_mdp_ctl_intfs_ops ops; |
| 640 | bool force_ctl_start; |
| 641 | |
| 642 | u64 last_input_time; |
| 643 | int pending_mode_switch; |
| 644 | u16 frame_rate; |
| 645 | |
| 646 | /* dynamic resolution switch during cont-splash handoff */ |
| 647 | bool switch_with_handoff; |
| 648 | |
| 649 | /* vsync handler for FRC */ |
| 650 | struct mdss_mdp_vsync_handler frc_vsync_handler; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 651 | }; |
| 652 | |
| 653 | struct mdss_mdp_mixer { |
| 654 | u32 num; |
| 655 | u32 ref_cnt; |
| 656 | char __iomem *base; |
| 657 | char __iomem *dspp_base; |
| 658 | char __iomem *pingpong_base; |
| 659 | u8 type; |
| 660 | u8 params_changed; |
| 661 | u16 width; |
| 662 | u16 height; |
| 663 | |
| 664 | bool valid_roi; |
| 665 | bool roi_changed; |
| 666 | struct mdss_rect roi; |
| 667 | |
| 668 | u8 cursor_enabled; |
| 669 | u16 cursor_hotx; |
| 670 | u16 cursor_hoty; |
| 671 | u8 rotator_mode; |
| 672 | |
| 673 | /* |
| 674 | * src_split_req is valid only for right layer mixer. |
| 675 | * |
| 676 | * VIDEO mode panels: Always true if source split is enabled. |
| 677 | * CMD mode panels: Only true if source split is enabled and |
| 678 | * for a given commit left and right both ROIs |
| 679 | * are valid. |
| 680 | */ |
| 681 | bool src_split_req; |
| 682 | bool is_right_mixer; |
| 683 | struct mdss_mdp_ctl *ctl; |
| 684 | struct mdss_mdp_pipe *stage_pipe[MAX_PIPES_PER_LM]; |
| 685 | u32 next_pipe_map; |
| 686 | u32 pipe_mapped; |
| 687 | }; |
| 688 | |
| 689 | struct mdss_mdp_format_params { |
| 690 | u32 format; |
| 691 | u32 flag; |
| 692 | u8 is_yuv; |
| 693 | |
| 694 | u8 frame_format; |
| 695 | u8 chroma_sample; |
| 696 | u8 solid_fill; |
| 697 | u8 fetch_planes; |
| 698 | u8 unpack_align_msb; /* 0 to LSB, 1 to MSB */ |
| 699 | u8 unpack_tight; /* 0 for loose, 1 for tight */ |
| 700 | u8 unpack_count; /* 0 = 1 component, 1 = 2 component ... */ |
| 701 | u8 bpp; |
| 702 | u8 alpha_enable; /* source has alpha */ |
| 703 | u8 fetch_mode; |
| 704 | u8 bits[MAX_PLANES]; |
| 705 | u8 element[MAX_PLANES]; |
| 706 | u8 unpack_dx_format; /*1 for 10 bit format otherwise 0 */ |
| 707 | }; |
| 708 | |
| 709 | struct mdss_mdp_format_ubwc_tile_info { |
| 710 | u16 tile_height; |
| 711 | u16 tile_width; |
| 712 | }; |
| 713 | |
| 714 | struct mdss_mdp_format_params_ubwc { |
| 715 | struct mdss_mdp_format_params mdp_format; |
| 716 | struct mdss_mdp_format_ubwc_tile_info micro; |
| 717 | }; |
| 718 | |
| 719 | struct mdss_mdp_plane_sizes { |
| 720 | u32 num_planes; |
| 721 | u32 plane_size[MAX_PLANES]; |
| 722 | u32 total_size; |
| 723 | u32 ystride[MAX_PLANES]; |
| 724 | u32 rau_cnt; |
| 725 | u32 rau_h[2]; |
| 726 | }; |
| 727 | |
| 728 | struct mdss_mdp_img_data { |
| 729 | dma_addr_t addr; |
| 730 | unsigned long len; |
| 731 | u32 offset; |
| 732 | u32 flags; |
| 733 | u32 dir; |
| 734 | u32 domain; |
| 735 | bool mapped; |
| 736 | bool skip_detach; |
| 737 | struct fd srcp_f; |
| 738 | struct dma_buf *srcp_dma_buf; |
| 739 | struct dma_buf_attachment *srcp_attachment; |
| 740 | struct sg_table *srcp_table; |
| 741 | }; |
| 742 | |
| 743 | enum mdss_mdp_data_state { |
| 744 | MDP_BUF_STATE_UNUSED, |
| 745 | MDP_BUF_STATE_READY, |
| 746 | MDP_BUF_STATE_ACTIVE, |
| 747 | MDP_BUF_STATE_CLEANUP, |
| 748 | }; |
| 749 | |
| 750 | struct mdss_mdp_data { |
| 751 | enum mdss_mdp_data_state state; |
| 752 | u8 num_planes; |
| 753 | struct mdss_mdp_img_data p[MAX_PLANES]; |
| 754 | struct list_head buf_list; |
| 755 | struct list_head pipe_list; |
| 756 | struct list_head chunk_list; |
| 757 | u64 last_alloc; |
| 758 | u64 last_freed; |
| 759 | struct mdss_mdp_pipe *last_pipe; |
| 760 | }; |
| 761 | |
| 762 | struct pp_hist_col_info { |
| 763 | u32 col_state; |
| 764 | u32 col_en; |
| 765 | u32 hist_cnt_read; |
| 766 | u32 hist_cnt_sent; |
| 767 | u32 hist_cnt_time; |
| 768 | u32 frame_cnt; |
| 769 | u32 data[HIST_V_SIZE]; |
| 770 | struct mutex hist_mutex; |
| 771 | spinlock_t hist_lock; |
| 772 | char __iomem *base; |
| 773 | u32 intr_shift; |
| 774 | u32 disp_num; |
| 775 | struct mdss_mdp_ctl *ctl; |
| 776 | }; |
| 777 | |
| 778 | struct mdss_mdp_ad { |
| 779 | char __iomem *base; |
| 780 | u8 num; |
| 781 | }; |
| 782 | |
| 783 | struct mdss_ad_info { |
| 784 | u8 num; |
| 785 | u8 calc_hw_num; |
| 786 | u32 ops; |
| 787 | u32 sts; |
| 788 | u32 reg_sts; |
| 789 | u32 state; |
| 790 | u32 ad_data; |
| 791 | u32 ad_data_mode; |
| 792 | struct mdss_ad_init init; |
| 793 | struct mdss_ad_cfg cfg; |
| 794 | struct mutex lock; |
| 795 | struct work_struct calc_work; |
| 796 | struct msm_fb_data_type *mfd; |
| 797 | struct msm_fb_data_type *bl_mfd; |
| 798 | struct mdss_mdp_vsync_handler handle; |
| 799 | u32 last_str; |
| 800 | u32 last_bl; |
| 801 | u32 last_ad_data; |
| 802 | u16 last_calib[4]; |
| 803 | bool last_ad_data_valid; |
| 804 | bool last_calib_valid; |
| 805 | u32 ipc_frame_count; |
| 806 | u32 bl_data; |
| 807 | u32 calc_itr; |
| 808 | uint32_t bl_lin[AD_BL_LIN_LEN]; |
| 809 | uint32_t bl_lin_inv[AD_BL_LIN_LEN]; |
| 810 | uint32_t bl_att_lut[AD_BL_ATT_LUT_LEN]; |
| 811 | }; |
| 812 | |
| 813 | struct pp_sts_type { |
| 814 | u32 pa_sts; |
| 815 | u32 pcc_sts; |
| 816 | u32 igc_sts; |
| 817 | u32 igc_tbl_idx; |
| 818 | u32 argc_sts; |
| 819 | u32 enhist_sts; |
| 820 | u32 dither_sts; |
| 821 | u32 gamut_sts; |
| 822 | u32 pgc_sts; |
| 823 | u32 sharp_sts; |
| 824 | u32 hist_sts; |
| 825 | u32 side_sts; |
| 826 | }; |
| 827 | |
| 828 | struct mdss_pipe_pp_res { |
| 829 | u32 igc_c0_c1[IGC_LUT_ENTRIES]; |
| 830 | u32 igc_c2[IGC_LUT_ENTRIES]; |
| 831 | u32 hist_lut[ENHIST_LUT_ENTRIES]; |
| 832 | struct pp_hist_col_info hist; |
| 833 | struct pp_sts_type pp_sts; |
| 834 | void *pa_cfg_payload; |
| 835 | void *pcc_cfg_payload; |
| 836 | void *igc_cfg_payload; |
| 837 | void *hist_lut_cfg_payload; |
| 838 | }; |
| 839 | |
| 840 | struct mdss_mdp_pipe_smp_map { |
| 841 | DECLARE_BITMAP(reserved, MAX_DRV_SUP_MMB_BLKS); |
| 842 | DECLARE_BITMAP(allocated, MAX_DRV_SUP_MMB_BLKS); |
| 843 | DECLARE_BITMAP(fixed, MAX_DRV_SUP_MMB_BLKS); |
| 844 | }; |
| 845 | |
| 846 | struct mdss_mdp_shared_reg_ctrl { |
| 847 | u32 reg_off; |
| 848 | u32 bit_off; |
| 849 | }; |
| 850 | |
| 851 | enum mdss_mdp_pipe_rect { |
| 852 | MDSS_MDP_PIPE_RECT0, /* default */ |
| 853 | MDSS_MDP_PIPE_RECT1, |
| 854 | MDSS_MDP_PIPE_MAX_RECTS, |
| 855 | }; |
| 856 | |
| 857 | /** |
| 858 | * enum mdss_mdp_pipe_multirect_mode - pipe multirect mode |
| 859 | * @MDSS_MDP_PIPE_MULTIRECT_NONE: pipe is not working in multirect mode |
| 860 | * @MDSS_MDP_PIPE_MULTIRECT_PARALLEL: rectangles are being fetched at the |
| 861 | * same time in time multiplexed fashion |
| 862 | * @MDSS_MDP_PIPE_MULTIRECT_SERIAL: rectangles are fetched serially, where |
| 863 | * one is only fetched after the other one |
| 864 | * is complete |
| 865 | */ |
| 866 | enum mdss_mdp_pipe_multirect_mode { |
| 867 | MDSS_MDP_PIPE_MULTIRECT_NONE, |
| 868 | MDSS_MDP_PIPE_MULTIRECT_PARALLEL, |
| 869 | MDSS_MDP_PIPE_MULTIRECT_SERIAL, |
| 870 | }; |
| 871 | |
| 872 | /** |
| 873 | * struct mdss_mdp_pipe_multirect_params - multirect info for layer or pipe |
| 874 | * @num: rectangle being operated, default is RECT0 if pipe doesn't |
| 875 | * support multirect |
| 876 | * @mode: mode of multirect operation, default is NONE |
| 877 | * @next: pointer to sibling pipe/layer which is also operating in |
| 878 | * multirect mode |
| 879 | */ |
| 880 | struct mdss_mdp_pipe_multirect_params { |
| 881 | enum mdss_mdp_pipe_rect num; /* RECT0 or RECT1 */ |
| 882 | int max_rects; |
| 883 | enum mdss_mdp_pipe_multirect_mode mode; |
| 884 | void *next; /* pointer to next pipe or layer */ |
| 885 | }; |
| 886 | |
| 887 | struct mdss_mdp_pipe { |
| 888 | u32 num; |
| 889 | u32 type; |
| 890 | u32 ndx; |
| 891 | u8 priority; |
| 892 | char __iomem *base; |
| 893 | u32 ftch_id; |
| 894 | u32 xin_id; |
| 895 | u32 panic_ctrl_ndx; |
| 896 | struct mdss_mdp_shared_reg_ctrl clk_ctrl; |
| 897 | struct mdss_mdp_shared_reg_ctrl clk_status; |
| 898 | struct mdss_mdp_shared_reg_ctrl sw_reset; |
| 899 | |
| 900 | struct kref kref; |
| 901 | |
| 902 | u32 play_cnt; |
| 903 | struct file *file; |
| 904 | bool is_handed_off; |
| 905 | |
| 906 | u32 flags; |
| 907 | u32 bwc_mode; |
| 908 | |
| 909 | /* valid only when pipe's output is crossing both layer mixers */ |
| 910 | bool src_split_req; |
| 911 | bool is_right_blend; |
| 912 | |
| 913 | u16 img_width; |
| 914 | u16 img_height; |
| 915 | u8 horz_deci; |
| 916 | u8 vert_deci; |
| 917 | struct mdss_rect src; |
| 918 | struct mdss_rect dst; |
| 919 | struct mdss_mdp_format_params *src_fmt; |
| 920 | struct mdss_mdp_plane_sizes src_planes; |
| 921 | |
| 922 | /* compression ratio from the source format */ |
| 923 | struct mult_factor comp_ratio; |
| 924 | |
| 925 | enum mdss_mdp_stage_index mixer_stage; |
| 926 | u8 is_fg; |
| 927 | u8 alpha; |
| 928 | u8 blend_op; |
| 929 | u8 overfetch_disable; |
| 930 | u32 transp; |
| 931 | u32 bg_color; |
| 932 | |
| 933 | struct msm_fb_data_type *mfd; |
| 934 | struct mdss_mdp_mixer *mixer_left; |
| 935 | struct mdss_mdp_mixer *mixer_right; |
| 936 | |
| 937 | struct mdp_overlay req_data; |
| 938 | struct mdp_input_layer layer; |
| 939 | u32 params_changed; |
| 940 | bool dirty; |
| 941 | bool unhalted; |
| 942 | bool async_update; |
| 943 | |
| 944 | struct mdss_mdp_pipe_smp_map smp_map[MAX_PLANES]; |
| 945 | |
| 946 | struct list_head buf_queue; |
| 947 | struct list_head list; |
| 948 | |
| 949 | struct mdp_overlay_pp_params pp_cfg; |
| 950 | struct mdss_pipe_pp_res pp_res; |
| 951 | struct mdp_scale_data_v2 scaler; |
| 952 | u8 chroma_sample_h; |
| 953 | u8 chroma_sample_v; |
| 954 | |
| 955 | wait_queue_head_t free_waitq; |
| 956 | u32 frame_rate; |
| 957 | u8 csc_coeff_set; |
| 958 | u8 supported_formats[BITS_TO_BYTES(MDP_IMGTYPE_LIMIT1)]; |
| 959 | |
| 960 | struct mdss_mdp_pipe_multirect_params multirect; |
| 961 | }; |
| 962 | |
| 963 | struct mdss_mdp_writeback_arg { |
| 964 | struct mdss_mdp_data *data; |
| 965 | void *priv_data; |
| 966 | }; |
| 967 | |
| 968 | struct mdss_mdp_wfd; |
| 969 | |
| 970 | struct mdss_overlay_private { |
| 971 | ktime_t vsync_time; |
| 972 | ktime_t lineptr_time; |
| 973 | struct kernfs_node *vsync_event_sd; |
| 974 | struct kernfs_node *lineptr_event_sd; |
| 975 | struct kernfs_node *hist_event_sd; |
| 976 | struct kernfs_node *bl_event_sd; |
| 977 | struct kernfs_node *ad_event_sd; |
| 978 | struct kernfs_node *ad_bl_event_sd; |
| 979 | int borderfill_enable; |
| 980 | int hw_refresh; |
| 981 | void *cpu_pm_hdl; |
| 982 | |
| 983 | struct mdss_data_type *mdata; |
| 984 | struct mutex ov_lock; |
| 985 | struct mutex dfps_lock; |
| 986 | struct mdss_mdp_ctl *ctl; |
| 987 | struct mdss_mdp_wfd *wfd; |
| 988 | |
| 989 | struct mutex list_lock; |
| 990 | struct list_head pipes_used; |
| 991 | struct list_head pipes_cleanup; |
| 992 | struct list_head pipes_destroy; |
| 993 | struct list_head rot_proc_list; |
| 994 | bool mixer_swap; |
| 995 | u32 resources_state; |
| 996 | |
| 997 | /* list of buffers that can be reused */ |
| 998 | struct list_head bufs_chunks; |
| 999 | struct list_head bufs_pool; |
| 1000 | struct list_head bufs_used; |
| 1001 | /* list of buffers which should be freed during cleanup stage */ |
| 1002 | struct list_head bufs_freelist; |
| 1003 | |
| 1004 | int ad_state; |
| 1005 | int dyn_pu_state; |
| 1006 | |
| 1007 | bool handoff; |
| 1008 | u32 splash_mem_addr; |
| 1009 | u32 splash_mem_size; |
| 1010 | u32 sd_enabled; |
| 1011 | |
Sachin Bhayare | 2b6d004 | 2018-01-13 19:38:21 +0530 | [diff] [blame] | 1012 | struct mdss_timeline *vsync_timeline; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1013 | struct mdss_mdp_vsync_handler vsync_retire_handler; |
| 1014 | int retire_cnt; |
| 1015 | bool kickoff_released; |
| 1016 | u32 cursor_ndx[2]; |
| 1017 | u32 hist_events; |
| 1018 | u32 bl_events; |
| 1019 | u32 ad_events; |
| 1020 | u32 ad_bl_events; |
| 1021 | |
| 1022 | bool allow_kickoff; |
| 1023 | |
| 1024 | /* video frame info used by deterministic frame rate control */ |
| 1025 | struct mdss_mdp_frc_fsm *frc_fsm; |
| 1026 | u8 sd_transition_state; |
| 1027 | struct kthread_worker worker; |
| 1028 | struct kthread_work vsync_work; |
| 1029 | struct task_struct *thread; |
| 1030 | }; |
| 1031 | |
| 1032 | struct mdss_mdp_set_ot_params { |
| 1033 | u32 xin_id; |
| 1034 | u32 num; |
| 1035 | u32 width; |
| 1036 | u32 height; |
| 1037 | u16 frame_rate; |
| 1038 | bool is_rot; |
| 1039 | bool is_wb; |
| 1040 | bool is_yuv; |
| 1041 | bool is_vbif_nrt; |
| 1042 | u32 reg_off_vbif_lim_conf; |
| 1043 | u32 reg_off_mdp_clk_ctrl; |
| 1044 | u32 bit_off_mdp_clk_ctrl; |
| 1045 | }; |
| 1046 | |
| 1047 | struct mdss_mdp_commit_cb { |
| 1048 | void *data; |
| 1049 | int (*commit_cb_fnc)(enum mdp_commit_stage_type commit_state, |
| 1050 | void *data); |
| 1051 | }; |
| 1052 | |
| 1053 | /** |
| 1054 | * enum mdss_screen_state - Screen states that MDP can be forced into |
| 1055 | * |
| 1056 | * @MDSS_SCREEN_DEFAULT: Do not force MDP into any screen state. |
| 1057 | * @MDSS_SCREEN_FORCE_BLANK: Force MDP to generate blank color fill screen. |
| 1058 | */ |
| 1059 | enum mdss_screen_state { |
| 1060 | MDSS_SCREEN_DEFAULT, |
| 1061 | MDSS_SCREEN_FORCE_BLANK, |
| 1062 | }; |
| 1063 | |
| 1064 | /** |
| 1065 | * enum mdss_mdp_clt_intf_event_flags - flags specifying how event to should |
| 1066 | * be sent to panel drivers. |
| 1067 | * |
| 1068 | * @CTL_INTF_EVENT_FLAG_DEFAULT: this flag denotes default behaviour where |
| 1069 | * event will be send to all panels attached this |
| 1070 | * display, recursively in split-DSI. |
| 1071 | * @CTL_INTF_EVENT_FLAG_SKIP_BROADCAST: this flag sends event only to panel |
| 1072 | * associated with this ctl. |
| 1073 | * @CTL_INTF_EVENT_FLAG_SLAVE_INTF: this flag sends event only to slave panel |
| 1074 | * associated with this ctl, i.e pingpong-split |
| 1075 | */ |
| 1076 | enum mdss_mdp_clt_intf_event_flags { |
| 1077 | CTL_INTF_EVENT_FLAG_DEFAULT = 0, |
| 1078 | CTL_INTF_EVENT_FLAG_SKIP_BROADCAST = BIT(1), |
| 1079 | CTL_INTF_EVENT_FLAG_SLAVE_INTF = BIT(2), |
| 1080 | }; |
| 1081 | |
| 1082 | #define mfd_to_mdp5_data(mfd) (mfd->mdp.private1) |
| 1083 | #define mfd_to_mdata(mfd) (((struct mdss_overlay_private *)\ |
| 1084 | (mfd->mdp.private1))->mdata) |
| 1085 | #define mfd_to_ctl(mfd) (((struct mdss_overlay_private *)\ |
| 1086 | (mfd->mdp.private1))->ctl) |
| 1087 | #define mfd_to_wb(mfd) (((struct mdss_overlay_private *)\ |
| 1088 | (mfd->mdp.private1))->wb) |
| 1089 | |
| 1090 | /** |
| 1091 | * - mdss_mdp_is_roi_changed |
| 1092 | * @mfd - pointer to mfd |
| 1093 | * |
| 1094 | * Function returns true if roi is changed for any layer mixer of a given |
| 1095 | * display, false otherwise. |
| 1096 | */ |
| 1097 | static inline bool mdss_mdp_is_roi_changed(struct msm_fb_data_type *mfd) |
| 1098 | { |
| 1099 | struct mdss_mdp_ctl *ctl; |
| 1100 | |
| 1101 | if (!mfd) |
| 1102 | return false; |
| 1103 | |
| 1104 | ctl = mfd_to_ctl(mfd); /* returns master ctl */ |
| 1105 | |
| 1106 | return ctl->mixer_left->roi_changed || |
| 1107 | (is_split_lm(mfd) ? ctl->mixer_right->roi_changed : false); |
| 1108 | } |
| 1109 | |
| 1110 | /** |
| 1111 | * - mdss_mdp_is_both_lm_valid |
| 1112 | * @main_ctl - pointer to a main ctl |
| 1113 | * |
| 1114 | * Function checks if both layer mixers are active or not. This can be useful |
| 1115 | * when partial update is enabled on either MDP_DUAL_LM_SINGLE_DISPLAY or |
| 1116 | * MDP_DUAL_LM_DUAL_DISPLAY . |
| 1117 | */ |
| 1118 | static inline bool mdss_mdp_is_both_lm_valid(struct mdss_mdp_ctl *main_ctl) |
| 1119 | { |
| 1120 | return (main_ctl && main_ctl->is_master && |
| 1121 | main_ctl->mixer_left && main_ctl->mixer_left->valid_roi && |
| 1122 | main_ctl->mixer_right && main_ctl->mixer_right->valid_roi); |
| 1123 | } |
| 1124 | |
| 1125 | enum mdss_mdp_pu_type { |
| 1126 | MDSS_MDP_INVALID_UPDATE = -1, |
| 1127 | MDSS_MDP_DEFAULT_UPDATE, |
| 1128 | MDSS_MDP_LEFT_ONLY_UPDATE, /* only valid for split_lm */ |
| 1129 | MDSS_MDP_RIGHT_ONLY_UPDATE, /* only valid for split_lm */ |
| 1130 | }; |
| 1131 | |
| 1132 | /* only call from master ctl */ |
| 1133 | static inline enum mdss_mdp_pu_type mdss_mdp_get_pu_type( |
| 1134 | struct mdss_mdp_ctl *mctl) |
| 1135 | { |
| 1136 | enum mdss_mdp_pu_type pu_type = MDSS_MDP_INVALID_UPDATE; |
| 1137 | |
| 1138 | if (!mctl || !mctl->is_master) |
| 1139 | return pu_type; |
| 1140 | |
| 1141 | if (!is_split_lm(mctl->mfd) || mdss_mdp_is_both_lm_valid(mctl)) |
| 1142 | pu_type = MDSS_MDP_DEFAULT_UPDATE; |
| 1143 | else if (mctl->mixer_left->valid_roi) |
| 1144 | pu_type = MDSS_MDP_LEFT_ONLY_UPDATE; |
| 1145 | else if (mctl->mixer_right->valid_roi) |
| 1146 | pu_type = MDSS_MDP_RIGHT_ONLY_UPDATE; |
| 1147 | else |
| 1148 | pr_err("%s: invalid pu_type\n", __func__); |
| 1149 | |
| 1150 | return pu_type; |
| 1151 | } |
| 1152 | |
| 1153 | static inline struct mdss_mdp_ctl *mdss_mdp_get_split_ctl( |
| 1154 | struct mdss_mdp_ctl *ctl) |
| 1155 | { |
| 1156 | if (ctl && ctl->mixer_right && (ctl->mixer_right->ctl != ctl)) |
| 1157 | return ctl->mixer_right->ctl; |
| 1158 | |
| 1159 | return NULL; |
| 1160 | } |
| 1161 | |
| 1162 | static inline struct mdss_mdp_ctl *mdss_mdp_get_main_ctl( |
| 1163 | struct mdss_mdp_ctl *sctl) |
| 1164 | { |
| 1165 | if (sctl && sctl->mfd && sctl->mixer_left && |
| 1166 | sctl->mixer_left->is_right_mixer) |
| 1167 | return mfd_to_ctl(sctl->mfd); |
| 1168 | |
| 1169 | return NULL; |
| 1170 | } |
| 1171 | |
| 1172 | static inline bool mdss_mdp_pipe_is_yuv(struct mdss_mdp_pipe *pipe) |
| 1173 | { |
| 1174 | return pipe && (pipe->type == MDSS_MDP_PIPE_TYPE_VIG); |
| 1175 | } |
| 1176 | |
| 1177 | static inline bool mdss_mdp_pipe_is_rgb(struct mdss_mdp_pipe *pipe) |
| 1178 | { |
| 1179 | return pipe && (pipe->type == MDSS_MDP_PIPE_TYPE_RGB); |
| 1180 | } |
| 1181 | |
| 1182 | static inline bool mdss_mdp_pipe_is_dma(struct mdss_mdp_pipe *pipe) |
| 1183 | { |
| 1184 | return pipe && (pipe->type == MDSS_MDP_PIPE_TYPE_DMA); |
| 1185 | } |
| 1186 | |
| 1187 | static inline void mdss_mdp_ctl_write(struct mdss_mdp_ctl *ctl, |
| 1188 | u32 reg, u32 val) |
| 1189 | { |
| 1190 | writel_relaxed(val, ctl->base + reg); |
| 1191 | } |
| 1192 | |
| 1193 | static inline u32 mdss_mdp_ctl_read(struct mdss_mdp_ctl *ctl, u32 reg) |
| 1194 | { |
| 1195 | return readl_relaxed(ctl->base + reg); |
| 1196 | } |
| 1197 | |
| 1198 | static inline void mdp_mixer_write(struct mdss_mdp_mixer *mixer, |
| 1199 | u32 reg, u32 val) |
| 1200 | { |
| 1201 | writel_relaxed(val, mixer->base + reg); |
| 1202 | } |
| 1203 | |
| 1204 | static inline u32 mdp_mixer_read(struct mdss_mdp_mixer *mixer, u32 reg) |
| 1205 | { |
| 1206 | return readl_relaxed(mixer->base + reg); |
| 1207 | } |
| 1208 | |
| 1209 | static inline void mdss_mdp_pingpong_write(char __iomem *pingpong_base, |
| 1210 | u32 reg, u32 val) |
| 1211 | { |
| 1212 | writel_relaxed(val, pingpong_base + reg); |
| 1213 | } |
| 1214 | |
| 1215 | static inline u32 mdss_mdp_pingpong_read(char __iomem *pingpong_base, u32 reg) |
| 1216 | { |
| 1217 | return readl_relaxed(pingpong_base + reg); |
| 1218 | } |
| 1219 | |
| 1220 | static inline int mdss_mdp_pipe_is_sw_reset_available( |
| 1221 | struct mdss_data_type *mdata) |
| 1222 | { |
| 1223 | switch (mdata->mdp_rev) { |
| 1224 | case MDSS_MDP_HW_REV_101_2: |
| 1225 | case MDSS_MDP_HW_REV_103_1: |
| 1226 | return true; |
| 1227 | default: |
| 1228 | return false; |
| 1229 | } |
| 1230 | } |
| 1231 | |
| 1232 | static inline int mdss_mdp_iommu_dyn_attach_supported( |
| 1233 | struct mdss_data_type *mdata) |
| 1234 | { |
| 1235 | return (mdata->mdp_rev >= MDSS_MDP_HW_REV_103); |
| 1236 | } |
| 1237 | |
| 1238 | static inline int mdss_mdp_line_buffer_width(void) |
| 1239 | { |
| 1240 | return MAX_LINE_BUFFER_WIDTH; |
| 1241 | } |
| 1242 | |
| 1243 | static inline u32 get_panel_yres(struct mdss_panel_info *pinfo) |
| 1244 | { |
| 1245 | u32 yres; |
| 1246 | |
| 1247 | yres = pinfo->yres + pinfo->lcdc.border_top + |
| 1248 | pinfo->lcdc.border_bottom; |
| 1249 | return yres; |
| 1250 | } |
| 1251 | |
| 1252 | static inline u32 get_panel_xres(struct mdss_panel_info *pinfo) |
| 1253 | { |
| 1254 | u32 xres; |
| 1255 | |
| 1256 | xres = pinfo->xres + pinfo->lcdc.border_left + |
| 1257 | pinfo->lcdc.border_right; |
| 1258 | return xres; |
| 1259 | } |
| 1260 | |
| 1261 | static inline u32 get_panel_width(struct mdss_mdp_ctl *ctl) |
| 1262 | { |
| 1263 | u32 width; |
| 1264 | |
| 1265 | width = get_panel_xres(&ctl->panel_data->panel_info); |
| 1266 | if (ctl->panel_data->next && is_pingpong_split(ctl->mfd)) |
| 1267 | width += get_panel_xres(&ctl->panel_data->next->panel_info); |
| 1268 | |
| 1269 | return width; |
| 1270 | } |
| 1271 | |
| 1272 | static inline bool mdss_mdp_req_init_restore_cfg(struct mdss_data_type *mdata) |
| 1273 | { |
| 1274 | if (IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1275 | MDSS_MDP_HW_REV_106) || |
| 1276 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1277 | MDSS_MDP_HW_REV_108) || |
| 1278 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1279 | MDSS_MDP_HW_REV_112) || |
| 1280 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1281 | MDSS_MDP_HW_REV_114) || |
| 1282 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1283 | MDSS_MDP_HW_REV_115) || |
| 1284 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1285 | MDSS_MDP_HW_REV_116)) |
| 1286 | return true; |
| 1287 | |
| 1288 | return false; |
| 1289 | } |
| 1290 | |
| 1291 | static inline int mdss_mdp_panic_signal_support_mode( |
| 1292 | struct mdss_data_type *mdata) |
| 1293 | { |
| 1294 | uint32_t signal_mode = MDSS_MDP_PANIC_NONE; |
| 1295 | |
| 1296 | if (IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1297 | MDSS_MDP_HW_REV_105) || |
| 1298 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1299 | MDSS_MDP_HW_REV_108) || |
| 1300 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1301 | MDSS_MDP_HW_REV_109) || |
| 1302 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1303 | MDSS_MDP_HW_REV_110)) |
| 1304 | signal_mode = MDSS_MDP_PANIC_COMMON_REG_CFG; |
| 1305 | else if (IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1306 | MDSS_MDP_HW_REV_107) || |
| 1307 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1308 | MDSS_MDP_HW_REV_114) || |
| 1309 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1310 | MDSS_MDP_HW_REV_115) || |
| 1311 | IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, |
| 1312 | MDSS_MDP_HW_REV_116)) |
| 1313 | signal_mode = MDSS_MDP_PANIC_PER_PIPE_CFG; |
| 1314 | |
| 1315 | return signal_mode; |
| 1316 | } |
| 1317 | |
| 1318 | static inline struct clk *mdss_mdp_get_clk(u32 clk_idx) |
| 1319 | { |
| 1320 | if (clk_idx < MDSS_MAX_CLK) |
| 1321 | return mdss_res->mdp_clk[clk_idx]; |
| 1322 | return NULL; |
| 1323 | } |
| 1324 | |
| 1325 | static inline void mdss_update_sd_client(struct mdss_data_type *mdata, |
| 1326 | unsigned int status) |
| 1327 | { |
| 1328 | if (status) |
| 1329 | atomic_inc(&mdata->sd_client_count); |
| 1330 | else |
| 1331 | atomic_add_unless(&mdss_res->sd_client_count, -1, 0); |
| 1332 | } |
| 1333 | |
| 1334 | static inline int mdss_mdp_get_wb_ctl_support(struct mdss_data_type *mdata, |
| 1335 | bool rotator_session) |
| 1336 | { |
| 1337 | /* |
| 1338 | * Any control path can be routed to any of the hardware datapaths. |
| 1339 | * But there is a HW restriction for 3D Mux block. As the 3D Mux |
| 1340 | * settings in the CTL registers are double buffered, if an interface |
| 1341 | * uses it and disconnects, then the subsequent interface which gets |
| 1342 | * connected should use the same control path in order to clear the |
| 1343 | * 3D MUX settings. |
| 1344 | * To handle this restriction, we are allowing WB also, to loop through |
| 1345 | * all the avialable control paths, so that it can reuse the control |
| 1346 | * path left by the external interface, thereby clearing the 3D Mux |
| 1347 | * settings. |
| 1348 | * The initial control paths can be used by Primary, External and WB. |
| 1349 | * The rotator can use the remaining available control paths. |
| 1350 | */ |
| 1351 | return rotator_session ? (mdata->nctl - mdata->nmixers_wb) : |
| 1352 | MDSS_MDP_CTL0; |
| 1353 | } |
| 1354 | |
| 1355 | static inline bool mdss_mdp_is_nrt_vbif_client(struct mdss_data_type *mdata, |
| 1356 | struct mdss_mdp_pipe *pipe) |
| 1357 | { |
| 1358 | return mdata->vbif_nrt_io.base && pipe->mixer_left && |
| 1359 | pipe->mixer_left->rotator_mode; |
| 1360 | } |
| 1361 | |
| 1362 | static inline bool mdss_mdp_is_nrt_ctl_path(struct mdss_mdp_ctl *ctl) |
| 1363 | { |
| 1364 | return (ctl->intf_num == MDSS_MDP_NO_INTF) || |
| 1365 | (ctl->mixer_left && ctl->mixer_left->rotator_mode); |
| 1366 | } |
| 1367 | |
| 1368 | static inline bool mdss_mdp_is_nrt_vbif_base_defined( |
| 1369 | struct mdss_data_type *mdata) |
| 1370 | { |
| 1371 | return mdata->vbif_nrt_io.base ? true : false; |
| 1372 | } |
| 1373 | |
| 1374 | static inline bool mdss_mdp_ctl_is_power_off(struct mdss_mdp_ctl *ctl) |
| 1375 | { |
| 1376 | return mdss_panel_is_power_off(ctl->power_state); |
| 1377 | } |
| 1378 | |
| 1379 | static inline bool mdss_mdp_ctl_is_power_on_interactive( |
| 1380 | struct mdss_mdp_ctl *ctl) |
| 1381 | { |
| 1382 | return mdss_panel_is_power_on_interactive(ctl->power_state); |
| 1383 | } |
| 1384 | |
| 1385 | static inline bool mdss_mdp_ctl_is_power_on(struct mdss_mdp_ctl *ctl) |
| 1386 | { |
| 1387 | return mdss_panel_is_power_on(ctl->power_state); |
| 1388 | } |
| 1389 | |
| 1390 | static inline bool mdss_mdp_ctl_is_power_on_lp(struct mdss_mdp_ctl *ctl) |
| 1391 | { |
| 1392 | return mdss_panel_is_power_on_lp(ctl->power_state); |
| 1393 | } |
| 1394 | |
| 1395 | static inline u32 left_lm_w_from_mfd(struct msm_fb_data_type *mfd) |
| 1396 | { |
| 1397 | struct mdss_mdp_ctl *ctl = mfd_to_ctl(mfd); |
| 1398 | struct mdss_panel_info *pinfo = mfd->panel_info; |
| 1399 | int width = 0; |
| 1400 | |
| 1401 | if (ctl && ctl->mixer_left) { |
| 1402 | width = ctl->mixer_left->width; |
| 1403 | width -= (pinfo->lcdc.border_left + pinfo->lcdc.border_right); |
| 1404 | pr_debug("ctl=%d mw=%d l=%d r=%d w=%d\n", |
| 1405 | ctl->num, ctl->mixer_left->width, |
| 1406 | pinfo->lcdc.border_left, pinfo->lcdc.border_right, |
| 1407 | width); |
| 1408 | } |
| 1409 | return width; |
| 1410 | } |
| 1411 | |
| 1412 | static inline bool mdss_mdp_is_tile_format(struct mdss_mdp_format_params *fmt) |
| 1413 | { |
| 1414 | return fmt && (fmt->fetch_mode == MDSS_MDP_FETCH_TILE); |
| 1415 | } |
| 1416 | |
| 1417 | static inline bool mdss_mdp_is_ubwc_format(struct mdss_mdp_format_params *fmt) |
| 1418 | { |
| 1419 | return fmt && (fmt->fetch_mode == MDSS_MDP_FETCH_UBWC); |
| 1420 | } |
| 1421 | |
| 1422 | static inline bool mdss_mdp_is_linear_format(struct mdss_mdp_format_params *fmt) |
| 1423 | { |
| 1424 | return fmt && (fmt->fetch_mode == MDSS_MDP_FETCH_LINEAR); |
| 1425 | } |
| 1426 | |
| 1427 | static inline bool mdss_mdp_is_nv12_format(struct mdss_mdp_format_params *fmt) |
| 1428 | { |
| 1429 | return fmt && (fmt->chroma_sample == MDSS_MDP_CHROMA_420) && |
| 1430 | (fmt->fetch_planes == MDSS_MDP_PLANE_PSEUDO_PLANAR); |
| 1431 | } |
| 1432 | |
| 1433 | static inline bool mdss_mdp_is_ubwc_supported(struct mdss_data_type *mdata) |
| 1434 | { |
| 1435 | return mdata->has_ubwc; |
| 1436 | } |
| 1437 | |
| 1438 | static inline bool mdss_mdp_is_wb_rotator_supported( |
| 1439 | struct mdss_data_type *mdata) |
| 1440 | { |
| 1441 | return mdata && !mdata->has_separate_rotator; |
| 1442 | } |
| 1443 | |
| 1444 | static inline int mdss_mdp_is_cdm_supported(struct mdss_data_type *mdata, |
| 1445 | u32 intf_type, u32 mixer_type) |
| 1446 | { |
| 1447 | int support = mdata->ncdm; |
| 1448 | |
| 1449 | /* |
| 1450 | * CDM is supported under these conditions |
| 1451 | * 1. If Device tree created a cdm block AND |
| 1452 | * 2. Output interface is HDMI OR Output interface is WB2 |
| 1453 | */ |
| 1454 | return support && ((intf_type == MDSS_INTF_HDMI) || |
| 1455 | ((intf_type == MDSS_MDP_NO_INTF) && |
| 1456 | ((mixer_type == MDSS_MDP_MIXER_TYPE_INTF) || |
| 1457 | (mixer_type == MDSS_MDP_MIXER_TYPE_WRITEBACK)))); |
| 1458 | } |
| 1459 | |
| 1460 | static inline u32 mdss_mdp_get_cursor_frame_size(struct mdss_data_type *mdata) |
| 1461 | { |
| 1462 | return mdata->max_cursor_size * mdata->max_cursor_size * 4; |
| 1463 | } |
| 1464 | |
| 1465 | static inline uint8_t pp_vig_csc_pipe_val(struct mdss_mdp_pipe *pipe) |
| 1466 | { |
| 1467 | switch (pipe->csc_coeff_set) { |
| 1468 | case MDP_CSC_ITU_R_601: |
| 1469 | return MDSS_MDP_CSC_YUV2RGB_601L; |
| 1470 | case MDP_CSC_ITU_R_601_FR: |
| 1471 | return MDSS_MDP_CSC_YUV2RGB_601FR; |
| 1472 | case MDP_CSC_ITU_R_2020: |
| 1473 | return MDSS_MDP_CSC_YUV2RGB_2020L; |
| 1474 | case MDP_CSC_ITU_R_2020_FR: |
| 1475 | return MDSS_MDP_CSC_YUV2RGB_2020FR; |
| 1476 | case MDP_CSC_ITU_R_709: |
| 1477 | default: |
| 1478 | return MDSS_MDP_CSC_YUV2RGB_709L; |
| 1479 | } |
| 1480 | } |
| 1481 | |
| 1482 | /* |
| 1483 | * when split_lm topology is used without 3D_Mux, either DSC_MERGE or |
| 1484 | * split_panel is used during full frame updates. Now when we go from |
| 1485 | * full frame update to right-only update, we need to disable DSC_MERGE or |
| 1486 | * split_panel. However, those are controlled through DSC0_COMMON_MODE |
| 1487 | * register which is double buffered, and this double buffer update is tied to |
| 1488 | * LM0. Now for right-only update, LM0 will not get double buffer update signal. |
| 1489 | * So DSC_MERGE or split_panel is not disabled for right-only update which is |
| 1490 | * a wrong HW state and leads ping-pong timeout. Workaround for this is to use |
| 1491 | * LM0->DSC0 pair for right-only update and disable DSC_MERGE or split_panel. |
| 1492 | * |
| 1493 | * However using LM0->DSC0 pair for right-only update requires many changes |
| 1494 | * at various levels of SW. To lower the SW impact and still support |
| 1495 | * right-only partial update, keep SW state as it is but swap mixer register |
| 1496 | * writes such that we instruct HW to use LM0->DSC0 pair. |
| 1497 | * |
| 1498 | * This function will return true if such a swap is needed or not. |
| 1499 | */ |
| 1500 | static inline bool mdss_mdp_is_lm_swap_needed(struct mdss_data_type *mdata, |
| 1501 | struct mdss_mdp_ctl *mctl) |
| 1502 | { |
| 1503 | if (!mdata || !mctl || !mctl->is_master || |
| 1504 | !mctl->panel_data || !mctl->mfd) |
| 1505 | return false; |
| 1506 | |
| 1507 | return (is_dsc_compression(&mctl->panel_data->panel_info)) && |
| 1508 | (mctl->panel_data->panel_info.partial_update_enabled) && |
| 1509 | (mdss_has_quirk(mdata, MDSS_QUIRK_DSC_RIGHT_ONLY_PU)) && |
| 1510 | ((mctl->mfd->split_mode == MDP_DUAL_LM_DUAL_DISPLAY) || |
| 1511 | ((mctl->mfd->split_mode == MDP_DUAL_LM_SINGLE_DISPLAY) && |
| 1512 | (mctl->panel_data->panel_info.dsc_enc_total == 2))) && |
| 1513 | (!mctl->mixer_left->valid_roi) && |
| 1514 | (mctl->mixer_right->valid_roi); |
| 1515 | } |
| 1516 | |
| 1517 | static inline int mdss_mdp_get_display_id(struct mdss_mdp_pipe *pipe) |
| 1518 | { |
| 1519 | return (pipe && pipe->mfd) ? pipe->mfd->index : -1; |
| 1520 | } |
| 1521 | |
| 1522 | static inline bool mdss_mdp_is_full_frame_update(struct mdss_mdp_ctl *ctl) |
| 1523 | { |
| 1524 | struct mdss_mdp_mixer *mixer; |
| 1525 | struct mdss_rect *roi; |
| 1526 | |
| 1527 | if (mdss_mdp_get_pu_type(ctl) != MDSS_MDP_DEFAULT_UPDATE) |
| 1528 | return false; |
| 1529 | |
| 1530 | if (ctl->mixer_left->valid_roi) { |
| 1531 | mixer = ctl->mixer_left; |
| 1532 | roi = &mixer->roi; |
| 1533 | if ((roi->x != 0) || (roi->y != 0) || (roi->w != mixer->width) |
| 1534 | || (roi->h != mixer->height)) |
| 1535 | return false; |
| 1536 | } |
| 1537 | |
| 1538 | if (ctl->mixer_right && ctl->mixer_right->valid_roi) { |
| 1539 | mixer = ctl->mixer_right; |
| 1540 | roi = &mixer->roi; |
| 1541 | if ((roi->x != 0) || (roi->y != 0) || (roi->w != mixer->width) |
| 1542 | || (roi->h != mixer->height)) |
| 1543 | return false; |
| 1544 | } |
| 1545 | |
| 1546 | return true; |
| 1547 | } |
| 1548 | |
| 1549 | static inline bool mdss_mdp_is_lineptr_supported(struct mdss_mdp_ctl *ctl) |
| 1550 | { |
| 1551 | struct mdss_panel_info *pinfo; |
| 1552 | |
| 1553 | if (!ctl || !ctl->mixer_left || !ctl->is_master) |
| 1554 | return false; |
| 1555 | |
| 1556 | pinfo = &ctl->panel_data->panel_info; |
| 1557 | |
| 1558 | return (ctl->is_video_mode || ((pinfo->type == MIPI_CMD_PANEL) |
| 1559 | && (pinfo->te.tear_check_en)) ? true : false); |
| 1560 | } |
| 1561 | |
| 1562 | static inline bool mdss_mdp_is_map_needed(struct mdss_data_type *mdata, |
| 1563 | struct mdss_mdp_img_data *data) |
| 1564 | { |
| 1565 | u32 is_secure_ui = data->flags & MDP_SECURE_DISPLAY_OVERLAY_SESSION; |
| 1566 | |
| 1567 | /* |
| 1568 | * For ULT Targets we need SMMU Map, to issue map call for secure Display. |
| 1569 | */ |
| 1570 | if (is_secure_ui && !mdss_has_quirk(mdata, MDSS_QUIRK_NEED_SECURE_MAP)) |
| 1571 | return false; |
| 1572 | |
| 1573 | return true; |
| 1574 | } |
| 1575 | |
| 1576 | static inline u32 mdss_mdp_get_rotator_dst_format(u32 in_format, u32 in_rot90, |
| 1577 | u32 bwc) |
| 1578 | { |
| 1579 | switch (in_format) { |
| 1580 | case MDP_RGB_565: |
| 1581 | case MDP_BGR_565: |
| 1582 | if (in_rot90) |
| 1583 | return MDP_RGB_888; |
| 1584 | else |
| 1585 | return in_format; |
| 1586 | case MDP_RGBA_8888: |
| 1587 | if (bwc) |
| 1588 | return MDP_BGRA_8888; |
| 1589 | else |
| 1590 | return in_format; |
| 1591 | case MDP_Y_CBCR_H2V2_VENUS: |
| 1592 | case MDP_Y_CRCB_H2V2_VENUS: |
| 1593 | case MDP_Y_CBCR_H2V2: |
| 1594 | if (in_rot90) |
| 1595 | return MDP_Y_CRCB_H2V2; |
| 1596 | else |
| 1597 | return in_format; |
| 1598 | case MDP_Y_CB_CR_H2V2: |
| 1599 | case MDP_Y_CR_CB_GH2V2: |
| 1600 | case MDP_Y_CR_CB_H2V2: |
| 1601 | return MDP_Y_CRCB_H2V2; |
| 1602 | default: |
| 1603 | return in_format; |
| 1604 | } |
| 1605 | } |
| 1606 | |
| 1607 | irqreturn_t mdss_mdp_isr(int irq, void *ptr); |
| 1608 | void mdss_mdp_irq_clear(struct mdss_data_type *mdata, |
| 1609 | u32 intr_type, u32 intf_num); |
| 1610 | int mdss_mdp_irq_enable(u32 intr_type, u32 intf_num); |
| 1611 | void mdss_mdp_irq_disable(u32 intr_type, u32 intf_num); |
| 1612 | void mdss_mdp_intr_check_and_clear(u32 intr_type, u32 intf_num); |
| 1613 | int mdss_mdp_hist_irq_enable(u32 irq); |
| 1614 | void mdss_mdp_hist_irq_disable(u32 irq); |
| 1615 | void mdss_mdp_irq_disable_nosync(u32 intr_type, u32 intf_num); |
| 1616 | int mdss_mdp_set_intr_callback(u32 intr_type, u32 intf_num, |
| 1617 | void (*fnc_ptr)(void *), void *arg); |
| 1618 | int mdss_mdp_set_intr_callback_nosync(u32 intr_type, u32 intf_num, |
| 1619 | void (*fnc_ptr)(void *), void *arg); |
| 1620 | u32 mdss_mdp_get_irq_mask(u32 intr_type, u32 intf_num); |
| 1621 | |
| 1622 | void mdss_mdp_footswitch_ctrl_splash(int on); |
| 1623 | void mdss_mdp_batfet_ctrl(struct mdss_data_type *mdata, int enable); |
| 1624 | void mdss_mdp_set_clk_rate(unsigned long min_clk_rate); |
| 1625 | unsigned long mdss_mdp_get_clk_rate(u32 clk_idx, bool locked); |
| 1626 | int mdss_mdp_vsync_clk_enable(int enable, bool locked); |
| 1627 | void mdss_mdp_clk_ctrl(int enable); |
| 1628 | struct mdss_data_type *mdss_mdp_get_mdata(void); |
| 1629 | int mdss_mdp_secure_display_ctrl(struct mdss_data_type *mdata, |
| 1630 | unsigned int enable); |
| 1631 | |
| 1632 | int mdss_mdp_overlay_init(struct msm_fb_data_type *mfd); |
| 1633 | int mdss_mdp_dfps_update_params(struct msm_fb_data_type *mfd, |
| 1634 | struct mdss_panel_data *pdata, struct dynamic_fps_data *data); |
| 1635 | int mdss_mdp_layer_atomic_validate(struct msm_fb_data_type *mfd, |
| 1636 | struct file *file, struct mdp_layer_commit_v1 *ov_commit); |
| 1637 | int mdss_mdp_layer_pre_commit(struct msm_fb_data_type *mfd, |
| 1638 | struct file *file, struct mdp_layer_commit_v1 *ov_commit); |
| 1639 | |
| 1640 | int mdss_mdp_layer_atomic_validate_wfd(struct msm_fb_data_type *mfd, |
| 1641 | struct file *file, struct mdp_layer_commit_v1 *ov_commit); |
| 1642 | int mdss_mdp_layer_pre_commit_wfd(struct msm_fb_data_type *mfd, |
| 1643 | struct file *file, struct mdp_layer_commit_v1 *ov_commit); |
| 1644 | bool mdss_mdp_wfd_is_config_same(struct msm_fb_data_type *mfd, |
| 1645 | struct mdp_output_layer *layer); |
| 1646 | |
| 1647 | int mdss_mdp_async_position_update(struct msm_fb_data_type *mfd, |
| 1648 | struct mdp_position_update *update_pos); |
| 1649 | |
| 1650 | int mdss_mdp_overlay_req_check(struct msm_fb_data_type *mfd, |
| 1651 | struct mdp_overlay *req, |
| 1652 | struct mdss_mdp_format_params *fmt); |
| 1653 | int mdss_mdp_overlay_vsync_ctrl(struct msm_fb_data_type *mfd, int en); |
| 1654 | int mdss_mdp_overlay_pipe_setup(struct msm_fb_data_type *mfd, |
| 1655 | struct mdp_overlay *req, struct mdss_mdp_pipe **ppipe, |
| 1656 | struct mdss_mdp_pipe *left_blend_pipe, bool is_single_layer); |
| 1657 | void mdss_mdp_handoff_cleanup_pipes(struct msm_fb_data_type *mfd, |
| 1658 | u32 type); |
| 1659 | int mdss_mdp_overlay_release(struct msm_fb_data_type *mfd, int ndx); |
| 1660 | int mdss_mdp_overlay_start(struct msm_fb_data_type *mfd); |
| 1661 | void mdss_mdp_overlay_set_chroma_sample( |
| 1662 | struct mdss_mdp_pipe *pipe); |
| 1663 | int mdp_pipe_tune_perf(struct mdss_mdp_pipe *pipe, |
| 1664 | u32 flags); |
| 1665 | int mdss_mdp_overlay_setup_scaling(struct mdss_mdp_pipe *pipe); |
| 1666 | struct mdss_mdp_pipe *mdss_mdp_pipe_assign(struct mdss_data_type *mdata, |
| 1667 | struct mdss_mdp_mixer *mixer, u32 ndx, |
| 1668 | enum mdss_mdp_pipe_rect rect_num); |
| 1669 | struct mdss_mdp_pipe *mdss_mdp_overlay_pipe_reuse( |
| 1670 | struct msm_fb_data_type *mfd, int pipe_ndx); |
| 1671 | void mdss_mdp_pipe_position_update(struct mdss_mdp_pipe *pipe, |
| 1672 | struct mdss_rect *src, struct mdss_rect *dst); |
| 1673 | int mdss_mdp_video_addr_setup(struct mdss_data_type *mdata, |
| 1674 | u32 *offsets, u32 count); |
| 1675 | int mdss_mdp_video_start(struct mdss_mdp_ctl *ctl); |
| 1676 | void mdss_mdp_switch_roi_reset(struct mdss_mdp_ctl *ctl); |
| 1677 | void mdss_mdp_switch_to_cmd_mode(struct mdss_mdp_ctl *ctl, int prep); |
| 1678 | void mdss_mdp_switch_to_vid_mode(struct mdss_mdp_ctl *ctl, int prep); |
| 1679 | void *mdss_mdp_get_intf_base_addr(struct mdss_data_type *mdata, |
| 1680 | u32 interface_id); |
| 1681 | int mdss_mdp_cmd_start(struct mdss_mdp_ctl *ctl); |
| 1682 | int mdss_mdp_writeback_start(struct mdss_mdp_ctl *ctl); |
| 1683 | int mdss_mdp_overlay_kickoff(struct msm_fb_data_type *mfd, |
| 1684 | struct mdp_display_commit *data); |
| 1685 | struct mdss_mdp_data *mdss_mdp_overlay_buf_alloc(struct msm_fb_data_type *mfd, |
| 1686 | struct mdss_mdp_pipe *pipe); |
| 1687 | void mdss_mdp_overlay_buf_free(struct msm_fb_data_type *mfd, |
| 1688 | struct mdss_mdp_data *buf); |
| 1689 | |
| 1690 | int mdss_mdp_ctl_reconfig(struct mdss_mdp_ctl *ctl, |
| 1691 | struct mdss_panel_data *pdata); |
| 1692 | struct mdss_mdp_ctl *mdss_mdp_ctl_init(struct mdss_panel_data *pdata, |
| 1693 | struct msm_fb_data_type *mfd); |
| 1694 | int mdss_mdp_video_reconfigure_splash_done(struct mdss_mdp_ctl *ctl, |
| 1695 | bool handoff); |
| 1696 | int mdss_mdp_cmd_reconfigure_splash_done(struct mdss_mdp_ctl *ctl, |
| 1697 | bool handoff); |
| 1698 | int mdss_mdp_ctl_splash_finish(struct mdss_mdp_ctl *ctl, bool handoff); |
| 1699 | void mdss_mdp_check_ctl_reset_status(struct mdss_mdp_ctl *ctl); |
| 1700 | int mdss_mdp_ctl_setup(struct mdss_mdp_ctl *ctl); |
| 1701 | int mdss_mdp_ctl_split_display_setup(struct mdss_mdp_ctl *ctl, |
| 1702 | struct mdss_panel_data *pdata); |
| 1703 | int mdss_mdp_ctl_destroy(struct mdss_mdp_ctl *ctl); |
| 1704 | int mdss_mdp_ctl_start(struct mdss_mdp_ctl *ctl, bool handoff); |
| 1705 | int mdss_mdp_ctl_stop(struct mdss_mdp_ctl *ctl, int panel_power_mode); |
| 1706 | int mdss_mdp_ctl_intf_event(struct mdss_mdp_ctl *ctl, int event, void *arg, |
| 1707 | u32 flags); |
| 1708 | int mdss_mdp_get_prefetch_lines(struct mdss_panel_info *pinfo); |
| 1709 | int mdss_mdp_perf_bw_check(struct mdss_mdp_ctl *ctl, |
| 1710 | struct mdss_mdp_pipe **left_plist, int left_cnt, |
| 1711 | struct mdss_mdp_pipe **right_plist, int right_cnt); |
| 1712 | int mdss_mdp_perf_bw_check_pipe(struct mdss_mdp_perf_params *perf, |
| 1713 | struct mdss_mdp_pipe *pipe); |
| 1714 | int mdss_mdp_get_pipe_overlap_bw(struct mdss_mdp_pipe *pipe, |
| 1715 | struct mdss_rect *roi, u64 *quota, u64 *quota_nocr, u32 flags); |
| 1716 | int mdss_mdp_get_panel_params(struct mdss_mdp_pipe *pipe, |
| 1717 | struct mdss_mdp_mixer *mixer, u32 *fps, u32 *v_total, |
| 1718 | u32 *h_total, u32 *xres); |
| 1719 | int mdss_mdp_perf_calc_pipe(struct mdss_mdp_pipe *pipe, |
| 1720 | struct mdss_mdp_perf_params *perf, struct mdss_rect *roi, |
| 1721 | u32 flags); |
| 1722 | bool mdss_mdp_is_amortizable_pipe(struct mdss_mdp_pipe *pipe, |
| 1723 | struct mdss_mdp_mixer *mixer, struct mdss_data_type *mdata); |
| 1724 | u32 mdss_mdp_calc_latency_buf_bytes(bool is_yuv, bool is_bwc, |
| 1725 | bool is_tile, u32 src_w, u32 bpp, bool use_latency_buf_percentage, |
| 1726 | u32 smp_bytes, bool is_ubwc, bool is_nv12, bool is_hflip); |
| 1727 | u32 mdss_mdp_get_mdp_clk_rate(struct mdss_data_type *mdata); |
| 1728 | int mdss_mdp_ctl_notify(struct mdss_mdp_ctl *ctl, int event); |
| 1729 | void mdss_mdp_ctl_notifier_register(struct mdss_mdp_ctl *ctl, |
| 1730 | struct notifier_block *notifier); |
| 1731 | void mdss_mdp_ctl_notifier_unregister(struct mdss_mdp_ctl *ctl, |
| 1732 | struct notifier_block *notifier); |
| 1733 | u32 mdss_mdp_ctl_perf_get_transaction_status(struct mdss_mdp_ctl *ctl); |
| 1734 | u32 apply_comp_ratio_factor(u32 quota, struct mdss_mdp_format_params *fmt, |
| 1735 | struct mult_factor *factor); |
| 1736 | |
| 1737 | int mdss_mdp_scan_pipes(void); |
| 1738 | |
| 1739 | int mdss_mdp_mixer_handoff(struct mdss_mdp_ctl *ctl, u32 num, |
| 1740 | struct mdss_mdp_pipe *pipe); |
| 1741 | |
| 1742 | void mdss_mdp_ctl_perf_set_transaction_status(struct mdss_mdp_ctl *ctl, |
| 1743 | enum mdss_mdp_perf_state_type component, bool new_status); |
| 1744 | void mdss_mdp_ctl_perf_release_bw(struct mdss_mdp_ctl *ctl); |
| 1745 | int mdss_mdp_async_ctl_flush(struct msm_fb_data_type *mfd, |
| 1746 | u32 flush_bits); |
| 1747 | int mdss_mdp_get_pipe_flush_bits(struct mdss_mdp_pipe *pipe); |
| 1748 | struct mdss_mdp_mixer *mdss_mdp_block_mixer_alloc(void); |
| 1749 | int mdss_mdp_block_mixer_destroy(struct mdss_mdp_mixer *mixer); |
| 1750 | struct mdss_mdp_mixer *mdss_mdp_mixer_get(struct mdss_mdp_ctl *ctl, int mux); |
| 1751 | struct mdss_mdp_pipe *mdss_mdp_get_staged_pipe(struct mdss_mdp_ctl *ctl, |
| 1752 | int mux, int stage, bool is_right_blend); |
| 1753 | int mdss_mdp_mixer_pipe_update(struct mdss_mdp_pipe *pipe, |
| 1754 | struct mdss_mdp_mixer *mixer, int params_changed); |
| 1755 | int mdss_mdp_mixer_pipe_unstage(struct mdss_mdp_pipe *pipe, |
| 1756 | struct mdss_mdp_mixer *mixer); |
| 1757 | void mdss_mdp_mixer_unstage_all(struct mdss_mdp_mixer *mixer); |
| 1758 | void mdss_mdp_reset_mixercfg(struct mdss_mdp_ctl *ctl); |
| 1759 | int mdss_mdp_display_commit(struct mdss_mdp_ctl *ctl, void *arg, |
| 1760 | struct mdss_mdp_commit_cb *commit_cb); |
| 1761 | int mdss_mdp_display_wait4comp(struct mdss_mdp_ctl *ctl); |
| 1762 | int mdss_mdp_display_wait4pingpong(struct mdss_mdp_ctl *ctl, bool use_lock); |
| 1763 | int mdss_mdp_display_wakeup_time(struct mdss_mdp_ctl *ctl, |
| 1764 | ktime_t *wakeup_time); |
| 1765 | |
| 1766 | int mdss_mdp_csc_setup(u32 block, u32 blk_idx, u32 csc_type); |
| 1767 | int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, struct mdp_csc_cfg *data); |
| 1768 | |
| 1769 | int mdss_mdp_pp_init(struct device *dev); |
| 1770 | void mdss_mdp_pp_term(struct device *dev); |
| 1771 | int mdss_mdp_pp_overlay_init(struct msm_fb_data_type *mfd); |
| 1772 | |
| 1773 | int mdss_mdp_pp_resume(struct msm_fb_data_type *mfd); |
| 1774 | |
| 1775 | int mdss_mdp_pp_setup(struct mdss_mdp_ctl *ctl); |
| 1776 | int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl); |
| 1777 | int mdss_mdp_pipe_pp_setup(struct mdss_mdp_pipe *pipe, u32 *op); |
| 1778 | void mdss_mdp_pipe_pp_clear(struct mdss_mdp_pipe *pipe); |
| 1779 | int mdss_mdp_pipe_sspp_setup(struct mdss_mdp_pipe *pipe, u32 *op); |
| 1780 | int mdss_mdp_pp_sspp_config(struct mdss_mdp_pipe *pipe); |
| 1781 | int mdss_mdp_copy_layer_pp_info(struct mdp_input_layer *layer); |
| 1782 | void mdss_mdp_free_layer_pp_info(struct mdp_input_layer *layer); |
| 1783 | |
| 1784 | int mdss_mdp_smp_setup(struct mdss_data_type *mdata, u32 cnt, u32 size); |
| 1785 | |
| 1786 | void mdss_hw_init(struct mdss_data_type *mdata); |
| 1787 | |
| 1788 | int mdss_mdp_mfd_valid_dspp(struct msm_fb_data_type *mfd); |
| 1789 | |
| 1790 | int mdss_mdp_pa_config(struct msm_fb_data_type *mfd, |
| 1791 | struct mdp_pa_cfg_data *config, u32 *copyback); |
| 1792 | int mdss_mdp_pa_v2_config(struct msm_fb_data_type *mfd, |
| 1793 | struct mdp_pa_v2_cfg_data *config, u32 *copyback); |
| 1794 | int mdss_mdp_pcc_config(struct msm_fb_data_type *mfd, |
| 1795 | struct mdp_pcc_cfg_data *cfg_ptr, u32 *copyback); |
| 1796 | int mdss_mdp_igc_lut_config(struct msm_fb_data_type *mfd, |
| 1797 | struct mdp_igc_lut_data *config, u32 *copyback, |
| 1798 | u32 copy_from_kernel); |
| 1799 | int mdss_mdp_argc_config(struct msm_fb_data_type *mfd, |
| 1800 | struct mdp_pgc_lut_data *config, u32 *copyback); |
| 1801 | int mdss_mdp_hist_lut_config(struct msm_fb_data_type *mfd, |
| 1802 | struct mdp_hist_lut_data *config, u32 *copyback); |
| 1803 | int mdss_mdp_pp_default_overlay_config(struct msm_fb_data_type *mfd, |
| 1804 | struct mdss_panel_data *pdata, |
| 1805 | bool enable); |
| 1806 | int mdss_mdp_dither_config(struct msm_fb_data_type *mfd, |
| 1807 | struct mdp_dither_cfg_data *config, u32 *copyback, |
| 1808 | int copy_from_kernel); |
| 1809 | int mdss_mdp_gamut_config(struct msm_fb_data_type *mfd, |
| 1810 | struct mdp_gamut_cfg_data *config, u32 *copyback); |
| 1811 | |
| 1812 | int mdss_mdp_hist_intr_req(struct mdss_intr *intr, u32 bits, bool en); |
| 1813 | int mdss_mdp_hist_intr_setup(struct mdss_intr *intr, int state); |
| 1814 | int mdss_mdp_hist_start(struct mdp_histogram_start_req *req); |
| 1815 | int mdss_mdp_hist_stop(u32 block); |
| 1816 | int mdss_mdp_hist_collect(struct mdp_histogram_data *hist); |
| 1817 | void mdss_mdp_hist_intr_done(u32 isr); |
| 1818 | |
| 1819 | int mdss_mdp_ad_config(struct msm_fb_data_type *mfd, |
| 1820 | struct mdss_ad_init_cfg *init_cfg); |
| 1821 | int mdss_mdp_ad_input(struct msm_fb_data_type *mfd, |
| 1822 | struct mdss_ad_input *input, int wait); |
| 1823 | int mdss_mdp_ad_addr_setup(struct mdss_data_type *mdata, u32 *ad_offsets); |
| 1824 | int mdss_mdp_calib_mode(struct msm_fb_data_type *mfd, |
| 1825 | struct mdss_calib_cfg *cfg); |
| 1826 | |
| 1827 | int mdss_mdp_pipe_handoff(struct mdss_mdp_pipe *pipe); |
| 1828 | int mdss_mdp_smp_handoff(struct mdss_data_type *mdata); |
| 1829 | struct mdss_mdp_pipe *mdss_mdp_pipe_alloc(struct mdss_mdp_mixer *mixer, |
| 1830 | u32 type, struct mdss_mdp_pipe *left_blend_pipe); |
| 1831 | struct mdss_mdp_pipe *mdss_mdp_pipe_get(u32 ndx, |
| 1832 | enum mdss_mdp_pipe_rect rect_num); |
| 1833 | struct mdss_mdp_pipe *mdss_mdp_pipe_search(struct mdss_data_type *mdata, |
| 1834 | u32 ndx, enum mdss_mdp_pipe_rect rect_num); |
| 1835 | int mdss_mdp_pipe_map(struct mdss_mdp_pipe *pipe); |
| 1836 | void mdss_mdp_pipe_unmap(struct mdss_mdp_pipe *pipe); |
| 1837 | |
| 1838 | u32 mdss_mdp_smp_calc_num_blocks(struct mdss_mdp_pipe *pipe); |
| 1839 | u32 mdss_mdp_smp_get_size(struct mdss_mdp_pipe *pipe); |
| 1840 | int mdss_mdp_smp_reserve(struct mdss_mdp_pipe *pipe); |
| 1841 | void mdss_mdp_smp_unreserve(struct mdss_mdp_pipe *pipe); |
| 1842 | void mdss_mdp_smp_release(struct mdss_mdp_pipe *pipe); |
| 1843 | |
| 1844 | int mdss_mdp_pipe_addr_setup(struct mdss_data_type *mdata, |
| 1845 | struct mdss_mdp_pipe *head, u32 *offsets, u32 *ftch_id, u32 *xin_id, |
| 1846 | u32 type, const int *pnums, u32 len, u32 rects_per_sspp, |
| 1847 | u8 priority_base); |
| 1848 | int mdss_mdp_mixer_addr_setup(struct mdss_data_type *mdata, u32 *mixer_offsets, |
| 1849 | u32 *dspp_offsets, u32 *pingpong_offsets, u32 type, u32 len); |
| 1850 | int mdss_mdp_ctl_addr_setup(struct mdss_data_type *mdata, u32 *ctl_offsets, |
| 1851 | u32 len); |
| 1852 | int mdss_mdp_wb_addr_setup(struct mdss_data_type *mdata, |
| 1853 | u32 num_wb, u32 num_intf_wb); |
| 1854 | |
| 1855 | void mdss_mdp_pipe_clk_force_off(struct mdss_mdp_pipe *pipe); |
| 1856 | int mdss_mdp_pipe_fetch_halt(struct mdss_mdp_pipe *pipe, bool is_recovery); |
| 1857 | int mdss_mdp_pipe_panic_signal_ctrl(struct mdss_mdp_pipe *pipe, bool enable); |
| 1858 | void mdss_mdp_bwcpanic_ctrl(struct mdss_data_type *mdata, bool enable); |
| 1859 | int mdss_mdp_pipe_destroy(struct mdss_mdp_pipe *pipe); |
| 1860 | int mdss_mdp_pipe_queue_data(struct mdss_mdp_pipe *pipe, |
| 1861 | struct mdss_mdp_data *src_data); |
| 1862 | |
| 1863 | int mdss_mdp_data_check(struct mdss_mdp_data *data, |
| 1864 | struct mdss_mdp_plane_sizes *ps, |
| 1865 | struct mdss_mdp_format_params *fmt); |
| 1866 | int mdss_mdp_get_plane_sizes(struct mdss_mdp_format_params *fmt, u32 w, u32 h, |
| 1867 | struct mdss_mdp_plane_sizes *ps, u32 bwc_mode, bool rotation); |
| 1868 | int mdss_mdp_get_rau_strides(u32 w, u32 h, struct mdss_mdp_format_params *fmt, |
| 1869 | struct mdss_mdp_plane_sizes *ps); |
| 1870 | void mdss_mdp_data_calc_offset(struct mdss_mdp_data *data, u16 x, u16 y, |
| 1871 | struct mdss_mdp_plane_sizes *ps, struct mdss_mdp_format_params *fmt); |
| 1872 | void mdss_mdp_format_flag_removal(u32 *table, u32 num, u32 remove_bits); |
| 1873 | struct mdss_mdp_format_params *mdss_mdp_get_format_params(u32 format); |
| 1874 | int mdss_mdp_validate_offset_for_ubwc_format( |
| 1875 | struct mdss_mdp_format_params *fmt, u16 x, u16 y); |
| 1876 | void mdss_mdp_get_v_h_subsample_rate(u8 chroma_samp, |
| 1877 | u8 *v_sample, u8 *h_sample); |
| 1878 | struct mult_factor *mdss_mdp_get_comp_factor(u32 format, |
| 1879 | bool rt_factor); |
| 1880 | int mdss_mdp_data_map(struct mdss_mdp_data *data, bool rotator, int dir); |
| 1881 | void mdss_mdp_data_free(struct mdss_mdp_data *data, bool rotator, int dir); |
| 1882 | int mdss_mdp_data_get_and_validate_size(struct mdss_mdp_data *data, |
| 1883 | struct msmfb_data *planes, int num_planes, u32 flags, |
| 1884 | struct device *dev, bool rotator, int dir, |
| 1885 | struct mdp_layer_buffer *buffer); |
| 1886 | u32 mdss_get_panel_framerate(struct msm_fb_data_type *mfd); |
| 1887 | int mdss_mdp_calc_phase_step(u32 src, u32 dst, u32 *out_phase); |
| 1888 | |
| 1889 | void mdss_mdp_intersect_rect(struct mdss_rect *res_rect, |
| 1890 | const struct mdss_rect *dst_rect, |
| 1891 | const struct mdss_rect *sci_rect); |
| 1892 | void mdss_mdp_crop_rect(struct mdss_rect *src_rect, |
| 1893 | struct mdss_rect *dst_rect, |
| 1894 | const struct mdss_rect *sci_rect); |
| 1895 | void rect_copy_mdss_to_mdp(struct mdp_rect *user, struct mdss_rect *kernel); |
| 1896 | void rect_copy_mdp_to_mdss(struct mdp_rect *user, struct mdss_rect *kernel); |
| 1897 | bool mdss_rect_overlap_check(struct mdss_rect *rect1, struct mdss_rect *rect2); |
| 1898 | void mdss_rect_split(struct mdss_rect *in_roi, struct mdss_rect *l_roi, |
| 1899 | struct mdss_rect *r_roi, u32 splitpoint); |
| 1900 | |
| 1901 | |
| 1902 | int mdss_mdp_get_ctl_mixers(u32 fb_num, u32 *mixer_id); |
| 1903 | bool mdss_mdp_mixer_reg_has_pipe(struct mdss_mdp_mixer *mixer, |
| 1904 | struct mdss_mdp_pipe *pipe); |
| 1905 | u32 mdss_mdp_fb_stride(u32 fb_index, u32 xres, int bpp); |
| 1906 | void mdss_check_dsi_ctrl_status(struct work_struct *work, uint32_t interval); |
| 1907 | |
| 1908 | int mdss_mdp_calib_config(struct mdp_calib_config_data *cfg, u32 *copyback); |
| 1909 | int mdss_mdp_calib_config_buffer(struct mdp_calib_config_buffer *cfg, |
| 1910 | u32 *copyback); |
| 1911 | int mdss_mdp_ctl_update_fps(struct mdss_mdp_ctl *ctl); |
| 1912 | int mdss_mdp_pipe_is_staged(struct mdss_mdp_pipe *pipe); |
| 1913 | int mdss_mdp_writeback_display_commit(struct mdss_mdp_ctl *ctl, void *arg); |
| 1914 | struct mdss_mdp_ctl *mdss_mdp_ctl_mixer_switch(struct mdss_mdp_ctl *ctl, |
| 1915 | u32 return_type); |
| 1916 | void mdss_mdp_set_roi(struct mdss_mdp_ctl *ctl, |
| 1917 | struct mdss_rect *l_roi, struct mdss_rect *r_roi); |
| 1918 | void mdss_mdp_mixer_update_pipe_map(struct mdss_mdp_ctl *master_ctl, |
| 1919 | int mixer_mux); |
| 1920 | |
| 1921 | void mdss_mdp_pipe_calc_pixel_extn(struct mdss_mdp_pipe *pipe); |
| 1922 | void mdss_mdp_pipe_calc_qseed3_cfg(struct mdss_mdp_pipe *pipe); |
| 1923 | void mdss_mdp_ctl_restore(bool locked); |
| 1924 | int mdss_mdp_ctl_reset(struct mdss_mdp_ctl *ctl, bool is_recovery); |
| 1925 | int mdss_mdp_wait_for_xin_halt(u32 xin_id, bool is_vbif_nrt); |
| 1926 | void mdss_mdp_set_ot_limit(struct mdss_mdp_set_ot_params *params); |
| 1927 | int mdss_mdp_cmd_set_autorefresh_mode(struct mdss_mdp_ctl *ctl, int frame_cnt); |
| 1928 | int mdss_mdp_cmd_get_autorefresh_mode(struct mdss_mdp_ctl *ctl); |
| 1929 | int mdss_mdp_ctl_cmd_set_autorefresh(struct mdss_mdp_ctl *ctl, int frame_cnt); |
| 1930 | int mdss_mdp_ctl_cmd_get_autorefresh(struct mdss_mdp_ctl *ctl); |
| 1931 | void mdss_mdp_ctl_event_timer(void *data); |
| 1932 | int mdss_mdp_pp_get_version(struct mdp_pp_feature_version *version); |
| 1933 | |
| 1934 | struct mdss_mdp_ctl *mdss_mdp_ctl_alloc(struct mdss_data_type *mdata, |
| 1935 | u32 off); |
| 1936 | int mdss_mdp_ctl_free(struct mdss_mdp_ctl *ctl); |
| 1937 | |
| 1938 | struct mdss_mdp_mixer *mdss_mdp_mixer_assign(u32 id, bool wb, bool rot); |
| 1939 | struct mdss_mdp_mixer *mdss_mdp_mixer_alloc( |
| 1940 | struct mdss_mdp_ctl *ctl, u32 type, int mux, int rotator); |
| 1941 | int mdss_mdp_mixer_free(struct mdss_mdp_mixer *mixer); |
| 1942 | |
| 1943 | bool mdss_mdp_is_wb_mdp_intf(u32 num, u32 reg_index); |
| 1944 | struct mdss_mdp_writeback *mdss_mdp_wb_assign(u32 id, u32 reg_index); |
| 1945 | struct mdss_mdp_writeback *mdss_mdp_wb_alloc(u32 caps, u32 reg_index); |
| 1946 | void mdss_mdp_wb_free(struct mdss_mdp_writeback *wb); |
| 1947 | |
| 1948 | void mdss_mdp_ctl_dsc_setup(struct mdss_mdp_ctl *ctl, |
| 1949 | struct mdss_panel_info *pinfo); |
| 1950 | |
| 1951 | void mdss_mdp_video_isr(void *ptr, u32 count); |
| 1952 | void mdss_mdp_enable_hw_irq(struct mdss_data_type *mdata); |
| 1953 | void mdss_mdp_disable_hw_irq(struct mdss_data_type *mdata); |
| 1954 | |
| 1955 | void mdss_mdp_set_supported_formats(struct mdss_data_type *mdata); |
| 1956 | |
| 1957 | void mdss_mdp_frc_fsm_init_state(struct mdss_mdp_frc_fsm *frc_fsm); |
| 1958 | void mdss_mdp_frc_fsm_change_state(struct mdss_mdp_frc_fsm *frc_fsm, |
| 1959 | enum mdss_mdp_frc_state_type state, |
| 1960 | void (*cb)(struct mdss_mdp_frc_fsm *frc_fsm)); |
| 1961 | void mdss_mdp_frc_fsm_update_state(struct mdss_mdp_frc_fsm *frc_fsm); |
| 1962 | |
| 1963 | #ifdef CONFIG_FB_MSM_MDP_NONE |
| 1964 | struct mdss_data_type *mdss_mdp_get_mdata(void) |
| 1965 | { |
| 1966 | return NULL; |
| 1967 | } |
| 1968 | |
| 1969 | int mdss_mdp_copy_layer_pp_info(struct mdp_input_layer *layer) |
| 1970 | { |
| 1971 | return -EFAULT; |
| 1972 | } |
| 1973 | |
| 1974 | void mdss_mdp_free_layer_pp_info(struct mdp_input_layer *layer) |
| 1975 | { |
| 1976 | } |
| 1977 | |
| 1978 | #endif /* CONFIG_FB_MSM_MDP_NONE */ |
| 1979 | #endif /* MDSS_MDP_H */ |