Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #include <linux/clk.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/clk/msm-clk.h> |
| 19 | #include <linux/iopoll.h> |
| 20 | #include <linux/kthread.h> |
| 21 | |
| 22 | #include "mdss_dsi.h" |
| 23 | #include "mdss_edp.h" |
| 24 | #include "mdss_dsi_phy.h" |
| 25 | |
| 26 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_0 0x00 |
| 27 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_1 0x04 |
| 28 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_2 0x08 |
| 29 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_3 0x0c |
| 30 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_4 0x10 |
| 31 | #define MDSS_DSI_DSIPHY_REGULATOR_CAL_PWR_CFG 0x18 |
| 32 | #define MDSS_DSI_DSIPHY_LDO_CNTRL 0x1dc |
| 33 | #define MDSS_DSI_DSIPHY_REGULATOR_TEST 0x294 |
| 34 | #define MDSS_DSI_DSIPHY_STRENGTH_CTRL_0 0x184 |
| 35 | #define MDSS_DSI_DSIPHY_STRENGTH_CTRL_1 0x188 |
| 36 | #define MDSS_DSI_DSIPHY_STRENGTH_CTRL_2 0x18c |
| 37 | #define MDSS_DSI_DSIPHY_TIMING_CTRL_0 0x140 |
| 38 | #define MDSS_DSI_DSIPHY_GLBL_TEST_CTRL 0x1d4 |
| 39 | #define MDSS_DSI_DSIPHY_CTRL_0 0x170 |
| 40 | #define MDSS_DSI_DSIPHY_CTRL_1 0x174 |
| 41 | |
| 42 | #define SW_RESET BIT(2) |
| 43 | #define SW_RESET_PLL BIT(0) |
| 44 | #define PWRDN_B BIT(7) |
| 45 | |
| 46 | /* 8996 */ |
| 47 | #define DATALANE_OFFSET_FROM_BASE_8996 0x100 |
| 48 | #define DSIPHY_CMN_PLL_CNTRL 0x0048 |
| 49 | #define DATALANE_SIZE_8996 0x80 |
| 50 | |
| 51 | #define DSIPHY_CMN_GLBL_TEST_CTRL 0x0018 |
| 52 | #define DSIPHY_CMN_CTRL_0 0x001c |
| 53 | #define DSIPHY_CMN_CTRL_1 0x0020 |
| 54 | #define DSIPHY_CMN_LDO_CNTRL 0x004c |
| 55 | #define DSIPHY_PLL_CLKBUFLR_EN 0x041c |
| 56 | #define DSIPHY_PLL_PLL_BANDGAP 0x0508 |
| 57 | |
| 58 | #define DSIPHY_LANE_STRENGTH_CTRL_1 0x003c |
| 59 | #define DSIPHY_LANE_VREG_CNTRL 0x0064 |
| 60 | |
| 61 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL0 0x214 |
| 62 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL1 0x218 |
| 63 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL2 0x21C |
| 64 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL3 0x220 |
| 65 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL4 0x224 |
| 66 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL5 0x228 |
| 67 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL6 0x22C |
| 68 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL7 0x230 |
| 69 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL8 0x234 |
| 70 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL9 0x238 |
| 71 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL10 0x23C |
| 72 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL11 0x240 |
| 73 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL12 0x244 |
| 74 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL13 0x248 |
| 75 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL14 0x24C |
| 76 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL15 0x250 |
| 77 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL16 0x254 |
| 78 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL17 0x258 |
| 79 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL18 0x25C |
| 80 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL19 0x260 |
| 81 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL19 0x260 |
| 82 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL20 0x264 |
| 83 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL21 0x268 |
| 84 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL22 0x26C |
| 85 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL23 0x270 |
| 86 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL24 0x274 |
| 87 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL25 0x278 |
| 88 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL26 0x27C |
| 89 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL27 0x280 |
| 90 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL28 0x284 |
| 91 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL29 0x288 |
| 92 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL30 0x28C |
| 93 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL31 0x290 |
| 94 | #define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR 0x294 |
| 95 | #define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2 0x298 |
| 96 | |
| 97 | #define DSIPHY_DLN0_CFG1 0x0104 |
| 98 | #define DSIPHY_DLN0_TIMING_CTRL_4 0x0118 |
| 99 | #define DSIPHY_DLN0_TIMING_CTRL_5 0x011C |
| 100 | #define DSIPHY_DLN0_TIMING_CTRL_6 0x0120 |
| 101 | #define DSIPHY_DLN0_TIMING_CTRL_7 0x0124 |
| 102 | #define DSIPHY_DLN0_TIMING_CTRL_8 0x0128 |
| 103 | |
| 104 | #define DSIPHY_DLN1_CFG1 0x0184 |
| 105 | #define DSIPHY_DLN1_TIMING_CTRL_4 0x0198 |
| 106 | #define DSIPHY_DLN1_TIMING_CTRL_5 0x019C |
| 107 | #define DSIPHY_DLN1_TIMING_CTRL_6 0x01A0 |
| 108 | #define DSIPHY_DLN1_TIMING_CTRL_7 0x01A4 |
| 109 | #define DSIPHY_DLN1_TIMING_CTRL_8 0x01A8 |
| 110 | |
| 111 | #define DSIPHY_DLN2_CFG1 0x0204 |
| 112 | #define DSIPHY_DLN2_TIMING_CTRL_4 0x0218 |
| 113 | #define DSIPHY_DLN2_TIMING_CTRL_5 0x021C |
| 114 | #define DSIPHY_DLN2_TIMING_CTRL_6 0x0220 |
| 115 | #define DSIPHY_DLN2_TIMING_CTRL_7 0x0224 |
| 116 | #define DSIPHY_DLN2_TIMING_CTRL_8 0x0228 |
| 117 | |
| 118 | #define DSIPHY_DLN3_CFG1 0x0284 |
| 119 | #define DSIPHY_DLN3_TIMING_CTRL_4 0x0298 |
| 120 | #define DSIPHY_DLN3_TIMING_CTRL_5 0x029C |
| 121 | #define DSIPHY_DLN3_TIMING_CTRL_6 0x02A0 |
| 122 | #define DSIPHY_DLN3_TIMING_CTRL_7 0x02A4 |
| 123 | #define DSIPHY_DLN3_TIMING_CTRL_8 0x02A8 |
| 124 | |
| 125 | #define DSIPHY_CKLN_CFG1 0x0304 |
| 126 | #define DSIPHY_CKLN_TIMING_CTRL_4 0x0318 |
| 127 | #define DSIPHY_CKLN_TIMING_CTRL_5 0x031C |
| 128 | #define DSIPHY_CKLN_TIMING_CTRL_6 0x0320 |
| 129 | #define DSIPHY_CKLN_TIMING_CTRL_7 0x0324 |
| 130 | #define DSIPHY_CKLN_TIMING_CTRL_8 0x0328 |
| 131 | |
| 132 | #define DSIPHY_PLL_RESETSM_CNTRL5 0x043c |
| 133 | |
| 134 | #define PLL_CALC_DATA(addr0, addr1, data0, data1) \ |
| 135 | (((data1) << 24) | ((((addr1)/4) & 0xFF) << 16) | \ |
| 136 | ((data0) << 8) | (((addr0)/4) & 0xFF)) |
| 137 | |
| 138 | #define MDSS_DYN_REF_REG_W(base, offset, addr0, addr1, data0, data1) \ |
| 139 | writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \ |
| 140 | (base) + (offset)) |
| 141 | |
| 142 | void mdss_dsi_dfps_config_8996(struct mdss_dsi_ctrl_pdata *ctrl) |
| 143 | { |
| 144 | struct mdss_panel_data *pdata; |
| 145 | struct mdss_panel_info *pinfo; |
| 146 | struct mdss_dsi_phy_ctrl *pd; |
| 147 | int glbl_tst_cntrl = |
| 148 | MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_GLBL_TEST_CTRL); |
| 149 | |
| 150 | pdata = &ctrl->panel_data; |
| 151 | if (!pdata) { |
| 152 | pr_err("%s: Invalid panel data\n", __func__); |
| 153 | return; |
| 154 | } |
| 155 | pinfo = &pdata->panel_info; |
| 156 | pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); |
| 157 | |
| 158 | if (mdss_dsi_is_ctrl_clk_slave(ctrl)) { |
| 159 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 160 | DSI_DYNAMIC_REFRESH_PLL_CTRL0, |
| 161 | DSIPHY_DLN0_CFG1, DSIPHY_DLN1_CFG1, |
| 162 | 0, 0); |
| 163 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 164 | DSI_DYNAMIC_REFRESH_PLL_CTRL1, |
| 165 | DSIPHY_DLN2_CFG1, DSIPHY_DLN3_CFG1, |
| 166 | 0x0, 0x0); |
| 167 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 168 | DSI_DYNAMIC_REFRESH_PLL_CTRL2, |
| 169 | DSIPHY_CKLN_CFG1, DSIPHY_DLN0_TIMING_CTRL_4, |
| 170 | 0x0, pd->timing_8996[0]); |
| 171 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 172 | DSI_DYNAMIC_REFRESH_PLL_CTRL3, |
| 173 | DSIPHY_DLN1_TIMING_CTRL_4, |
| 174 | DSIPHY_DLN2_TIMING_CTRL_4, |
| 175 | pd->timing_8996[8], |
| 176 | pd->timing_8996[16]); |
| 177 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 178 | DSI_DYNAMIC_REFRESH_PLL_CTRL4, |
| 179 | DSIPHY_DLN3_TIMING_CTRL_4, |
| 180 | DSIPHY_CKLN_TIMING_CTRL_4, |
| 181 | pd->timing_8996[24], |
| 182 | pd->timing_8996[32]); |
| 183 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 184 | DSI_DYNAMIC_REFRESH_PLL_CTRL5, |
| 185 | DSIPHY_DLN0_TIMING_CTRL_5, |
| 186 | DSIPHY_DLN1_TIMING_CTRL_5, |
| 187 | pd->timing_8996[1], |
| 188 | pd->timing_8996[9]); |
| 189 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 190 | DSI_DYNAMIC_REFRESH_PLL_CTRL6, |
| 191 | DSIPHY_DLN2_TIMING_CTRL_5, |
| 192 | DSIPHY_DLN3_TIMING_CTRL_5, |
| 193 | pd->timing_8996[17], |
| 194 | pd->timing_8996[25]); |
| 195 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 196 | DSI_DYNAMIC_REFRESH_PLL_CTRL7, |
| 197 | DSIPHY_CKLN_TIMING_CTRL_5, |
| 198 | DSIPHY_DLN0_TIMING_CTRL_6, |
| 199 | pd->timing_8996[33], |
| 200 | pd->timing_8996[2]); |
| 201 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 202 | DSI_DYNAMIC_REFRESH_PLL_CTRL8, |
| 203 | DSIPHY_DLN1_TIMING_CTRL_6, |
| 204 | DSIPHY_DLN2_TIMING_CTRL_6, |
| 205 | pd->timing_8996[10], |
| 206 | pd->timing_8996[18]); |
| 207 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 208 | DSI_DYNAMIC_REFRESH_PLL_CTRL9, |
| 209 | DSIPHY_DLN3_TIMING_CTRL_6, |
| 210 | DSIPHY_CKLN_TIMING_CTRL_6, |
| 211 | pd->timing_8996[26], |
| 212 | pd->timing_8996[34]); |
| 213 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 214 | DSI_DYNAMIC_REFRESH_PLL_CTRL10, |
| 215 | DSIPHY_DLN0_TIMING_CTRL_7, |
| 216 | DSIPHY_DLN1_TIMING_CTRL_7, |
| 217 | pd->timing_8996[3], |
| 218 | pd->timing_8996[11]); |
| 219 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 220 | DSI_DYNAMIC_REFRESH_PLL_CTRL11, |
| 221 | DSIPHY_DLN2_TIMING_CTRL_7, |
| 222 | DSIPHY_DLN3_TIMING_CTRL_7, |
| 223 | pd->timing_8996[19], |
| 224 | pd->timing_8996[27]); |
| 225 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 226 | DSI_DYNAMIC_REFRESH_PLL_CTRL12, |
| 227 | DSIPHY_CKLN_TIMING_CTRL_7, |
| 228 | DSIPHY_DLN0_TIMING_CTRL_8, |
| 229 | pd->timing_8996[35], |
| 230 | pd->timing_8996[4]); |
| 231 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 232 | DSI_DYNAMIC_REFRESH_PLL_CTRL13, |
| 233 | DSIPHY_DLN1_TIMING_CTRL_8, |
| 234 | DSIPHY_DLN2_TIMING_CTRL_8, |
| 235 | pd->timing_8996[12], |
| 236 | pd->timing_8996[20]); |
| 237 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 238 | DSI_DYNAMIC_REFRESH_PLL_CTRL14, |
| 239 | DSIPHY_DLN3_TIMING_CTRL_8, |
| 240 | DSIPHY_CKLN_TIMING_CTRL_8, |
| 241 | pd->timing_8996[28], |
| 242 | pd->timing_8996[36]); |
| 243 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 244 | DSI_DYNAMIC_REFRESH_PLL_CTRL15, |
| 245 | 0x0110, 0x0110, 0, 0); |
| 246 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 247 | DSI_DYNAMIC_REFRESH_PLL_CTRL16, |
| 248 | 0x0110, 0x0110, 0, 0); |
| 249 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 250 | DSI_DYNAMIC_REFRESH_PLL_CTRL17, |
| 251 | 0x0110, 0x0110, 0, 0); |
| 252 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 253 | DSI_DYNAMIC_REFRESH_PLL_CTRL18, |
| 254 | 0x0110, 0x0110, 0, 0); |
| 255 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 256 | DSI_DYNAMIC_REFRESH_PLL_CTRL19, |
| 257 | 0x0110, 0x0110, 0, 0); |
| 258 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 259 | DSI_DYNAMIC_REFRESH_PLL_CTRL20, |
| 260 | 0x110, 0x110, 0, 0); |
| 261 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 262 | DSI_DYNAMIC_REFRESH_PLL_CTRL21, |
| 263 | 0x110, 0x110, 0, 0); |
| 264 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 265 | DSI_DYNAMIC_REFRESH_PLL_CTRL22, |
| 266 | 0x110, 0x110, 0, 0); |
| 267 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 268 | DSI_DYNAMIC_REFRESH_PLL_CTRL23, |
| 269 | 0x110, 0x110, 0, 0); |
| 270 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 271 | DSI_DYNAMIC_REFRESH_PLL_CTRL24, |
| 272 | 0x110, 0x110, 0, 0); |
| 273 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 274 | DSI_DYNAMIC_REFRESH_PLL_CTRL25, |
| 275 | 0x110, 0x110, 0, 0); |
| 276 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 277 | DSI_DYNAMIC_REFRESH_PLL_CTRL26, |
| 278 | 0x110, 0x110, 0, 0); |
| 279 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 280 | DSI_DYNAMIC_REFRESH_PLL_CTRL27, |
| 281 | 0x110, 0x110, 0, 0); |
| 282 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 283 | DSI_DYNAMIC_REFRESH_PLL_CTRL28, |
| 284 | 0x110, 0x110, 0, 0); |
| 285 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 286 | DSI_DYNAMIC_REFRESH_PLL_CTRL29, |
| 287 | 0x110, 0x110, 0, 0); |
| 288 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 289 | DSI_DYNAMIC_REFRESH_PLL_CTRL30, |
| 290 | 0x110, 0x110, 0, 0); |
| 291 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 292 | DSI_DYNAMIC_REFRESH_PLL_CTRL31, |
| 293 | 0x110, 0x110, 0, 0); |
| 294 | MIPI_OUTP(ctrl->ctrl_base + |
| 295 | DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR, 0x0); |
| 296 | MIPI_OUTP(ctrl->ctrl_base + |
| 297 | DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2, 0x0); |
| 298 | } else { |
| 299 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 300 | DSI_DYNAMIC_REFRESH_PLL_CTRL0, |
| 301 | DSIPHY_CMN_GLBL_TEST_CTRL, |
| 302 | DSIPHY_PLL_PLL_BANDGAP, |
| 303 | glbl_tst_cntrl | BIT(1), 0x1); |
| 304 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 305 | DSI_DYNAMIC_REFRESH_PLL_CTRL1, |
| 306 | DSIPHY_PLL_RESETSM_CNTRL5, |
| 307 | DSIPHY_PLL_PLL_BANDGAP, |
| 308 | 0x0D, 0x03); |
| 309 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 310 | DSI_DYNAMIC_REFRESH_PLL_CTRL2, |
| 311 | DSIPHY_PLL_RESETSM_CNTRL5, |
| 312 | DSIPHY_CMN_PLL_CNTRL, |
| 313 | 0x1D, 0x00); |
| 314 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 315 | DSI_DYNAMIC_REFRESH_PLL_CTRL3, |
| 316 | DSIPHY_CMN_CTRL_1, DSIPHY_DLN0_CFG1, |
| 317 | 0x20, 0); |
| 318 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 319 | DSI_DYNAMIC_REFRESH_PLL_CTRL4, |
| 320 | DSIPHY_DLN1_CFG1, DSIPHY_DLN2_CFG1, |
| 321 | 0, 0); |
| 322 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 323 | DSI_DYNAMIC_REFRESH_PLL_CTRL5, |
| 324 | DSIPHY_DLN3_CFG1, DSIPHY_CKLN_CFG1, |
| 325 | 0, 0); |
| 326 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 327 | DSI_DYNAMIC_REFRESH_PLL_CTRL6, |
| 328 | DSIPHY_DLN0_TIMING_CTRL_4, |
| 329 | DSIPHY_DLN1_TIMING_CTRL_4, |
| 330 | pd->timing_8996[0], |
| 331 | pd->timing_8996[8]); |
| 332 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 333 | DSI_DYNAMIC_REFRESH_PLL_CTRL7, |
| 334 | DSIPHY_DLN2_TIMING_CTRL_4, |
| 335 | DSIPHY_DLN3_TIMING_CTRL_4, |
| 336 | pd->timing_8996[16], |
| 337 | pd->timing_8996[24]); |
| 338 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 339 | DSI_DYNAMIC_REFRESH_PLL_CTRL8, |
| 340 | DSIPHY_CKLN_TIMING_CTRL_4, |
| 341 | DSIPHY_DLN0_TIMING_CTRL_5, |
| 342 | pd->timing_8996[32], |
| 343 | pd->timing_8996[1]); |
| 344 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 345 | DSI_DYNAMIC_REFRESH_PLL_CTRL9, |
| 346 | DSIPHY_DLN1_TIMING_CTRL_5, |
| 347 | DSIPHY_DLN2_TIMING_CTRL_5, |
| 348 | pd->timing_8996[9], |
| 349 | pd->timing_8996[17]); |
| 350 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 351 | DSI_DYNAMIC_REFRESH_PLL_CTRL10, |
| 352 | DSIPHY_DLN3_TIMING_CTRL_5, |
| 353 | DSIPHY_CKLN_TIMING_CTRL_5, |
| 354 | pd->timing_8996[25], |
| 355 | pd->timing_8996[33]); |
| 356 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 357 | DSI_DYNAMIC_REFRESH_PLL_CTRL11, |
| 358 | DSIPHY_DLN0_TIMING_CTRL_6, |
| 359 | DSIPHY_DLN1_TIMING_CTRL_6, |
| 360 | pd->timing_8996[2], |
| 361 | pd->timing_8996[10]); |
| 362 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 363 | DSI_DYNAMIC_REFRESH_PLL_CTRL12, |
| 364 | DSIPHY_DLN2_TIMING_CTRL_6, |
| 365 | DSIPHY_DLN3_TIMING_CTRL_6, |
| 366 | pd->timing_8996[18], |
| 367 | pd->timing_8996[26]); |
| 368 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 369 | DSI_DYNAMIC_REFRESH_PLL_CTRL13, |
| 370 | DSIPHY_CKLN_TIMING_CTRL_6, |
| 371 | DSIPHY_DLN0_TIMING_CTRL_7, |
| 372 | pd->timing_8996[34], |
| 373 | pd->timing_8996[3]); |
| 374 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 375 | DSI_DYNAMIC_REFRESH_PLL_CTRL14, |
| 376 | DSIPHY_DLN1_TIMING_CTRL_7, |
| 377 | DSIPHY_DLN2_TIMING_CTRL_7, |
| 378 | pd->timing_8996[11], |
| 379 | pd->timing_8996[19]); |
| 380 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 381 | DSI_DYNAMIC_REFRESH_PLL_CTRL15, |
| 382 | DSIPHY_DLN3_TIMING_CTRL_7, |
| 383 | DSIPHY_CKLN_TIMING_CTRL_7, |
| 384 | pd->timing_8996[27], |
| 385 | pd->timing_8996[35]); |
| 386 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 387 | DSI_DYNAMIC_REFRESH_PLL_CTRL16, |
| 388 | DSIPHY_DLN0_TIMING_CTRL_8, |
| 389 | DSIPHY_DLN1_TIMING_CTRL_8, |
| 390 | pd->timing_8996[4], |
| 391 | pd->timing_8996[12]); |
| 392 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 393 | DSI_DYNAMIC_REFRESH_PLL_CTRL17, |
| 394 | DSIPHY_DLN2_TIMING_CTRL_8, |
| 395 | DSIPHY_DLN3_TIMING_CTRL_8, |
| 396 | pd->timing_8996[20], |
| 397 | pd->timing_8996[28]); |
| 398 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 399 | DSI_DYNAMIC_REFRESH_PLL_CTRL18, |
| 400 | DSIPHY_CKLN_TIMING_CTRL_8, |
| 401 | DSIPHY_CMN_CTRL_1, |
| 402 | pd->timing_8996[36], 0); |
| 403 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 404 | DSI_DYNAMIC_REFRESH_PLL_CTRL30, |
| 405 | DSIPHY_CMN_GLBL_TEST_CTRL, |
| 406 | DSIPHY_CMN_GLBL_TEST_CTRL, |
| 407 | ((glbl_tst_cntrl) & (~BIT(2))), |
| 408 | ((glbl_tst_cntrl) & (~BIT(2)))); |
| 409 | MDSS_DYN_REF_REG_W(ctrl->ctrl_base, |
| 410 | DSI_DYNAMIC_REFRESH_PLL_CTRL31, |
| 411 | DSIPHY_CMN_GLBL_TEST_CTRL, |
| 412 | DSIPHY_CMN_GLBL_TEST_CTRL, |
| 413 | ((glbl_tst_cntrl) & (~BIT(2))), |
| 414 | ((glbl_tst_cntrl) & (~BIT(2)))); |
| 415 | } |
| 416 | |
| 417 | wmb(); /* make sure phy timings are updated*/ |
| 418 | } |
| 419 | |
| 420 | static void mdss_dsi_ctrl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl) |
| 421 | { |
| 422 | /* start phy sw reset */ |
| 423 | MIPI_OUTP(ctrl->ctrl_base + 0x12c, 0x0001); |
| 424 | udelay(1000); |
| 425 | wmb(); /* make sure reset */ |
| 426 | /* end phy sw reset */ |
| 427 | MIPI_OUTP(ctrl->ctrl_base + 0x12c, 0x0000); |
| 428 | udelay(100); |
| 429 | wmb(); /* maek sure reset cleared */ |
| 430 | } |
| 431 | |
| 432 | int mdss_dsi_phy_pll_reset_status(struct mdss_dsi_ctrl_pdata *ctrl) |
| 433 | { |
| 434 | int rc; |
| 435 | u32 val; |
| 436 | u32 const sleep_us = 10, timeout_us = 100; |
| 437 | |
| 438 | pr_debug("%s: polling for RESETSM_READY_STATUS.CORE_READY\n", |
| 439 | __func__); |
| 440 | rc = readl_poll_timeout(ctrl->phy_io.base + 0x4cc, val, |
| 441 | (val & 0x1), sleep_us, timeout_us); |
| 442 | |
| 443 | return rc; |
| 444 | } |
| 445 | |
| 446 | static void mdss_dsi_phy_sw_reset_sub(struct mdss_dsi_ctrl_pdata *ctrl) |
| 447 | { |
| 448 | struct mdss_dsi_ctrl_pdata *sctrl = NULL; |
| 449 | struct dsi_shared_data *sdata; |
| 450 | struct mdss_dsi_ctrl_pdata *octrl; |
| 451 | u32 reg_val = 0; |
| 452 | |
| 453 | if (ctrl == NULL) { |
| 454 | pr_err("%s: Invalid input data\n", __func__); |
| 455 | return; |
| 456 | } |
| 457 | |
| 458 | sdata = ctrl->shared_data; |
| 459 | octrl = mdss_dsi_get_other_ctrl(ctrl); |
| 460 | |
| 461 | if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) { |
| 462 | if (mdss_dsi_is_ctrl_clk_master(ctrl)) |
| 463 | sctrl = mdss_dsi_get_ctrl_clk_slave(); |
| 464 | else |
| 465 | return; |
| 466 | } |
| 467 | |
| 468 | /* |
| 469 | * For dual dsi case if we do DSI PHY sw reset, |
| 470 | * this will reset DSI PHY regulators also. |
| 471 | * Since DSI PHY regulator is shared among both |
| 472 | * the DSI controllers, we should not do DSI PHY |
| 473 | * sw reset when the other DSI controller is still |
| 474 | * active. |
| 475 | */ |
| 476 | mutex_lock(&sdata->phy_reg_lock); |
| 477 | if ((mdss_dsi_is_hw_config_dual(sdata) && |
| 478 | (octrl && octrl->is_phyreg_enabled))) { |
| 479 | /* start phy lane and HW reset */ |
| 480 | reg_val = MIPI_INP(ctrl->ctrl_base + 0x12c); |
| 481 | reg_val |= (BIT(16) | BIT(8)); |
| 482 | MIPI_OUTP(ctrl->ctrl_base + 0x12c, reg_val); |
| 483 | /* wait for 1ms as per HW design */ |
| 484 | usleep_range(1000, 2000); |
| 485 | /* ensure phy lane and HW reset starts */ |
| 486 | wmb(); |
| 487 | /* end phy lane and HW reset */ |
| 488 | reg_val = MIPI_INP(ctrl->ctrl_base + 0x12c); |
| 489 | reg_val &= ~(BIT(16) | BIT(8)); |
| 490 | MIPI_OUTP(ctrl->ctrl_base + 0x12c, reg_val); |
| 491 | /* wait for 100us as per HW design */ |
| 492 | usleep_range(100, 200); |
| 493 | /* ensure phy lane and HW reset ends */ |
| 494 | wmb(); |
| 495 | } else { |
| 496 | /* start phy sw reset */ |
| 497 | mdss_dsi_ctrl_phy_reset(ctrl); |
| 498 | if (sctrl) |
| 499 | mdss_dsi_ctrl_phy_reset(sctrl); |
| 500 | |
| 501 | } |
| 502 | mutex_unlock(&sdata->phy_reg_lock); |
| 503 | } |
| 504 | |
| 505 | void mdss_dsi_phy_sw_reset(struct mdss_dsi_ctrl_pdata *ctrl) |
| 506 | { |
| 507 | struct mdss_dsi_ctrl_pdata *sctrl = NULL; |
| 508 | struct dsi_shared_data *sdata; |
| 509 | |
| 510 | if (ctrl == NULL) { |
| 511 | pr_err("%s: Invalid input data\n", __func__); |
| 512 | return; |
| 513 | } |
| 514 | |
| 515 | sdata = ctrl->shared_data; |
| 516 | |
| 517 | /* |
| 518 | * When operating in split display mode, make sure that the PHY reset |
| 519 | * is only done from the clock master. This will ensure that the PLL is |
| 520 | * off when PHY reset is called. |
| 521 | */ |
| 522 | if (mdss_dsi_is_ctrl_clk_slave(ctrl)) |
| 523 | return; |
| 524 | |
| 525 | mdss_dsi_phy_sw_reset_sub(ctrl); |
| 526 | |
| 527 | if (mdss_dsi_is_ctrl_clk_master(ctrl)) { |
| 528 | sctrl = mdss_dsi_get_ctrl_clk_slave(); |
| 529 | if (sctrl) |
| 530 | mdss_dsi_phy_sw_reset_sub(sctrl); |
| 531 | else |
| 532 | pr_warn("%s: unable to get slave ctrl\n", __func__); |
| 533 | } |
| 534 | |
| 535 | /* All other quirks go here */ |
| 536 | if ((sdata->hw_rev == MDSS_DSI_HW_REV_103) && |
| 537 | !mdss_dsi_is_hw_config_dual(sdata) && |
| 538 | mdss_dsi_is_right_ctrl(ctrl)) { |
| 539 | |
| 540 | /* |
| 541 | * phy sw reset will wipe out the pll settings for PLL. |
| 542 | * Need to explicitly turn off PLL1 if unused to avoid |
| 543 | * current leakage issues. |
| 544 | */ |
| 545 | if ((mdss_dsi_is_hw_config_split(sdata) || |
| 546 | mdss_dsi_is_pll_src_pll0(sdata)) && |
| 547 | ctrl->vco_dummy_clk) { |
| 548 | pr_debug("Turn off unused PLL1 registers\n"); |
| 549 | clk_set_rate(ctrl->vco_dummy_clk, 1); |
| 550 | } |
| 551 | } |
| 552 | } |
| 553 | |
| 554 | static void mdss_dsi_phy_regulator_disable(struct mdss_dsi_ctrl_pdata *ctrl) |
| 555 | { |
| 556 | if (!ctrl) { |
| 557 | pr_err("%s: Invalid input data\n", __func__); |
| 558 | return; |
| 559 | } |
| 560 | |
| 561 | if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) |
| 562 | return; |
| 563 | |
| 564 | MIPI_OUTP(ctrl->phy_regulator_io.base + 0x018, 0x000); |
| 565 | } |
| 566 | |
| 567 | static void mdss_dsi_phy_shutdown(struct mdss_dsi_ctrl_pdata *ctrl) |
| 568 | { |
| 569 | if (!ctrl) { |
| 570 | pr_err("%s: Invalid input data\n", __func__); |
| 571 | return; |
| 572 | } |
| 573 | |
| 574 | if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) { |
| 575 | MIPI_OUTP(ctrl->phy_io.base + DSIPHY_PLL_CLKBUFLR_EN, 0); |
| 576 | MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_GLBL_TEST_CTRL, 0); |
| 577 | MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0); |
| 578 | } else { |
| 579 | MIPI_OUTP(ctrl->phy_io.base + MDSS_DSI_DSIPHY_CTRL_0, 0x000); |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | /** |
| 584 | * mdss_dsi_lp_cd_rx() -- enable LP and CD at receiving |
| 585 | * @ctrl: pointer to DSI controller structure |
| 586 | * |
| 587 | * LP: low power |
| 588 | * CD: contention detection |
| 589 | */ |
| 590 | void mdss_dsi_lp_cd_rx(struct mdss_dsi_ctrl_pdata *ctrl) |
| 591 | { |
| 592 | struct mdss_dsi_phy_ctrl *pd; |
| 593 | |
| 594 | if (!ctrl) { |
| 595 | pr_err("%s: Invalid input data\n", __func__); |
| 596 | return; |
| 597 | } |
| 598 | |
| 599 | if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) |
| 600 | return; |
| 601 | |
| 602 | pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); |
| 603 | |
| 604 | MIPI_OUTP((ctrl->phy_io.base) + 0x0188, pd->strength[1]); |
| 605 | /* Strength ctrl 1, LP Rx + CD Rxcontention detection */ |
| 606 | wmb(); |
| 607 | } |
| 608 | |
| 609 | static void mdss_dsi_28nm_phy_regulator_enable( |
| 610 | struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 611 | { |
| 612 | struct mdss_dsi_phy_ctrl *pd; |
| 613 | |
| 614 | pd = &(((ctrl_pdata->panel_data).panel_info.mipi).dsi_phy_db); |
| 615 | |
| 616 | if (pd->reg_ldo_mode) { |
| 617 | /* Regulator ctrl 0 */ |
| 618 | MIPI_OUTP(ctrl_pdata->phy_regulator_io.base, 0x0); |
| 619 | /* Regulator ctrl - CAL_PWR_CFG */ |
| 620 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 621 | + 0x18, pd->regulator[6]); |
| 622 | /* Add H/w recommended delay */ |
| 623 | udelay(1000); |
| 624 | /* Regulator ctrl - TEST */ |
| 625 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 626 | + 0x14, pd->regulator[5]); |
| 627 | /* Regulator ctrl 3 */ |
| 628 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 629 | + 0xc, pd->regulator[3]); |
| 630 | /* Regulator ctrl 2 */ |
| 631 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 632 | + 0x8, pd->regulator[2]); |
| 633 | /* Regulator ctrl 1 */ |
| 634 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 635 | + 0x4, pd->regulator[1]); |
| 636 | /* Regulator ctrl 4 */ |
| 637 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 638 | + 0x10, pd->regulator[4]); |
| 639 | /* LDO ctrl */ |
| 640 | if ((ctrl_pdata->shared_data->hw_rev == |
| 641 | MDSS_DSI_HW_REV_103_1) |
| 642 | || (ctrl_pdata->shared_data->hw_rev == |
| 643 | MDSS_DSI_HW_REV_104_2)) |
| 644 | MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x05); |
| 645 | else |
| 646 | MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x0d); |
| 647 | } else { |
| 648 | /* Regulator ctrl 0 */ |
| 649 | MIPI_OUTP(ctrl_pdata->phy_regulator_io.base, |
| 650 | 0x0); |
| 651 | /* Regulator ctrl - CAL_PWR_CFG */ |
| 652 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 653 | + 0x18, pd->regulator[6]); |
| 654 | /* Add H/w recommended delay */ |
| 655 | udelay(1000); |
| 656 | /* Regulator ctrl 1 */ |
| 657 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 658 | + 0x4, pd->regulator[1]); |
| 659 | /* Regulator ctrl 2 */ |
| 660 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 661 | + 0x8, pd->regulator[2]); |
| 662 | /* Regulator ctrl 3 */ |
| 663 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 664 | + 0xc, pd->regulator[3]); |
| 665 | /* Regulator ctrl 4 */ |
| 666 | MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) |
| 667 | + 0x10, pd->regulator[4]); |
| 668 | /* LDO ctrl */ |
| 669 | MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x00); |
| 670 | /* Regulator ctrl 0 */ |
| 671 | MIPI_OUTP(ctrl_pdata->phy_regulator_io.base, |
| 672 | pd->regulator[0]); |
| 673 | } |
| 674 | } |
| 675 | |
| 676 | static void mdss_dsi_28nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 677 | { |
| 678 | struct mdss_dsi_phy_ctrl *pd; |
| 679 | int i, off, ln, offset; |
| 680 | |
| 681 | if (!ctrl_pdata) { |
| 682 | pr_err("%s: Invalid input data\n", __func__); |
| 683 | return; |
| 684 | } |
| 685 | |
| 686 | pd = &(((ctrl_pdata->panel_data).panel_info.mipi).dsi_phy_db); |
| 687 | |
| 688 | /* Strength ctrl 0 for 28nm PHY*/ |
| 689 | if ((ctrl_pdata->shared_data->hw_rev <= MDSS_DSI_HW_REV_104_2) && |
| 690 | (ctrl_pdata->shared_data->hw_rev != MDSS_DSI_HW_REV_103)) { |
| 691 | MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0170, 0x5b); |
| 692 | MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0184, pd->strength[0]); |
| 693 | /* make sure PHY strength ctrl is set */ |
| 694 | wmb(); |
| 695 | } |
| 696 | |
| 697 | off = 0x0140; /* phy timing ctrl 0 - 11 */ |
| 698 | for (i = 0; i < 12; i++) { |
| 699 | MIPI_OUTP((ctrl_pdata->phy_io.base) + off, pd->timing[i]); |
| 700 | /* make sure phy timing register is programed */ |
| 701 | wmb(); |
| 702 | off += 4; |
| 703 | } |
| 704 | |
| 705 | /* 4 lanes + clk lane configuration */ |
| 706 | /* lane config n * (0 - 4) & DataPath setup */ |
| 707 | for (ln = 0; ln < 5; ln++) { |
| 708 | off = (ln * 0x40); |
| 709 | for (i = 0; i < 9; i++) { |
| 710 | offset = i + (ln * 9); |
| 711 | MIPI_OUTP((ctrl_pdata->phy_io.base) + off, |
| 712 | pd->lanecfg[offset]); |
| 713 | /* make sure lane config register is programed */ |
| 714 | wmb(); |
| 715 | off += 4; |
| 716 | } |
| 717 | } |
| 718 | |
| 719 | MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0180, 0x0a); |
| 720 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_4 */ |
| 721 | wmb(); |
| 722 | |
| 723 | /* DSI_0_PHY_DSIPHY_GLBL_TEST_CTRL */ |
| 724 | if (!mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data)) { |
| 725 | MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x01d4, 0x01); |
| 726 | } else { |
| 727 | if (((ctrl_pdata->panel_data).panel_info.pdest == DISPLAY_1) || |
| 728 | (ctrl_pdata->shared_data->hw_rev == MDSS_DSI_HW_REV_103_1)) |
| 729 | MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x01d4, 0x01); |
| 730 | else |
| 731 | MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x01d4, 0x00); |
| 732 | } |
| 733 | /* ensure DSIPHY_GLBL_TEST_CTRL is set */ |
| 734 | wmb(); |
| 735 | |
| 736 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */ |
| 737 | MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0170, 0x5f); |
| 738 | /* make sure PHY lanes are powered on */ |
| 739 | wmb(); |
| 740 | |
| 741 | off = 0x01b4; /* phy BIST ctrl 0 - 5 */ |
| 742 | for (i = 0; i < 6; i++) { |
| 743 | MIPI_OUTP((ctrl_pdata->phy_io.base) + off, pd->bistctrl[i]); |
| 744 | wmb(); /* make sure PHY bit control is configured */ |
| 745 | off += 4; |
| 746 | } |
| 747 | |
| 748 | } |
| 749 | |
| 750 | static void mdss_dsi_20nm_phy_regulator_enable(struct mdss_dsi_ctrl_pdata |
| 751 | *ctrl_pdata) |
| 752 | { |
| 753 | struct mdss_dsi_phy_ctrl *pd; |
| 754 | void __iomem *phy_io_base; |
| 755 | |
| 756 | pd = &(((ctrl_pdata->panel_data).panel_info.mipi).dsi_phy_db); |
| 757 | phy_io_base = ctrl_pdata->phy_regulator_io.base; |
| 758 | |
| 759 | if (pd->regulator_len != 7) { |
| 760 | pr_err("%s: wrong regulator settings\n", __func__); |
| 761 | return; |
| 762 | } |
| 763 | |
| 764 | if (pd->reg_ldo_mode) { |
| 765 | MIPI_OUTP(ctrl_pdata->phy_io.base + MDSS_DSI_DSIPHY_LDO_CNTRL, |
| 766 | 0x1d); |
| 767 | } else { |
| 768 | MIPI_OUTP(phy_io_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_1, |
| 769 | pd->regulator[1]); |
| 770 | MIPI_OUTP(phy_io_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_2, |
| 771 | pd->regulator[2]); |
| 772 | MIPI_OUTP(phy_io_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_3, |
| 773 | pd->regulator[3]); |
| 774 | MIPI_OUTP(phy_io_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_4, |
| 775 | pd->regulator[4]); |
| 776 | MIPI_OUTP(phy_io_base + MDSS_DSI_DSIPHY_REGULATOR_CAL_PWR_CFG, |
| 777 | pd->regulator[6]); |
| 778 | MIPI_OUTP(ctrl_pdata->phy_io.base + MDSS_DSI_DSIPHY_LDO_CNTRL, |
| 779 | 0x00); |
| 780 | MIPI_OUTP(phy_io_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_0, |
| 781 | pd->regulator[0]); |
| 782 | } |
| 783 | } |
| 784 | |
| 785 | static void mdss_dsi_20nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 786 | { |
| 787 | struct mdss_dsi_phy_ctrl *pd; |
| 788 | int i, off, ln, offset; |
| 789 | |
| 790 | pd = &(((ctrl_pdata->panel_data).panel_info.mipi).dsi_phy_db); |
| 791 | |
| 792 | if (pd->strength_len != 2) { |
| 793 | pr_err("%s: wrong strength ctrl\n", __func__); |
| 794 | return; |
| 795 | } |
| 796 | |
| 797 | MIPI_OUTP((ctrl_pdata->phy_io.base) + MDSS_DSI_DSIPHY_STRENGTH_CTRL_0, |
| 798 | pd->strength[0]); |
| 799 | |
| 800 | |
| 801 | if (!mdss_dsi_is_hw_config_dual(ctrl_pdata->shared_data)) { |
| 802 | if (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) || |
| 803 | mdss_dsi_is_left_ctrl(ctrl_pdata) || |
| 804 | (mdss_dsi_is_right_ctrl(ctrl_pdata) && |
| 805 | mdss_dsi_is_pll_src_pll0(ctrl_pdata->shared_data))) |
| 806 | MIPI_OUTP((ctrl_pdata->phy_io.base) + |
| 807 | MDSS_DSI_DSIPHY_GLBL_TEST_CTRL, 0x00); |
| 808 | else |
| 809 | MIPI_OUTP((ctrl_pdata->phy_io.base) + |
| 810 | MDSS_DSI_DSIPHY_GLBL_TEST_CTRL, 0x01); |
| 811 | } else { |
| 812 | if (mdss_dsi_is_left_ctrl(ctrl_pdata)) |
| 813 | MIPI_OUTP((ctrl_pdata->phy_io.base) + |
| 814 | MDSS_DSI_DSIPHY_GLBL_TEST_CTRL, 0x00); |
| 815 | else |
| 816 | MIPI_OUTP((ctrl_pdata->phy_io.base) + |
| 817 | MDSS_DSI_DSIPHY_GLBL_TEST_CTRL, 0x01); |
| 818 | } |
| 819 | |
| 820 | if (pd->lanecfg_len != 45) { |
| 821 | pr_err("%s: wrong lane cfg\n", __func__); |
| 822 | return; |
| 823 | } |
| 824 | |
| 825 | /* 4 lanes + clk lane configuration */ |
| 826 | /* lane config n * (0 - 4) & DataPath setup */ |
| 827 | for (ln = 0; ln < 5; ln++) { |
| 828 | off = (ln * 0x40); |
| 829 | for (i = 0; i < 9; i++) { |
| 830 | offset = i + (ln * 9); |
| 831 | MIPI_OUTP((ctrl_pdata->phy_io.base) + off, |
| 832 | pd->lanecfg[offset]); |
| 833 | /* make sure lane config register is programed */ |
| 834 | wmb(); |
| 835 | off += 4; |
| 836 | } |
| 837 | } |
| 838 | |
| 839 | off = 0; /* phy timing ctrl 0 - 11 */ |
| 840 | for (i = 0; i < 12; i++) { |
| 841 | MIPI_OUTP((ctrl_pdata->phy_io.base) + |
| 842 | MDSS_DSI_DSIPHY_TIMING_CTRL_0 + off, pd->timing[i]); |
| 843 | wmb(); /* make sure phy timing register is programed */ |
| 844 | off += 4; |
| 845 | } |
| 846 | |
| 847 | MIPI_OUTP((ctrl_pdata->phy_io.base) + MDSS_DSI_DSIPHY_CTRL_1, 0); |
| 848 | /* make sure everything is written before enable */ |
| 849 | wmb(); |
| 850 | MIPI_OUTP((ctrl_pdata->phy_io.base) + MDSS_DSI_DSIPHY_CTRL_0, 0x7f); |
| 851 | } |
| 852 | |
| 853 | static void mdss_dsi_8996_pll_source_standalone( |
| 854 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 855 | { |
| 856 | u32 data; |
| 857 | |
| 858 | /* |
| 859 | * pll right output enabled |
| 860 | * bit clk select from left |
| 861 | */ |
| 862 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_PLL_CLKBUFLR_EN, 0x01); |
| 863 | data = MIPI_INP((ctrl->phy_io.base) + DSIPHY_CMN_GLBL_TEST_CTRL); |
| 864 | data &= ~BIT(2); |
| 865 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_GLBL_TEST_CTRL, data); |
| 866 | } |
| 867 | |
| 868 | static void mdss_dsi_8996_pll_source_from_right( |
| 869 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 870 | { |
| 871 | u32 data; |
| 872 | |
| 873 | /* |
| 874 | * pll left + right output disabled |
| 875 | * bit clk select from right |
| 876 | */ |
| 877 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_PLL_CLKBUFLR_EN, 0x00); |
| 878 | data = MIPI_INP((ctrl->phy_io.base) + DSIPHY_CMN_GLBL_TEST_CTRL); |
| 879 | data |= BIT(2); |
| 880 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_GLBL_TEST_CTRL, data); |
| 881 | |
| 882 | /* enable bias current for pll1 during split display case */ |
| 883 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_PLL_PLL_BANDGAP, 0x3); |
| 884 | } |
| 885 | |
| 886 | static void mdss_dsi_8996_pll_source_from_left( |
| 887 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 888 | { |
| 889 | u32 data; |
| 890 | |
| 891 | /* |
| 892 | * pll left + right output enabled |
| 893 | * bit clk select from left |
| 894 | */ |
| 895 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_PLL_CLKBUFLR_EN, 0x03); |
| 896 | data = MIPI_INP((ctrl->phy_io.base) + DSIPHY_CMN_GLBL_TEST_CTRL); |
| 897 | data &= ~BIT(2); |
| 898 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_GLBL_TEST_CTRL, data); |
| 899 | } |
| 900 | |
| 901 | static void mdss_dsi_8996_phy_regulator_enable( |
| 902 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 903 | { |
| 904 | struct mdss_dsi_phy_ctrl *pd; |
| 905 | int j, off, ln, cnt, ln_off; |
| 906 | char *ip; |
| 907 | void __iomem *base; |
| 908 | |
| 909 | pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); |
| 910 | /* 4 lanes + clk lane configuration */ |
| 911 | for (ln = 0; ln < 5; ln++) { |
| 912 | /* |
| 913 | * data lane offset from base: 0x100 |
| 914 | * data lane size: 0x80 |
| 915 | */ |
| 916 | base = ctrl->phy_io.base + |
| 917 | DATALANE_OFFSET_FROM_BASE_8996; |
| 918 | base += (ln * DATALANE_SIZE_8996); /* lane base */ |
| 919 | |
| 920 | /* vreg ctrl, 1 * 5 */ |
| 921 | cnt = 1; |
| 922 | ln_off = cnt * ln; |
| 923 | ip = &pd->regulator[ln_off]; |
| 924 | off = 0x64; |
| 925 | for (j = 0; j < cnt; j++, off += 4) |
| 926 | MIPI_OUTP(base + off, *ip++); |
| 927 | } |
| 928 | |
| 929 | wmb(); /* make sure registers committed */ |
| 930 | |
| 931 | } |
| 932 | |
| 933 | static void mdss_dsi_8996_phy_power_off( |
| 934 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 935 | { |
| 936 | int ln; |
| 937 | void __iomem *base; |
| 938 | u32 data; |
| 939 | |
| 940 | /* Turn off PLL power */ |
| 941 | data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0); |
| 942 | MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data & ~BIT(7)); |
| 943 | |
| 944 | /* 4 lanes + clk lane configuration */ |
| 945 | for (ln = 0; ln < 5; ln++) { |
| 946 | base = ctrl->phy_io.base + |
| 947 | DATALANE_OFFSET_FROM_BASE_8996; |
| 948 | base += (ln * DATALANE_SIZE_8996); /* lane base */ |
| 949 | |
| 950 | /* turn off phy ldo */ |
| 951 | MIPI_OUTP(base + DSIPHY_LANE_VREG_CNTRL, 0x1c); |
| 952 | } |
| 953 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_LDO_CNTRL, 0x1c); |
| 954 | |
| 955 | /* 4 lanes + clk lane configuration */ |
| 956 | for (ln = 0; ln < 5; ln++) { |
| 957 | base = ctrl->phy_io.base + |
| 958 | DATALANE_OFFSET_FROM_BASE_8996; |
| 959 | base += (ln * DATALANE_SIZE_8996); /* lane base */ |
| 960 | |
| 961 | MIPI_OUTP(base + DSIPHY_LANE_STRENGTH_CTRL_1, 0x0); |
| 962 | } |
| 963 | |
| 964 | wmb(); /* make sure registers committed */ |
| 965 | } |
| 966 | |
| 967 | static void mdss_dsi_phy_power_off( |
| 968 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 969 | { |
| 970 | struct mdss_panel_info *pinfo; |
| 971 | |
| 972 | if (ctrl->phy_power_off) |
| 973 | return; |
| 974 | |
| 975 | pinfo = &ctrl->panel_data.panel_info; |
| 976 | |
| 977 | if ((ctrl->shared_data->phy_rev != DSI_PHY_REV_20) || |
| 978 | !pinfo->allow_phy_power_off) { |
| 979 | pr_debug("%s: ctrl%d phy rev:%d panel support for phy off:%d\n", |
| 980 | __func__, ctrl->ndx, ctrl->shared_data->phy_rev, |
| 981 | pinfo->allow_phy_power_off); |
| 982 | return; |
| 983 | } |
| 984 | |
| 985 | /* supported for phy rev 2.0 and if panel allows it*/ |
| 986 | mdss_dsi_8996_phy_power_off(ctrl); |
| 987 | |
| 988 | ctrl->phy_power_off = true; |
| 989 | } |
| 990 | |
| 991 | static void mdss_dsi_8996_phy_power_on( |
| 992 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 993 | { |
| 994 | int j, off, ln, cnt, ln_off; |
| 995 | void __iomem *base; |
| 996 | struct mdss_dsi_phy_ctrl *pd; |
| 997 | char *ip; |
| 998 | u32 data; |
| 999 | |
| 1000 | pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); |
| 1001 | |
| 1002 | /* 4 lanes + clk lane configuration */ |
| 1003 | for (ln = 0; ln < 5; ln++) { |
| 1004 | base = ctrl->phy_io.base + |
| 1005 | DATALANE_OFFSET_FROM_BASE_8996; |
| 1006 | base += (ln * DATALANE_SIZE_8996); /* lane base */ |
| 1007 | |
| 1008 | /* strength, 2 * 5 */ |
| 1009 | cnt = 2; |
| 1010 | ln_off = cnt * ln; |
| 1011 | ip = &pd->strength[ln_off]; |
| 1012 | off = 0x38; |
| 1013 | for (j = 0; j < cnt; j++, off += 4) |
| 1014 | MIPI_OUTP(base + off, *ip++); |
| 1015 | } |
| 1016 | |
| 1017 | mdss_dsi_8996_phy_regulator_enable(ctrl); |
| 1018 | |
| 1019 | /* Turn on PLL power */ |
| 1020 | data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0); |
| 1021 | MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data | BIT(7)); |
| 1022 | } |
| 1023 | |
| 1024 | static void mdss_dsi_phy_power_on( |
| 1025 | struct mdss_dsi_ctrl_pdata *ctrl, bool mmss_clamp) |
| 1026 | { |
| 1027 | if (mmss_clamp && !ctrl->phy_power_off) |
| 1028 | mdss_dsi_phy_init(ctrl); |
| 1029 | else if ((ctrl->shared_data->phy_rev == DSI_PHY_REV_20) && |
| 1030 | ctrl->phy_power_off) |
| 1031 | mdss_dsi_8996_phy_power_on(ctrl); |
| 1032 | |
| 1033 | ctrl->phy_power_off = false; |
| 1034 | } |
| 1035 | |
| 1036 | static void mdss_dsi_8996_phy_config(struct mdss_dsi_ctrl_pdata *ctrl) |
| 1037 | { |
| 1038 | struct mdss_dsi_phy_ctrl *pd; |
| 1039 | int j, off, ln, cnt, ln_off; |
| 1040 | char *ip; |
| 1041 | void __iomem *base; |
| 1042 | |
| 1043 | pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); |
| 1044 | |
| 1045 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_LDO_CNTRL, 0x1c); |
| 1046 | |
| 1047 | /* clk_en */ |
| 1048 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_GLBL_TEST_CTRL, 0x1); |
| 1049 | |
| 1050 | if (pd->lanecfg_len != 20) { |
| 1051 | pr_err("%s: wrong lane cfg\n", __func__); |
| 1052 | return; |
| 1053 | } |
| 1054 | |
| 1055 | if (pd->strength_len != 10) { |
| 1056 | pr_err("%s: wrong strength ctrl\n", __func__); |
| 1057 | return; |
| 1058 | } |
| 1059 | |
| 1060 | if (pd->regulator_len != 5) { |
| 1061 | pr_err("%s: wrong regulator setting\n", __func__); |
| 1062 | return; |
| 1063 | } |
| 1064 | |
| 1065 | /* 4 lanes + clk lane configuration */ |
| 1066 | for (ln = 0; ln < 5; ln++) { |
| 1067 | /* |
| 1068 | * data lane offset from base: 0x100 |
| 1069 | * data lane size: 0x80 |
| 1070 | */ |
| 1071 | base = ctrl->phy_io.base + |
| 1072 | DATALANE_OFFSET_FROM_BASE_8996; |
| 1073 | base += (ln * DATALANE_SIZE_8996); /* lane base */ |
| 1074 | |
| 1075 | /* lane cfg, 4 * 5 */ |
| 1076 | cnt = 4; |
| 1077 | ln_off = cnt * ln; |
| 1078 | ip = &pd->lanecfg[ln_off]; |
| 1079 | off = 0x0; |
| 1080 | for (j = 0; j < cnt; j++) { |
| 1081 | MIPI_OUTP(base + off, *ip++); |
| 1082 | off += 4; |
| 1083 | } |
| 1084 | |
| 1085 | /* test str */ |
| 1086 | MIPI_OUTP(base + 0x14, 0x0088); /* fixed */ |
| 1087 | |
| 1088 | /* phy timing, 8 * 5 */ |
| 1089 | cnt = 8; |
| 1090 | ln_off = cnt * ln; |
| 1091 | ip = &pd->timing_8996[ln_off]; |
| 1092 | off = 0x18; |
| 1093 | for (j = 0; j < cnt; j++, off += 4) |
| 1094 | MIPI_OUTP(base + off, *ip++); |
| 1095 | |
| 1096 | /* strength, 2 * 5 */ |
| 1097 | cnt = 2; |
| 1098 | ln_off = cnt * ln; |
| 1099 | ip = &pd->strength[ln_off]; |
| 1100 | off = 0x38; |
| 1101 | for (j = 0; j < cnt; j++, off += 4) |
| 1102 | MIPI_OUTP(base + off, *ip++); |
| 1103 | } |
| 1104 | |
| 1105 | wmb(); /* make sure registers committed */ |
| 1106 | |
| 1107 | /* reset digital block */ |
| 1108 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_CTRL_1, 0x80); |
| 1109 | udelay(100); |
| 1110 | MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_CTRL_1, 0x00); |
| 1111 | |
| 1112 | if (mdss_dsi_is_hw_config_split(ctrl->shared_data)) { |
| 1113 | if (mdss_dsi_is_left_ctrl(ctrl)) |
| 1114 | mdss_dsi_8996_pll_source_from_left(ctrl); |
| 1115 | else |
| 1116 | mdss_dsi_8996_pll_source_from_right(ctrl); |
| 1117 | } else { |
| 1118 | if (mdss_dsi_is_right_ctrl(ctrl) && |
| 1119 | mdss_dsi_is_pll_src_pll0(ctrl->shared_data)) |
| 1120 | mdss_dsi_8996_pll_source_from_left(ctrl); |
| 1121 | else |
| 1122 | mdss_dsi_8996_pll_source_standalone(ctrl); |
| 1123 | } |
| 1124 | |
| 1125 | MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f); |
| 1126 | wmb(); /* make sure registers committed */ |
| 1127 | } |
| 1128 | |
| 1129 | static void mdss_dsi_phy_regulator_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, |
| 1130 | bool enable) |
| 1131 | { |
| 1132 | struct mdss_dsi_ctrl_pdata *other_ctrl; |
| 1133 | struct dsi_shared_data *sdata; |
| 1134 | |
| 1135 | if (!ctrl) { |
| 1136 | pr_err("%s: Invalid input data\n", __func__); |
| 1137 | return; |
| 1138 | } |
| 1139 | |
| 1140 | sdata = ctrl->shared_data; |
| 1141 | other_ctrl = mdss_dsi_get_other_ctrl(ctrl); |
| 1142 | |
| 1143 | mutex_lock(&sdata->phy_reg_lock); |
| 1144 | if (enable) { |
| 1145 | if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) { |
| 1146 | mdss_dsi_8996_phy_regulator_enable(ctrl); |
| 1147 | } else { |
| 1148 | switch (ctrl->shared_data->hw_rev) { |
| 1149 | case MDSS_DSI_HW_REV_103: |
| 1150 | mdss_dsi_20nm_phy_regulator_enable(ctrl); |
| 1151 | break; |
| 1152 | default: |
| 1153 | /* |
| 1154 | * For dual dsi case, do not reconfigure dsi phy |
| 1155 | * regulator if the other dsi controller is still |
| 1156 | * active. |
| 1157 | */ |
| 1158 | if (!mdss_dsi_is_hw_config_dual(sdata) || |
| 1159 | (other_ctrl && (!other_ctrl->is_phyreg_enabled |
| 1160 | || other_ctrl->mmss_clamp))) |
| 1161 | mdss_dsi_28nm_phy_regulator_enable(ctrl); |
| 1162 | break; |
| 1163 | } |
| 1164 | } |
| 1165 | ctrl->is_phyreg_enabled = 1; |
| 1166 | } else { |
| 1167 | /* |
| 1168 | * In split-dsi/dual-dsi configuration, the dsi phy regulator |
| 1169 | * should be turned off only when both the DSI devices are |
| 1170 | * going to be turned off since it is shared. |
| 1171 | */ |
| 1172 | if (mdss_dsi_is_hw_config_split(ctrl->shared_data) || |
| 1173 | mdss_dsi_is_hw_config_dual(ctrl->shared_data)) { |
| 1174 | if (other_ctrl && !other_ctrl->is_phyreg_enabled) |
| 1175 | mdss_dsi_phy_regulator_disable(ctrl); |
| 1176 | } else { |
| 1177 | mdss_dsi_phy_regulator_disable(ctrl); |
| 1178 | } |
| 1179 | ctrl->is_phyreg_enabled = 0; |
| 1180 | } |
| 1181 | mutex_unlock(&sdata->phy_reg_lock); |
| 1182 | } |
| 1183 | |
| 1184 | static void mdss_dsi_phy_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, bool enable) |
| 1185 | { |
| 1186 | struct mdss_dsi_ctrl_pdata *other_ctrl; |
| 1187 | |
| 1188 | if (!ctrl) { |
| 1189 | pr_err("%s: Invalid input data\n", __func__); |
| 1190 | return; |
| 1191 | } |
| 1192 | |
| 1193 | if (enable) { |
| 1194 | |
| 1195 | if (ctrl->shared_data->phy_rev == DSI_PHY_REV_20) { |
| 1196 | mdss_dsi_8996_phy_config(ctrl); |
| 1197 | } else { |
| 1198 | switch (ctrl->shared_data->hw_rev) { |
| 1199 | case MDSS_DSI_HW_REV_103: |
| 1200 | mdss_dsi_20nm_phy_config(ctrl); |
| 1201 | break; |
| 1202 | default: |
| 1203 | mdss_dsi_28nm_phy_config(ctrl); |
| 1204 | break; |
| 1205 | } |
| 1206 | } |
| 1207 | } else { |
| 1208 | /* |
| 1209 | * In split-dsi configuration, the phy should be disabled for |
| 1210 | * the first controller only when the second controller is |
| 1211 | * disabled. This is true regardless of whether broadcast |
| 1212 | * mode is enabled. |
| 1213 | */ |
| 1214 | if (mdss_dsi_is_hw_config_split(ctrl->shared_data)) { |
| 1215 | other_ctrl = mdss_dsi_get_other_ctrl(ctrl); |
| 1216 | if (mdss_dsi_is_right_ctrl(ctrl) && other_ctrl) { |
| 1217 | mdss_dsi_phy_shutdown(other_ctrl); |
| 1218 | mdss_dsi_phy_shutdown(ctrl); |
| 1219 | } |
| 1220 | } else { |
| 1221 | mdss_dsi_phy_shutdown(ctrl); |
| 1222 | } |
| 1223 | } |
| 1224 | } |
| 1225 | |
| 1226 | void mdss_dsi_phy_disable(struct mdss_dsi_ctrl_pdata *ctrl) |
| 1227 | { |
| 1228 | if (ctrl == NULL) { |
| 1229 | pr_err("%s: Invalid input data\n", __func__); |
| 1230 | return; |
| 1231 | } |
| 1232 | |
| 1233 | mdss_dsi_phy_ctrl(ctrl, false); |
| 1234 | mdss_dsi_phy_regulator_ctrl(ctrl, false); |
| 1235 | /* |
| 1236 | * Wait for the registers writes to complete in order to |
| 1237 | * ensure that the phy is completely disabled |
| 1238 | */ |
| 1239 | wmb(); |
| 1240 | } |
| 1241 | |
| 1242 | static void mdss_dsi_phy_init_sub(struct mdss_dsi_ctrl_pdata *ctrl) |
| 1243 | { |
| 1244 | mdss_dsi_phy_regulator_ctrl(ctrl, true); |
| 1245 | mdss_dsi_phy_ctrl(ctrl, true); |
| 1246 | } |
| 1247 | |
| 1248 | void mdss_dsi_phy_init(struct mdss_dsi_ctrl_pdata *ctrl) |
| 1249 | { |
| 1250 | struct mdss_dsi_ctrl_pdata *sctrl = NULL; |
| 1251 | |
| 1252 | /* |
| 1253 | * When operating in split display mode, make sure that both the PHY |
| 1254 | * blocks are initialized together prior to the PLL being enabled. This |
| 1255 | * is achieved by calling the phy_init function for the clk_slave from |
| 1256 | * the clock_master. |
| 1257 | */ |
| 1258 | if (mdss_dsi_is_ctrl_clk_slave(ctrl)) |
| 1259 | return; |
| 1260 | |
| 1261 | mdss_dsi_phy_init_sub(ctrl); |
| 1262 | |
| 1263 | if (mdss_dsi_is_ctrl_clk_master(ctrl)) { |
| 1264 | sctrl = mdss_dsi_get_ctrl_clk_slave(); |
| 1265 | if (sctrl) |
| 1266 | mdss_dsi_phy_init_sub(sctrl); |
| 1267 | else |
| 1268 | pr_warn("%s: unable to get slave ctrl\n", __func__); |
| 1269 | } |
| 1270 | } |
| 1271 | |
| 1272 | void mdss_dsi_core_clk_deinit(struct device *dev, struct dsi_shared_data *sdata) |
| 1273 | { |
| 1274 | if (sdata->mmss_misc_ahb_clk) |
| 1275 | devm_clk_put(dev, sdata->mmss_misc_ahb_clk); |
| 1276 | if (sdata->ext_pixel1_clk) |
| 1277 | devm_clk_put(dev, sdata->ext_pixel1_clk); |
| 1278 | if (sdata->ext_byte1_clk) |
| 1279 | devm_clk_put(dev, sdata->ext_byte1_clk); |
| 1280 | if (sdata->ext_pixel0_clk) |
| 1281 | devm_clk_put(dev, sdata->ext_pixel0_clk); |
| 1282 | if (sdata->ext_byte0_clk) |
| 1283 | devm_clk_put(dev, sdata->ext_byte0_clk); |
| 1284 | if (sdata->axi_clk) |
| 1285 | devm_clk_put(dev, sdata->axi_clk); |
| 1286 | if (sdata->ahb_clk) |
| 1287 | devm_clk_put(dev, sdata->ahb_clk); |
| 1288 | if (sdata->mdp_core_clk) |
| 1289 | devm_clk_put(dev, sdata->mdp_core_clk); |
| 1290 | } |
| 1291 | |
| 1292 | int mdss_dsi_clk_refresh(struct mdss_panel_data *pdata, bool update_phy) |
| 1293 | { |
| 1294 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1295 | struct mdss_panel_info *pinfo = NULL; |
| 1296 | int rc = 0; |
| 1297 | |
| 1298 | if (!pdata) { |
| 1299 | pr_err("%s: invalid panel data\n", __func__); |
| 1300 | return -EINVAL; |
| 1301 | } |
| 1302 | |
| 1303 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1304 | panel_data); |
| 1305 | pinfo = &pdata->panel_info; |
| 1306 | |
| 1307 | if (!ctrl_pdata || !pinfo) { |
| 1308 | pr_err("%s: invalid ctrl data\n", __func__); |
| 1309 | return -EINVAL; |
| 1310 | } |
| 1311 | |
| 1312 | if (update_phy) { |
| 1313 | pinfo->mipi.frame_rate = mdss_panel_calc_frame_rate(pinfo); |
| 1314 | pr_debug("%s: new frame rate %d\n", |
| 1315 | __func__, pinfo->mipi.frame_rate); |
| 1316 | } |
| 1317 | |
| 1318 | rc = mdss_dsi_clk_div_config(&pdata->panel_info, |
| 1319 | pdata->panel_info.mipi.frame_rate); |
| 1320 | if (rc) { |
| 1321 | pr_err("%s: unable to initialize the clk dividers\n", |
| 1322 | __func__); |
| 1323 | return rc; |
| 1324 | } |
| 1325 | ctrl_pdata->refresh_clk_rate = false; |
| 1326 | ctrl_pdata->pclk_rate = pdata->panel_info.mipi.dsi_pclk_rate; |
| 1327 | ctrl_pdata->byte_clk_rate = pdata->panel_info.clk_rate / 8; |
| 1328 | pr_debug("%s ctrl_pdata->byte_clk_rate=%d ctrl_pdata->pclk_rate=%d\n", |
| 1329 | __func__, ctrl_pdata->byte_clk_rate, ctrl_pdata->pclk_rate); |
| 1330 | |
| 1331 | rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle, |
| 1332 | MDSS_DSI_LINK_BYTE_CLK, ctrl_pdata->byte_clk_rate, |
| 1333 | MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON); |
| 1334 | if (rc) { |
| 1335 | pr_err("%s: dsi_byte_clk - clk_set_rate failed\n", |
| 1336 | __func__); |
| 1337 | return rc; |
| 1338 | } |
| 1339 | |
| 1340 | rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle, |
| 1341 | MDSS_DSI_LINK_PIX_CLK, ctrl_pdata->pclk_rate, |
| 1342 | MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON); |
| 1343 | if (rc) { |
| 1344 | pr_err("%s: dsi_pixel_clk - clk_set_rate failed\n", |
| 1345 | __func__); |
| 1346 | return rc; |
| 1347 | } |
| 1348 | |
| 1349 | if (update_phy) { |
| 1350 | /* phy panel timing calaculation */ |
| 1351 | rc = mdss_dsi_phy_calc_timing_param(pinfo, |
| 1352 | ctrl_pdata->shared_data->phy_rev, |
| 1353 | pinfo->mipi.frame_rate); |
| 1354 | if (rc) { |
| 1355 | pr_err("Error in calculating phy timings\n"); |
| 1356 | return rc; |
| 1357 | } |
| 1358 | ctrl_pdata->update_phy_timing = false; |
| 1359 | } |
| 1360 | |
| 1361 | return rc; |
| 1362 | } |
| 1363 | |
| 1364 | int mdss_dsi_core_clk_init(struct platform_device *pdev, |
| 1365 | struct dsi_shared_data *sdata) |
| 1366 | { |
| 1367 | struct device *dev = NULL; |
| 1368 | int rc = 0; |
| 1369 | |
| 1370 | if (!pdev) { |
| 1371 | pr_err("%s: Invalid pdev\n", __func__); |
| 1372 | goto error; |
| 1373 | } |
| 1374 | |
| 1375 | dev = &pdev->dev; |
| 1376 | |
| 1377 | /* Mandatory Clocks */ |
| 1378 | sdata->mdp_core_clk = devm_clk_get(dev, "mdp_core_clk"); |
| 1379 | if (IS_ERR(sdata->mdp_core_clk)) { |
| 1380 | rc = PTR_ERR(sdata->mdp_core_clk); |
| 1381 | pr_err("%s: Unable to get mdp core clk. rc=%d\n", |
| 1382 | __func__, rc); |
| 1383 | goto error; |
| 1384 | } |
| 1385 | |
| 1386 | sdata->ahb_clk = devm_clk_get(dev, "iface_clk"); |
| 1387 | if (IS_ERR(sdata->ahb_clk)) { |
| 1388 | rc = PTR_ERR(sdata->ahb_clk); |
| 1389 | pr_err("%s: Unable to get mdss ahb clk. rc=%d\n", |
| 1390 | __func__, rc); |
| 1391 | goto error; |
| 1392 | } |
| 1393 | |
| 1394 | sdata->axi_clk = devm_clk_get(dev, "bus_clk"); |
| 1395 | if (IS_ERR(sdata->axi_clk)) { |
| 1396 | rc = PTR_ERR(sdata->axi_clk); |
| 1397 | pr_err("%s: Unable to get axi bus clk. rc=%d\n", |
| 1398 | __func__, rc); |
| 1399 | goto error; |
| 1400 | } |
| 1401 | |
| 1402 | /* Optional Clocks */ |
| 1403 | sdata->ext_byte0_clk = devm_clk_get(dev, "ext_byte0_clk"); |
| 1404 | if (IS_ERR(sdata->ext_byte0_clk)) { |
| 1405 | pr_debug("%s: unable to get byte0 clk rcg. rc=%d\n", |
| 1406 | __func__, rc); |
| 1407 | sdata->ext_byte0_clk = NULL; |
| 1408 | } |
| 1409 | |
| 1410 | sdata->ext_pixel0_clk = devm_clk_get(dev, "ext_pixel0_clk"); |
| 1411 | if (IS_ERR(sdata->ext_pixel0_clk)) { |
| 1412 | pr_debug("%s: unable to get pixel0 clk rcg. rc=%d\n", |
| 1413 | __func__, rc); |
| 1414 | sdata->ext_pixel0_clk = NULL; |
| 1415 | } |
| 1416 | |
| 1417 | sdata->ext_byte1_clk = devm_clk_get(dev, "ext_byte1_clk"); |
| 1418 | if (IS_ERR(sdata->ext_byte1_clk)) { |
| 1419 | pr_debug("%s: unable to get byte1 clk rcg. rc=%d\n", |
| 1420 | __func__, rc); |
| 1421 | sdata->ext_byte1_clk = NULL; |
| 1422 | } |
| 1423 | |
| 1424 | sdata->ext_pixel1_clk = devm_clk_get(dev, "ext_pixel1_clk"); |
| 1425 | if (IS_ERR(sdata->ext_pixel1_clk)) { |
| 1426 | pr_debug("%s: unable to get pixel1 clk rcg. rc=%d\n", |
| 1427 | __func__, rc); |
| 1428 | sdata->ext_pixel1_clk = NULL; |
| 1429 | } |
| 1430 | |
| 1431 | sdata->mmss_misc_ahb_clk = devm_clk_get(dev, "core_mmss_clk"); |
| 1432 | if (IS_ERR(sdata->mmss_misc_ahb_clk)) { |
| 1433 | sdata->mmss_misc_ahb_clk = NULL; |
| 1434 | pr_debug("%s: Unable to get mmss misc ahb clk\n", |
| 1435 | __func__); |
| 1436 | } |
| 1437 | |
| 1438 | error: |
| 1439 | if (rc) |
| 1440 | mdss_dsi_core_clk_deinit(dev, sdata); |
| 1441 | return rc; |
| 1442 | } |
| 1443 | |
| 1444 | void mdss_dsi_link_clk_deinit(struct device *dev, |
| 1445 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 1446 | { |
| 1447 | if (ctrl->vco_dummy_clk) |
| 1448 | devm_clk_put(dev, ctrl->vco_dummy_clk); |
| 1449 | if (ctrl->pixel_clk_rcg) |
| 1450 | devm_clk_put(dev, ctrl->pixel_clk_rcg); |
| 1451 | if (ctrl->byte_clk_rcg) |
| 1452 | devm_clk_put(dev, ctrl->byte_clk_rcg); |
| 1453 | if (ctrl->byte_clk) |
| 1454 | devm_clk_put(dev, ctrl->byte_clk); |
| 1455 | if (ctrl->esc_clk) |
| 1456 | devm_clk_put(dev, ctrl->esc_clk); |
| 1457 | if (ctrl->pixel_clk) |
| 1458 | devm_clk_put(dev, ctrl->pixel_clk); |
| 1459 | } |
| 1460 | |
| 1461 | int mdss_dsi_link_clk_init(struct platform_device *pdev, |
| 1462 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 1463 | { |
| 1464 | struct device *dev = NULL; |
| 1465 | int rc = 0; |
| 1466 | |
| 1467 | if (!pdev) { |
| 1468 | pr_err("%s: Invalid pdev\n", __func__); |
| 1469 | goto error; |
| 1470 | } |
| 1471 | |
| 1472 | dev = &pdev->dev; |
| 1473 | |
| 1474 | /* Mandatory Clocks */ |
| 1475 | ctrl->byte_clk = devm_clk_get(dev, "byte_clk"); |
| 1476 | if (IS_ERR(ctrl->byte_clk)) { |
| 1477 | rc = PTR_ERR(ctrl->byte_clk); |
| 1478 | pr_err("%s: can't find dsi_byte_clk. rc=%d\n", |
| 1479 | __func__, rc); |
| 1480 | ctrl->byte_clk = NULL; |
| 1481 | goto error; |
| 1482 | } |
| 1483 | |
| 1484 | ctrl->pixel_clk = devm_clk_get(dev, "pixel_clk"); |
| 1485 | if (IS_ERR(ctrl->pixel_clk)) { |
| 1486 | rc = PTR_ERR(ctrl->pixel_clk); |
| 1487 | pr_err("%s: can't find dsi_pixel_clk. rc=%d\n", |
| 1488 | __func__, rc); |
| 1489 | ctrl->pixel_clk = NULL; |
| 1490 | goto error; |
| 1491 | } |
| 1492 | |
| 1493 | ctrl->esc_clk = devm_clk_get(dev, "core_clk"); |
| 1494 | if (IS_ERR(ctrl->esc_clk)) { |
| 1495 | rc = PTR_ERR(ctrl->esc_clk); |
| 1496 | pr_err("%s: can't find dsi_esc_clk. rc=%d\n", |
| 1497 | __func__, rc); |
| 1498 | ctrl->esc_clk = NULL; |
| 1499 | goto error; |
| 1500 | } |
| 1501 | |
| 1502 | /* Optional Clocks */ |
| 1503 | ctrl->byte_clk_rcg = devm_clk_get(dev, "byte_clk_rcg"); |
| 1504 | if (IS_ERR(ctrl->byte_clk_rcg)) { |
| 1505 | pr_debug("%s: can't find byte clk rcg. rc=%d\n", __func__, rc); |
| 1506 | ctrl->byte_clk_rcg = NULL; |
| 1507 | } |
| 1508 | |
| 1509 | ctrl->pixel_clk_rcg = devm_clk_get(dev, "pixel_clk_rcg"); |
| 1510 | if (IS_ERR(ctrl->pixel_clk_rcg)) { |
| 1511 | pr_debug("%s: can't find pixel clk rcg. rc=%d\n", __func__, rc); |
| 1512 | ctrl->pixel_clk_rcg = NULL; |
| 1513 | } |
| 1514 | |
| 1515 | ctrl->vco_dummy_clk = devm_clk_get(dev, "pll_vco_dummy_clk"); |
| 1516 | if (IS_ERR(ctrl->vco_dummy_clk)) { |
| 1517 | pr_debug("%s: can't find vco dummy clk. rc=%d\n", __func__, rc); |
| 1518 | ctrl->vco_dummy_clk = NULL; |
| 1519 | } |
| 1520 | |
| 1521 | error: |
| 1522 | if (rc) |
| 1523 | mdss_dsi_link_clk_deinit(dev, ctrl); |
| 1524 | return rc; |
| 1525 | } |
| 1526 | |
| 1527 | void mdss_dsi_shadow_clk_deinit(struct device *dev, |
| 1528 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 1529 | { |
| 1530 | if (ctrl->mux_byte_clk) |
| 1531 | devm_clk_put(dev, ctrl->mux_byte_clk); |
| 1532 | if (ctrl->mux_pixel_clk) |
| 1533 | devm_clk_put(dev, ctrl->mux_pixel_clk); |
| 1534 | if (ctrl->pll_byte_clk) |
| 1535 | devm_clk_put(dev, ctrl->pll_byte_clk); |
| 1536 | if (ctrl->pll_pixel_clk) |
| 1537 | devm_clk_put(dev, ctrl->pll_pixel_clk); |
| 1538 | if (ctrl->shadow_byte_clk) |
| 1539 | devm_clk_put(dev, ctrl->shadow_byte_clk); |
| 1540 | if (ctrl->shadow_pixel_clk) |
| 1541 | devm_clk_put(dev, ctrl->shadow_pixel_clk); |
| 1542 | } |
| 1543 | |
| 1544 | int mdss_dsi_shadow_clk_init(struct platform_device *pdev, |
| 1545 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 1546 | { |
| 1547 | struct device *dev = NULL; |
| 1548 | int rc = 0; |
| 1549 | |
| 1550 | if (!pdev) { |
| 1551 | pr_err("%s: Invalid pdev\n", __func__); |
| 1552 | return -EINVAL; |
| 1553 | } |
| 1554 | |
| 1555 | dev = &pdev->dev; |
| 1556 | ctrl->mux_byte_clk = devm_clk_get(dev, "pll_byte_clk_mux"); |
| 1557 | if (IS_ERR(ctrl->mux_byte_clk)) { |
| 1558 | rc = PTR_ERR(ctrl->mux_byte_clk); |
| 1559 | pr_err("%s: can't find mux_byte_clk. rc=%d\n", |
| 1560 | __func__, rc); |
| 1561 | ctrl->mux_byte_clk = NULL; |
| 1562 | goto error; |
| 1563 | } |
| 1564 | |
| 1565 | ctrl->mux_pixel_clk = devm_clk_get(dev, "pll_pixel_clk_mux"); |
| 1566 | if (IS_ERR(ctrl->mux_pixel_clk)) { |
| 1567 | rc = PTR_ERR(ctrl->mux_pixel_clk); |
| 1568 | pr_err("%s: can't find mdss_mux_pixel_clk. rc=%d\n", |
| 1569 | __func__, rc); |
| 1570 | ctrl->mux_pixel_clk = NULL; |
| 1571 | goto error; |
| 1572 | } |
| 1573 | |
| 1574 | ctrl->pll_byte_clk = devm_clk_get(dev, "pll_byte_clk_src"); |
| 1575 | if (IS_ERR(ctrl->pll_byte_clk)) { |
| 1576 | rc = PTR_ERR(ctrl->pll_byte_clk); |
| 1577 | pr_err("%s: can't find pll_byte_clk. rc=%d\n", |
| 1578 | __func__, rc); |
| 1579 | ctrl->pll_byte_clk = NULL; |
| 1580 | goto error; |
| 1581 | } |
| 1582 | |
| 1583 | ctrl->pll_pixel_clk = devm_clk_get(dev, "pll_pixel_clk_src"); |
| 1584 | if (IS_ERR(ctrl->pll_pixel_clk)) { |
| 1585 | rc = PTR_ERR(ctrl->pll_pixel_clk); |
| 1586 | pr_err("%s: can't find pll_pixel_clk. rc=%d\n", |
| 1587 | __func__, rc); |
| 1588 | ctrl->pll_pixel_clk = NULL; |
| 1589 | goto error; |
| 1590 | } |
| 1591 | |
| 1592 | ctrl->shadow_byte_clk = devm_clk_get(dev, "pll_shadow_byte_clk_src"); |
| 1593 | if (IS_ERR(ctrl->shadow_byte_clk)) { |
| 1594 | rc = PTR_ERR(ctrl->shadow_byte_clk); |
| 1595 | pr_err("%s: can't find shadow_byte_clk. rc=%d\n", |
| 1596 | __func__, rc); |
| 1597 | ctrl->shadow_byte_clk = NULL; |
| 1598 | goto error; |
| 1599 | } |
| 1600 | |
| 1601 | ctrl->shadow_pixel_clk = devm_clk_get(dev, "pll_shadow_pixel_clk_src"); |
| 1602 | if (IS_ERR(ctrl->shadow_pixel_clk)) { |
| 1603 | rc = PTR_ERR(ctrl->shadow_pixel_clk); |
| 1604 | pr_err("%s: can't find shadow_pixel_clk. rc=%d\n", |
| 1605 | __func__, rc); |
| 1606 | ctrl->shadow_pixel_clk = NULL; |
| 1607 | goto error; |
| 1608 | } |
| 1609 | |
| 1610 | error: |
| 1611 | if (rc) |
| 1612 | mdss_dsi_shadow_clk_deinit(dev, ctrl); |
| 1613 | return rc; |
| 1614 | } |
| 1615 | |
| 1616 | bool is_diff_frame_rate(struct mdss_panel_info *panel_info, |
| 1617 | u32 frame_rate) |
| 1618 | { |
| 1619 | if (panel_info->dynamic_fps && panel_info->current_fps) |
| 1620 | return (frame_rate != panel_info->current_fps); |
| 1621 | else |
| 1622 | return (frame_rate != panel_info->mipi.frame_rate); |
| 1623 | } |
| 1624 | |
| 1625 | int mdss_dsi_clk_div_config(struct mdss_panel_info *panel_info, |
| 1626 | int frame_rate) |
| 1627 | { |
| 1628 | struct mdss_panel_data *pdata = container_of(panel_info, |
| 1629 | struct mdss_panel_data, panel_info); |
| 1630 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = container_of(pdata, |
| 1631 | struct mdss_dsi_ctrl_pdata, panel_data); |
| 1632 | u64 h_period, v_period, clk_rate; |
| 1633 | u32 dsi_pclk_rate; |
| 1634 | u8 lanes = 0, bpp; |
| 1635 | |
| 1636 | if (panel_info->mipi.data_lane3) |
| 1637 | lanes += 1; |
| 1638 | if (panel_info->mipi.data_lane2) |
| 1639 | lanes += 1; |
| 1640 | if (panel_info->mipi.data_lane1) |
| 1641 | lanes += 1; |
| 1642 | if (panel_info->mipi.data_lane0) |
| 1643 | lanes += 1; |
| 1644 | |
| 1645 | switch (panel_info->mipi.dst_format) { |
| 1646 | case DSI_CMD_DST_FORMAT_RGB888: |
| 1647 | case DSI_VIDEO_DST_FORMAT_RGB888: |
| 1648 | case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE: |
| 1649 | bpp = 3; |
| 1650 | break; |
| 1651 | case DSI_CMD_DST_FORMAT_RGB565: |
| 1652 | case DSI_VIDEO_DST_FORMAT_RGB565: |
| 1653 | bpp = 2; |
| 1654 | break; |
| 1655 | default: |
| 1656 | bpp = 3; /* Default format set to RGB888 */ |
| 1657 | break; |
| 1658 | } |
| 1659 | |
| 1660 | h_period = mdss_panel_get_htotal(panel_info, true); |
| 1661 | v_period = mdss_panel_get_vtotal(panel_info); |
| 1662 | |
| 1663 | if (ctrl_pdata->refresh_clk_rate || is_diff_frame_rate(panel_info, |
| 1664 | frame_rate) || (!panel_info->clk_rate)) { |
| 1665 | if (lanes > 0) { |
| 1666 | panel_info->clk_rate = h_period * v_period * frame_rate |
| 1667 | * bpp * 8; |
| 1668 | do_div(panel_info->clk_rate, lanes); |
| 1669 | } else { |
| 1670 | pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); |
| 1671 | panel_info->clk_rate = |
| 1672 | h_period * v_period * frame_rate * bpp * 8; |
| 1673 | } |
| 1674 | } |
| 1675 | |
| 1676 | if (panel_info->clk_rate == 0) |
| 1677 | panel_info->clk_rate = 454000000; |
| 1678 | |
| 1679 | clk_rate = panel_info->clk_rate; |
| 1680 | do_div(clk_rate, 8 * bpp); |
| 1681 | dsi_pclk_rate = (u32) clk_rate * lanes; |
| 1682 | |
| 1683 | if ((dsi_pclk_rate < 3300000) || (dsi_pclk_rate > 250000000)) |
| 1684 | dsi_pclk_rate = 35000000; |
| 1685 | panel_info->mipi.dsi_pclk_rate = dsi_pclk_rate; |
| 1686 | |
| 1687 | return 0; |
| 1688 | } |
| 1689 | |
| 1690 | static bool mdss_dsi_is_ulps_req_valid(struct mdss_dsi_ctrl_pdata *ctrl, |
| 1691 | int enable) |
| 1692 | { |
| 1693 | struct mdss_dsi_ctrl_pdata *octrl = NULL; |
| 1694 | struct mdss_panel_data *pdata = &ctrl->panel_data; |
| 1695 | struct mdss_panel_info *pinfo = &pdata->panel_info; |
| 1696 | |
| 1697 | pr_debug("%s: checking ulps req validity for ctrl%d\n", |
| 1698 | __func__, ctrl->ndx); |
| 1699 | |
| 1700 | if (!mdss_dsi_ulps_feature_enabled(pdata) && |
| 1701 | !pinfo->ulps_suspend_enabled) { |
| 1702 | pr_debug("%s: ULPS feature is not enabled\n", __func__); |
| 1703 | return false; |
| 1704 | } |
| 1705 | |
| 1706 | /* |
| 1707 | * No need to enter ULPS when transitioning from splash screen to |
| 1708 | * boot animation since it is expected that the clocks would be turned |
| 1709 | * right back on. |
| 1710 | */ |
| 1711 | if (enable && pinfo->cont_splash_enabled) { |
| 1712 | pr_debug("%s: skip ULPS config with splash screen enabled\n", |
| 1713 | __func__); |
| 1714 | return false; |
| 1715 | } |
| 1716 | |
| 1717 | /* |
| 1718 | * No need to enable ULPS if panel is not yet initialized. |
| 1719 | * However, this should be allowed in following usecases: |
| 1720 | * 1. If ULPS during suspend feature is enabled, where we |
| 1721 | * configure the lanes in ULPS after turning off the panel. |
| 1722 | * 2. When coming out of idle PC with clamps enabled, where we |
| 1723 | * transition the controller HW state back to ULPS prior to |
| 1724 | * disabling ULPS. |
| 1725 | */ |
| 1726 | if (enable && !ctrl->mmss_clamp && |
| 1727 | !(ctrl->ctrl_state & CTRL_STATE_PANEL_INIT) && |
| 1728 | !pdata->panel_info.ulps_suspend_enabled) { |
| 1729 | pr_debug("%s: panel not yet initialized\n", __func__); |
| 1730 | return false; |
| 1731 | } |
| 1732 | |
| 1733 | /* |
| 1734 | * For split-DSI usecase, wait till both controllers are initialized. |
| 1735 | * The same exceptions as above are applicable here too. |
| 1736 | */ |
| 1737 | if (mdss_dsi_is_hw_config_split(ctrl->shared_data)) { |
| 1738 | octrl = mdss_dsi_get_other_ctrl(ctrl); |
| 1739 | if (enable && !ctrl->mmss_clamp && octrl && |
| 1740 | !(octrl->ctrl_state & CTRL_STATE_PANEL_INIT) && |
| 1741 | !pdata->panel_info.ulps_suspend_enabled) { |
| 1742 | pr_debug("%s: split-DSI, other ctrl not ready yet\n", |
| 1743 | __func__); |
| 1744 | return false; |
| 1745 | } |
| 1746 | } |
| 1747 | |
| 1748 | return true; |
| 1749 | } |
| 1750 | |
| 1751 | /** |
| 1752 | * mdss_dsi_ulps_config() - Program DSI lanes to enter/exit ULPS mode |
| 1753 | * @ctrl: pointer to DSI controller structure |
| 1754 | * @enable: 1 to enter ULPS, 0 to exit ULPS |
| 1755 | * |
| 1756 | * This function executes the necessary programming sequence to enter/exit |
| 1757 | * DSI Ultra-Low Power State (ULPS). This function assumes that the link and |
| 1758 | * core clocks are already on. |
| 1759 | */ |
| 1760 | static int mdss_dsi_ulps_config(struct mdss_dsi_ctrl_pdata *ctrl, |
| 1761 | int enable) |
| 1762 | { |
| 1763 | int ret = 0; |
| 1764 | struct mdss_panel_data *pdata = NULL; |
| 1765 | struct mdss_panel_info *pinfo; |
| 1766 | struct mipi_panel_info *mipi; |
| 1767 | u32 lane_status = 0; |
| 1768 | u32 active_lanes = 0; |
| 1769 | |
| 1770 | if (!ctrl) { |
| 1771 | pr_err("%s: invalid input\n", __func__); |
| 1772 | return -EINVAL; |
| 1773 | } |
| 1774 | |
| 1775 | pdata = &ctrl->panel_data; |
| 1776 | if (!pdata) { |
| 1777 | pr_err("%s: Invalid panel data\n", __func__); |
| 1778 | return -EINVAL; |
| 1779 | } |
| 1780 | pinfo = &pdata->panel_info; |
| 1781 | mipi = &pinfo->mipi; |
| 1782 | |
| 1783 | if (!mdss_dsi_is_ulps_req_valid(ctrl, enable)) { |
| 1784 | pr_debug("%s: skiping ULPS config for ctrl%d, enable=%d\n", |
| 1785 | __func__, ctrl->ndx, enable); |
| 1786 | return 0; |
| 1787 | } |
| 1788 | |
| 1789 | /* clock lane will always be programmed for ulps */ |
| 1790 | active_lanes = BIT(4); |
| 1791 | /* |
| 1792 | * make a note of all active data lanes for which ulps entry/exit |
| 1793 | * is needed |
| 1794 | */ |
| 1795 | if (mipi->data_lane0) |
| 1796 | active_lanes |= BIT(0); |
| 1797 | if (mipi->data_lane1) |
| 1798 | active_lanes |= BIT(1); |
| 1799 | if (mipi->data_lane2) |
| 1800 | active_lanes |= BIT(2); |
| 1801 | if (mipi->data_lane3) |
| 1802 | active_lanes |= BIT(3); |
| 1803 | |
| 1804 | pr_debug("%s: configuring ulps (%s) for ctrl%d, active lanes=0x%08x,clamps=%s\n", |
| 1805 | __func__, (enable ? "on" : "off"), ctrl->ndx, |
| 1806 | active_lanes, ctrl->mmss_clamp ? "enabled" : "disabled"); |
| 1807 | |
| 1808 | if (enable && !ctrl->ulps) { |
| 1809 | /* |
| 1810 | * Ensure that the lanes are idle prior to placing a ULPS entry |
| 1811 | * request. This is needed to ensure that there is no overlap |
| 1812 | * between any HS or LP commands being sent out on the lane and |
| 1813 | * a potential ULPS entry request. |
| 1814 | * |
| 1815 | * This check needs to be avoided when we are resuming from idle |
| 1816 | * power collapse and just restoring the controller state to |
| 1817 | * ULPS with the clamps still in place. |
| 1818 | */ |
| 1819 | if (!ctrl->mmss_clamp) { |
| 1820 | ret = mdss_dsi_wait_for_lane_idle(ctrl); |
| 1821 | if (ret) { |
| 1822 | pr_warn("%s: lanes not idle, skip ulps\n", |
| 1823 | __func__); |
| 1824 | ret = 0; |
| 1825 | goto error; |
| 1826 | } |
| 1827 | } |
| 1828 | |
| 1829 | /* |
| 1830 | * ULPS Entry Request. |
| 1831 | * Wait for a short duration to ensure that the lanes |
| 1832 | * enter ULP state. |
| 1833 | */ |
| 1834 | MIPI_OUTP(ctrl->ctrl_base + 0x0AC, active_lanes); |
| 1835 | usleep_range(100, 110); |
| 1836 | |
| 1837 | /* Check to make sure that all active data lanes are in ULPS */ |
| 1838 | lane_status = MIPI_INP(ctrl->ctrl_base + 0xA8); |
| 1839 | if (lane_status & (active_lanes << 8)) { |
| 1840 | pr_err("%s: ULPS entry req failed for ctrl%d. Lane status=0x%08x\n", |
| 1841 | __func__, ctrl->ndx, lane_status); |
| 1842 | ret = -EINVAL; |
| 1843 | goto error; |
| 1844 | } |
| 1845 | |
| 1846 | ctrl->ulps = true; |
| 1847 | } else if (!enable && ctrl->ulps) { |
| 1848 | /* |
| 1849 | * Clear out any phy errors prior to exiting ULPS |
| 1850 | * This fixes certain instances where phy does not exit |
| 1851 | * ULPS cleanly. Also, do not print error during such cases. |
| 1852 | */ |
| 1853 | mdss_dsi_dln0_phy_err(ctrl, false); |
| 1854 | |
| 1855 | /* |
| 1856 | * ULPS Exit Request |
| 1857 | * Hardware requirement is to wait for at least 1ms |
| 1858 | */ |
| 1859 | MIPI_OUTP(ctrl->ctrl_base + 0x0AC, active_lanes << 8); |
| 1860 | usleep_range(1000, 1100); |
| 1861 | |
| 1862 | /* |
| 1863 | * Sometimes when exiting ULPS, it is possible that some DSI |
| 1864 | * lanes are not in the stop state which could lead to DSI |
| 1865 | * commands not going through. To avoid this, force the lanes |
| 1866 | * to be in stop state. |
| 1867 | */ |
| 1868 | MIPI_OUTP(ctrl->ctrl_base + 0x0AC, active_lanes << 16); |
| 1869 | wmb(); /* ensure lanes are put to stop state */ |
| 1870 | |
| 1871 | MIPI_OUTP(ctrl->ctrl_base + 0x0AC, 0x0); |
| 1872 | wmb(); /* ensure lanes are in proper state */ |
| 1873 | |
| 1874 | /* |
| 1875 | * Wait for a short duration before enabling |
| 1876 | * data transmission |
| 1877 | */ |
| 1878 | usleep_range(100, 110); |
| 1879 | |
| 1880 | lane_status = MIPI_INP(ctrl->ctrl_base + 0xA8); |
| 1881 | ctrl->ulps = false; |
| 1882 | } else { |
| 1883 | pr_debug("%s: No change requested: %s -> %s\n", __func__, |
| 1884 | ctrl->ulps ? "enabled" : "disabled", |
| 1885 | enable ? "enabled" : "disabled"); |
| 1886 | } |
| 1887 | |
| 1888 | pr_debug("%s: DSI lane status = 0x%08x. Ulps %s\n", __func__, |
| 1889 | lane_status, enable ? "enabled" : "disabled"); |
| 1890 | |
| 1891 | error: |
| 1892 | return ret; |
| 1893 | } |
| 1894 | |
| 1895 | /** |
| 1896 | * mdss_dsi_clamp_ctrl() - Program DSI clamps for supporting power collapse |
| 1897 | * @ctrl: pointer to DSI controller structure |
| 1898 | * @enable: 1 to enable clamps, 0 to disable clamps |
| 1899 | * |
| 1900 | * For idle-screen usecases with command mode panels, MDSS can be power |
| 1901 | * collapsed. However, DSI phy needs to remain on. To avoid any mismatch |
| 1902 | * between the DSI controller state, DSI phy needs to be clamped before |
| 1903 | * power collapsing. This function executes the required programming |
| 1904 | * sequence to configure these DSI clamps. This function should only be called |
| 1905 | * when the DSI link clocks are disabled. |
| 1906 | */ |
| 1907 | static int mdss_dsi_clamp_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, int enable) |
| 1908 | { |
| 1909 | struct mipi_panel_info *mipi = NULL; |
| 1910 | u32 clamp_reg, regval = 0; |
| 1911 | u32 clamp_reg_off, phyrst_reg_off; |
| 1912 | |
| 1913 | if (!ctrl) { |
| 1914 | pr_err("%s: invalid input\n", __func__); |
| 1915 | return -EINVAL; |
| 1916 | } |
| 1917 | |
| 1918 | if (!ctrl->mmss_misc_io.base) { |
| 1919 | pr_err("%s: mmss_misc_io not mapped\n", __func__); |
| 1920 | return -EINVAL; |
| 1921 | } |
| 1922 | |
| 1923 | clamp_reg_off = ctrl->shared_data->ulps_clamp_ctrl_off; |
| 1924 | phyrst_reg_off = ctrl->shared_data->ulps_phyrst_ctrl_off; |
| 1925 | mipi = &ctrl->panel_data.panel_info.mipi; |
| 1926 | |
| 1927 | /* clock lane will always be clamped */ |
| 1928 | clamp_reg = BIT(9); |
| 1929 | if (ctrl->ulps) |
| 1930 | clamp_reg |= BIT(8); |
| 1931 | /* make a note of all active data lanes which need to be clamped */ |
| 1932 | if (mipi->data_lane0) { |
| 1933 | clamp_reg |= BIT(7); |
| 1934 | if (ctrl->ulps) |
| 1935 | clamp_reg |= BIT(6); |
| 1936 | } |
| 1937 | if (mipi->data_lane1) { |
| 1938 | clamp_reg |= BIT(5); |
| 1939 | if (ctrl->ulps) |
| 1940 | clamp_reg |= BIT(4); |
| 1941 | } |
| 1942 | if (mipi->data_lane2) { |
| 1943 | clamp_reg |= BIT(3); |
| 1944 | if (ctrl->ulps) |
| 1945 | clamp_reg |= BIT(2); |
| 1946 | } |
| 1947 | if (mipi->data_lane3) { |
| 1948 | clamp_reg |= BIT(1); |
| 1949 | if (ctrl->ulps) |
| 1950 | clamp_reg |= BIT(0); |
| 1951 | } |
| 1952 | pr_debug("%s: called for ctrl%d, enable=%d, clamp_reg=0x%08x\n", |
| 1953 | __func__, ctrl->ndx, enable, clamp_reg); |
| 1954 | if (enable && !ctrl->mmss_clamp) { |
| 1955 | regval = MIPI_INP(ctrl->mmss_misc_io.base + clamp_reg_off); |
| 1956 | /* Enable MMSS DSI Clamps */ |
| 1957 | if (ctrl->ndx == DSI_CTRL_0) { |
| 1958 | MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, |
| 1959 | regval | clamp_reg); |
| 1960 | MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, |
| 1961 | regval | (clamp_reg | BIT(15))); |
| 1962 | } else if (ctrl->ndx == DSI_CTRL_1) { |
| 1963 | MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, |
| 1964 | regval | (clamp_reg << 16)); |
| 1965 | MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, |
| 1966 | regval | ((clamp_reg << 16) | BIT(31))); |
| 1967 | } |
| 1968 | /* update clamp ctrl before setting phy reset disable */ |
| 1969 | wmb(); |
| 1970 | |
| 1971 | /* |
| 1972 | * This register write ensures that DSI PHY will not be |
| 1973 | * reset when mdss ahb clock reset is asserted while coming |
| 1974 | * out of power collapse |
| 1975 | */ |
| 1976 | if (IS_MDSS_MAJOR_MINOR_SAME(ctrl->shared_data->hw_rev, |
| 1977 | MDSS_DSI_HW_REV_104) && |
| 1978 | (MDSS_GET_STEP(ctrl->shared_data->hw_rev) != |
| 1979 | MDSS_DSI_HW_REV_STEP_2)) { |
| 1980 | |
| 1981 | regval = MIPI_INP(ctrl->mmss_misc_io.base + |
| 1982 | clamp_reg_off); |
| 1983 | MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, |
| 1984 | regval | BIT(30)); |
| 1985 | } else { |
| 1986 | MIPI_OUTP(ctrl->mmss_misc_io.base + phyrst_reg_off, |
| 1987 | 0x1); |
| 1988 | } |
| 1989 | /* make sure that clamp ctrl is updated before disable call */ |
| 1990 | wmb(); |
| 1991 | ctrl->mmss_clamp = true; |
| 1992 | } else if (!enable && ctrl->mmss_clamp) { |
| 1993 | if (IS_MDSS_MAJOR_MINOR_SAME(ctrl->shared_data->hw_rev, |
| 1994 | MDSS_DSI_HW_REV_104) && |
| 1995 | (MDSS_GET_STEP(ctrl->shared_data->hw_rev) != |
| 1996 | MDSS_DSI_HW_REV_STEP_2)) { |
| 1997 | |
| 1998 | regval = MIPI_INP(ctrl->mmss_misc_io.base + |
| 1999 | clamp_reg_off); |
| 2000 | MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, |
| 2001 | regval & ~BIT(30)); |
| 2002 | } else { |
| 2003 | MIPI_OUTP(ctrl->mmss_misc_io.base + phyrst_reg_off, |
| 2004 | 0x0); |
| 2005 | } |
| 2006 | /* update clamp ctrl before unsetting phy reset disable */ |
| 2007 | wmb(); |
| 2008 | |
| 2009 | regval = MIPI_INP(ctrl->mmss_misc_io.base + clamp_reg_off); |
| 2010 | /* Disable MMSS DSI Clamps */ |
| 2011 | if (ctrl->ndx == DSI_CTRL_0) |
| 2012 | MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, |
| 2013 | regval & ~(clamp_reg | BIT(15))); |
| 2014 | else if (ctrl->ndx == DSI_CTRL_1) |
| 2015 | MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, |
| 2016 | regval & ~((clamp_reg << 16) | BIT(31))); |
| 2017 | /* make sure that clamp ctrl is updated before enable call */ |
| 2018 | wmb(); |
| 2019 | ctrl->mmss_clamp = false; |
| 2020 | } else { |
| 2021 | pr_debug("%s: No change requested: %s -> %s\n", __func__, |
| 2022 | ctrl->mmss_clamp ? "enabled" : "disabled", |
| 2023 | enable ? "enabled" : "disabled"); |
| 2024 | } |
| 2025 | |
| 2026 | return 0; |
| 2027 | } |
| 2028 | |
| 2029 | DEFINE_MUTEX(dsi_clk_mutex); |
| 2030 | |
| 2031 | int mdss_dsi_clk_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, void *clk_handle, |
| 2032 | enum mdss_dsi_clk_type clk_type, enum mdss_dsi_clk_state clk_state) |
| 2033 | { |
| 2034 | int rc = 0; |
| 2035 | struct mdss_dsi_ctrl_pdata *mctrl = NULL; |
| 2036 | int i, *vote_cnt; |
| 2037 | |
| 2038 | void *m_clk_handle; |
| 2039 | bool is_ecg = false; |
| 2040 | int state = MDSS_DSI_CLK_OFF; |
| 2041 | |
| 2042 | if (!ctrl) { |
| 2043 | pr_err("%s: Invalid arg\n", __func__); |
| 2044 | return -EINVAL; |
| 2045 | } |
| 2046 | |
| 2047 | mutex_lock(&dsi_clk_mutex); |
| 2048 | /* |
| 2049 | * In sync_wait_broadcast mode, we need to enable clocks |
| 2050 | * for the other controller as well when enabling clocks |
| 2051 | * for the trigger controller. |
| 2052 | * |
| 2053 | * If sync wait_broadcase mode is not enabled, but if split display |
| 2054 | * mode is enabled where both DSI controller's branch clocks are |
| 2055 | * sourced out of a single PLL, then we need to ensure that the |
| 2056 | * controller associated with that PLL also has it's clocks turned |
| 2057 | * on. This is required to make sure that if that controller's PLL/PHY |
| 2058 | * are clamped then they can be removed. |
| 2059 | */ |
| 2060 | if (mdss_dsi_sync_wait_trigger(ctrl)) { |
| 2061 | mctrl = mdss_dsi_get_other_ctrl(ctrl); |
| 2062 | if (!mctrl) |
| 2063 | pr_warn("%s: Unable to get other control\n", __func__); |
| 2064 | } else if (mdss_dsi_is_ctrl_clk_slave(ctrl)) { |
| 2065 | mctrl = mdss_dsi_get_ctrl_clk_master(); |
| 2066 | if (!mctrl) |
| 2067 | pr_warn("%s: Unable to get clk master control\n", |
| 2068 | __func__); |
| 2069 | } |
| 2070 | |
| 2071 | /* |
| 2072 | * it should add and remove extra votes based on voting clients to avoid |
| 2073 | * removal of legitimate vote from DSI client. |
| 2074 | */ |
| 2075 | if (mctrl && (clk_handle == ctrl->dsi_clk_handle)) { |
| 2076 | m_clk_handle = mctrl->dsi_clk_handle; |
| 2077 | vote_cnt = &mctrl->m_dsi_vote_cnt; |
| 2078 | } else if (mctrl) { |
| 2079 | m_clk_handle = mctrl->mdp_clk_handle; |
| 2080 | vote_cnt = &mctrl->m_mdp_vote_cnt; |
| 2081 | } |
| 2082 | |
| 2083 | /* |
| 2084 | * When DSI is used in split mode, the link clock for master controller |
| 2085 | * has to be turned on first before the link clock for slave can be |
| 2086 | * turned on. In case the current controller is a slave, an ON vote is |
| 2087 | * cast for master before changing the state of the slave clock. After |
| 2088 | * the state change for slave, the ON votes will be removed depending on |
| 2089 | * the new state. |
| 2090 | */ |
| 2091 | pr_debug("%s: DSI_%d: clk = %d, state = %d, caller = %pS, mctrl=%d\n", |
| 2092 | __func__, ctrl->ndx, clk_type, clk_state, |
| 2093 | __builtin_return_address(0), mctrl ? 1 : 0); |
| 2094 | if (mctrl && (clk_type & MDSS_DSI_LINK_CLK)) { |
| 2095 | if (clk_state != MDSS_DSI_CLK_ON) { |
| 2096 | /* preserve clk state; do not turn off forcefully */ |
| 2097 | is_ecg = is_dsi_clk_in_ecg_state(m_clk_handle); |
| 2098 | if (is_ecg) |
| 2099 | state = MDSS_DSI_CLK_EARLY_GATE; |
| 2100 | } |
| 2101 | |
| 2102 | rc = mdss_dsi_clk_req_state(m_clk_handle, |
| 2103 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON, mctrl->ndx); |
| 2104 | if (rc) { |
| 2105 | pr_err("%s: failed to turn on mctrl clocks, rc=%d\n", |
| 2106 | __func__, rc); |
| 2107 | goto error; |
| 2108 | } |
| 2109 | (*vote_cnt)++; |
| 2110 | } |
| 2111 | |
| 2112 | rc = mdss_dsi_clk_req_state(clk_handle, clk_type, clk_state, ctrl->ndx); |
| 2113 | if (rc) { |
| 2114 | pr_err("%s: failed set clk state, rc = %d\n", __func__, rc); |
| 2115 | goto error; |
| 2116 | } |
| 2117 | |
| 2118 | if (mctrl && (clk_type & MDSS_DSI_LINK_CLK) && |
| 2119 | clk_state != MDSS_DSI_CLK_ON) { |
| 2120 | |
| 2121 | /* |
| 2122 | * In case of split dsi, an ON vote is cast for all state change |
| 2123 | * requests. If the current state is ON, then the vote would not |
| 2124 | * be released. |
| 2125 | * |
| 2126 | * If the current state is ECG, there is one possible way to |
| 2127 | * transition in to this state, which is ON -> ECG. In this case |
| 2128 | * two votes will be removed because one was cast at ON and |
| 2129 | * other when entering ECG. |
| 2130 | * |
| 2131 | * If the current state is OFF, it could have been due to two |
| 2132 | * possible transitions in to OFF state. |
| 2133 | * 1. ON -> OFF: In this case two votes were cast by the |
| 2134 | * slave controller, one during ON (which is not |
| 2135 | * removed) and one during OFF. So we need to remove two |
| 2136 | * votes. |
| 2137 | * 2. ECG -> OFF: In this case there is only one vote |
| 2138 | * for ON, since the previous ECG state must have |
| 2139 | * removed two votes to let clocks turn off. |
| 2140 | * |
| 2141 | * To satisfy the above requirement, vote_cnt keeps track of |
| 2142 | * the number of ON votes for master requested by slave. For |
| 2143 | * every OFF/ECG state request, Either 2 or vote_cnt number of |
| 2144 | * votes are removed depending on which is lower. |
| 2145 | */ |
| 2146 | for (i = 0; (i < *vote_cnt && i < 2); i++) { |
| 2147 | rc = mdss_dsi_clk_req_state(m_clk_handle, |
| 2148 | MDSS_DSI_ALL_CLKS, state, mctrl->ndx); |
| 2149 | if (rc) { |
| 2150 | pr_err("%s: failed to set mctrl clk state, rc = %d\n", |
| 2151 | __func__, rc); |
| 2152 | goto error; |
| 2153 | } |
| 2154 | } |
| 2155 | (*vote_cnt) -= i; |
| 2156 | pr_debug("%s: ctrl=%d, vote_cnt=%d dsi_vote_cnt=%d mdp_vote_cnt:%d\n", |
| 2157 | __func__, ctrl->ndx, *vote_cnt, mctrl->m_dsi_vote_cnt, |
| 2158 | mctrl->m_mdp_vote_cnt); |
| 2159 | } |
| 2160 | |
| 2161 | error: |
| 2162 | mutex_unlock(&dsi_clk_mutex); |
| 2163 | return rc; |
| 2164 | } |
| 2165 | |
| 2166 | int mdss_dsi_pre_clkoff_cb(void *priv, |
| 2167 | enum mdss_dsi_clk_type clk, |
| 2168 | enum mdss_dsi_clk_state new_state) |
| 2169 | { |
| 2170 | int rc = 0; |
| 2171 | struct mdss_dsi_ctrl_pdata *ctrl = priv; |
| 2172 | struct mdss_panel_data *pdata = NULL; |
| 2173 | |
| 2174 | pdata = &ctrl->panel_data; |
| 2175 | |
| 2176 | if ((clk & MDSS_DSI_LINK_CLK) && (new_state == MDSS_DSI_CLK_OFF)) { |
| 2177 | /* |
| 2178 | * If ULPS feature is enabled, enter ULPS first. |
| 2179 | * However, when blanking the panel, we should enter ULPS |
| 2180 | * only if ULPS during suspend feature is enabled. |
| 2181 | */ |
| 2182 | if (!(ctrl->ctrl_state & CTRL_STATE_PANEL_INIT)) { |
| 2183 | if (pdata->panel_info.ulps_suspend_enabled) |
| 2184 | mdss_dsi_ulps_config(ctrl, 1); |
| 2185 | } else if (mdss_dsi_ulps_feature_enabled(pdata)) { |
| 2186 | rc = mdss_dsi_ulps_config(ctrl, 1); |
| 2187 | } |
| 2188 | if (rc) { |
| 2189 | pr_err("%s: failed enable ulps, rc = %d\n", |
| 2190 | __func__, rc); |
| 2191 | } |
| 2192 | } |
| 2193 | |
| 2194 | if ((clk & MDSS_DSI_CORE_CLK) && (new_state == MDSS_DSI_CLK_OFF)) { |
| 2195 | /* |
| 2196 | * Enable DSI clamps only if entering idle power collapse or |
| 2197 | * when ULPS during suspend is enabled. |
| 2198 | */ |
| 2199 | if ((ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) || |
| 2200 | pdata->panel_info.ulps_suspend_enabled) { |
| 2201 | mdss_dsi_phy_power_off(ctrl); |
| 2202 | rc = mdss_dsi_clamp_ctrl(ctrl, 1); |
| 2203 | if (rc) |
| 2204 | pr_err("%s: Failed to enable dsi clamps. rc=%d\n", |
| 2205 | __func__, rc); |
| 2206 | } else { |
| 2207 | /* |
| 2208 | * Make sure that controller is not in ULPS state when |
| 2209 | * the DSI link is not active. |
| 2210 | */ |
| 2211 | rc = mdss_dsi_ulps_config(ctrl, 0); |
| 2212 | if (rc) |
| 2213 | pr_err("%s: failed to disable ulps. rc=%d\n", |
| 2214 | __func__, rc); |
| 2215 | } |
| 2216 | } |
| 2217 | |
| 2218 | return rc; |
| 2219 | } |
| 2220 | |
| 2221 | int mdss_dsi_post_clkon_cb(void *priv, |
| 2222 | enum mdss_dsi_clk_type clk, |
| 2223 | enum mdss_dsi_clk_state curr_state) |
| 2224 | { |
| 2225 | int rc = 0; |
| 2226 | struct mdss_panel_data *pdata = NULL; |
| 2227 | struct mdss_dsi_ctrl_pdata *ctrl = priv; |
| 2228 | bool mmss_clamp; |
| 2229 | |
| 2230 | pdata = &ctrl->panel_data; |
| 2231 | |
| 2232 | if (clk & MDSS_DSI_CORE_CLK) { |
| 2233 | mmss_clamp = ctrl->mmss_clamp; |
| 2234 | /* |
| 2235 | * controller setup is needed if coming out of idle |
| 2236 | * power collapse with clamps enabled. |
| 2237 | */ |
| 2238 | if (mmss_clamp) |
| 2239 | mdss_dsi_ctrl_setup(ctrl); |
| 2240 | |
| 2241 | if (ctrl->ulps) { |
| 2242 | /* |
| 2243 | * ULPS Entry Request. This is needed if the lanes were |
| 2244 | * in ULPS prior to power collapse, since after |
| 2245 | * power collapse and reset, the DSI controller resets |
| 2246 | * back to idle state and not ULPS. This ulps entry |
| 2247 | * request will transition the state of the DSI |
| 2248 | * controller to ULPS which will match the state of the |
| 2249 | * DSI phy. This needs to be done prior to disabling |
| 2250 | * the DSI clamps. |
| 2251 | * |
| 2252 | * Also, reset the ulps flag so that ulps_config |
| 2253 | * function would reconfigure the controller state to |
| 2254 | * ULPS. |
| 2255 | */ |
| 2256 | ctrl->ulps = false; |
| 2257 | rc = mdss_dsi_ulps_config(ctrl, 1); |
| 2258 | if (rc) { |
| 2259 | pr_err("%s: Failed to enter ULPS. rc=%d\n", |
| 2260 | __func__, rc); |
| 2261 | goto error; |
| 2262 | } |
| 2263 | } |
| 2264 | |
| 2265 | rc = mdss_dsi_clamp_ctrl(ctrl, 0); |
| 2266 | if (rc) { |
| 2267 | pr_err("%s: Failed to disable dsi clamps. rc=%d\n", |
| 2268 | __func__, rc); |
| 2269 | goto error; |
| 2270 | } |
| 2271 | |
| 2272 | /* |
| 2273 | * Phy setup is needed if coming out of idle |
| 2274 | * power collapse with clamps enabled. |
| 2275 | */ |
| 2276 | if (ctrl->phy_power_off || mmss_clamp) |
| 2277 | mdss_dsi_phy_power_on(ctrl, mmss_clamp); |
| 2278 | } |
| 2279 | if (clk & MDSS_DSI_LINK_CLK) { |
| 2280 | if (ctrl->ulps) { |
| 2281 | rc = mdss_dsi_ulps_config(ctrl, 0); |
| 2282 | if (rc) { |
| 2283 | pr_err("%s: failed to disable ulps, rc= %d\n", |
| 2284 | __func__, rc); |
| 2285 | goto error; |
| 2286 | } |
| 2287 | } |
| 2288 | } |
| 2289 | error: |
| 2290 | return rc; |
| 2291 | } |
| 2292 | |
| 2293 | int mdss_dsi_post_clkoff_cb(void *priv, |
| 2294 | enum mdss_dsi_clk_type clk_type, |
| 2295 | enum mdss_dsi_clk_state curr_state) |
| 2296 | { |
| 2297 | int rc = 0; |
| 2298 | struct mdss_dsi_ctrl_pdata *ctrl = priv; |
| 2299 | struct mdss_panel_data *pdata = NULL; |
| 2300 | struct dsi_shared_data *sdata; |
| 2301 | int i; |
| 2302 | |
| 2303 | if (!ctrl) { |
| 2304 | pr_err("%s: Invalid arg\n", __func__); |
| 2305 | return -EINVAL; |
| 2306 | } |
| 2307 | |
| 2308 | pdata = &ctrl->panel_data; |
| 2309 | if ((clk_type & MDSS_DSI_CORE_CLK) && |
| 2310 | (curr_state == MDSS_DSI_CLK_OFF)) { |
| 2311 | sdata = ctrl->shared_data; |
| 2312 | |
| 2313 | for (i = DSI_MAX_PM - 1; i >= DSI_CORE_PM; i--) { |
| 2314 | if ((ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) && |
| 2315 | (i != DSI_CORE_PM)) |
| 2316 | continue; |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 2317 | rc = msm_mdss_enable_vreg( |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 2318 | sdata->power_data[i].vreg_config, |
| 2319 | sdata->power_data[i].num_vreg, 0); |
| 2320 | if (rc) { |
| 2321 | pr_warn("%s: failed to disable vregs for %s\n", |
| 2322 | __func__, |
| 2323 | __mdss_dsi_pm_name(i)); |
| 2324 | rc = 0; |
| 2325 | } else { |
| 2326 | ctrl->core_power = false; |
| 2327 | } |
| 2328 | } |
| 2329 | |
| 2330 | /* |
| 2331 | * temp workaround until framework issues pertaining to LP2 |
| 2332 | * power state transitions are fixed. For now, we internally |
| 2333 | * transition to LP2 state whenever core power is turned off |
| 2334 | * in LP1 state |
| 2335 | */ |
| 2336 | if (mdss_dsi_is_panel_on_lp(pdata)) |
| 2337 | mdss_dsi_panel_power_ctrl(pdata, |
| 2338 | MDSS_PANEL_POWER_LP2); |
| 2339 | } |
| 2340 | return rc; |
| 2341 | } |
| 2342 | |
| 2343 | int mdss_dsi_pre_clkon_cb(void *priv, |
| 2344 | enum mdss_dsi_clk_type clk_type, |
| 2345 | enum mdss_dsi_clk_state new_state) |
| 2346 | { |
| 2347 | int rc = 0; |
| 2348 | struct mdss_dsi_ctrl_pdata *ctrl = priv; |
| 2349 | struct mdss_panel_data *pdata = NULL; |
| 2350 | struct dsi_shared_data *sdata; |
| 2351 | int i; |
| 2352 | |
| 2353 | if (!ctrl) { |
| 2354 | pr_err("%s: invalid input\n", __func__); |
| 2355 | return -EINVAL; |
| 2356 | } |
| 2357 | |
| 2358 | pdata = &ctrl->panel_data; |
| 2359 | if ((clk_type & MDSS_DSI_CORE_CLK) && (new_state == MDSS_DSI_CLK_ON) && |
| 2360 | (ctrl->core_power == false)) { |
| 2361 | sdata = ctrl->shared_data; |
| 2362 | /* |
| 2363 | * Enable DSI core power |
| 2364 | * 1.> PANEL_PM are controlled as part of |
| 2365 | * panel_power_ctrl. Needed not be handled here. |
| 2366 | * 2.> CORE_PM are controlled by dsi clk manager. |
| 2367 | * 3.> CTRL_PM need to be enabled/disabled |
| 2368 | * only during unblank/blank. Their state should |
| 2369 | * not be changed during static screen. |
| 2370 | */ |
| 2371 | pr_debug("%s: Enable DSI core power\n", __func__); |
| 2372 | for (i = DSI_CORE_PM; i < DSI_MAX_PM; i++) { |
| 2373 | if ((ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) && |
| 2374 | (!pdata->panel_info.cont_splash_enabled) && |
| 2375 | (i != DSI_CORE_PM)) |
| 2376 | continue; |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 2377 | rc = msm_mdss_enable_vreg( |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 2378 | sdata->power_data[i].vreg_config, |
| 2379 | sdata->power_data[i].num_vreg, 1); |
| 2380 | if (rc) { |
| 2381 | pr_err("%s: failed to enable vregs for %s\n", |
| 2382 | __func__, |
| 2383 | __mdss_dsi_pm_name(i)); |
| 2384 | } else { |
| 2385 | ctrl->core_power = true; |
| 2386 | } |
| 2387 | |
| 2388 | } |
| 2389 | /* |
| 2390 | * temp workaround until framework issues pertaining to LP2 |
| 2391 | * power state transitions are fixed. For now, if we intend to |
| 2392 | * send a frame update when in LP1, we have to explicitly exit |
| 2393 | * LP2 state here |
| 2394 | */ |
| 2395 | if (mdss_dsi_is_panel_on_ulp(pdata)) |
| 2396 | mdss_dsi_panel_power_ctrl(pdata, MDSS_PANEL_POWER_LP1); |
| 2397 | } |
| 2398 | /* Disable dynamic clock gating*/ |
| 2399 | if (ctrl->mdss_util->dyn_clk_gating_ctrl) |
| 2400 | ctrl->mdss_util->dyn_clk_gating_ctrl(0); |
| 2401 | |
| 2402 | return rc; |
| 2403 | } |
| 2404 | |
| 2405 | void mdss_edp_clk_deinit(struct mdss_edp_drv_pdata *edp_drv) |
| 2406 | { |
| 2407 | if (edp_drv->aux_clk) |
| 2408 | clk_put(edp_drv->aux_clk); |
| 2409 | if (edp_drv->pixel_clk) |
| 2410 | clk_put(edp_drv->pixel_clk); |
| 2411 | if (edp_drv->ahb_clk) |
| 2412 | clk_put(edp_drv->ahb_clk); |
| 2413 | if (edp_drv->link_clk) |
| 2414 | clk_put(edp_drv->link_clk); |
| 2415 | if (edp_drv->mdp_core_clk) |
| 2416 | clk_put(edp_drv->mdp_core_clk); |
| 2417 | } |
| 2418 | |
| 2419 | int mdss_edp_clk_init(struct mdss_edp_drv_pdata *edp_drv) |
| 2420 | { |
| 2421 | struct device *dev = &(edp_drv->pdev->dev); |
| 2422 | |
| 2423 | edp_drv->aux_clk = clk_get(dev, "core_clk"); |
| 2424 | if (IS_ERR(edp_drv->aux_clk)) { |
| 2425 | pr_err("%s: Can't find aux_clk", __func__); |
| 2426 | edp_drv->aux_clk = NULL; |
| 2427 | goto mdss_edp_clk_err; |
| 2428 | } |
| 2429 | |
| 2430 | edp_drv->pixel_clk = clk_get(dev, "pixel_clk"); |
| 2431 | if (IS_ERR(edp_drv->pixel_clk)) { |
| 2432 | pr_err("%s: Can't find pixel_clk", __func__); |
| 2433 | edp_drv->pixel_clk = NULL; |
| 2434 | goto mdss_edp_clk_err; |
| 2435 | } |
| 2436 | |
| 2437 | edp_drv->ahb_clk = clk_get(dev, "iface_clk"); |
| 2438 | if (IS_ERR(edp_drv->ahb_clk)) { |
| 2439 | pr_err("%s: Can't find ahb_clk", __func__); |
| 2440 | edp_drv->ahb_clk = NULL; |
| 2441 | goto mdss_edp_clk_err; |
| 2442 | } |
| 2443 | |
| 2444 | edp_drv->link_clk = clk_get(dev, "link_clk"); |
| 2445 | if (IS_ERR(edp_drv->link_clk)) { |
| 2446 | pr_err("%s: Can't find link_clk", __func__); |
| 2447 | edp_drv->link_clk = NULL; |
| 2448 | goto mdss_edp_clk_err; |
| 2449 | } |
| 2450 | |
| 2451 | /* need mdss clock to receive irq */ |
| 2452 | edp_drv->mdp_core_clk = clk_get(dev, "mdp_core_clk"); |
| 2453 | if (IS_ERR(edp_drv->mdp_core_clk)) { |
| 2454 | pr_err("%s: Can't find mdp_core_clk", __func__); |
| 2455 | edp_drv->mdp_core_clk = NULL; |
| 2456 | goto mdss_edp_clk_err; |
| 2457 | } |
| 2458 | |
| 2459 | return 0; |
| 2460 | |
| 2461 | mdss_edp_clk_err: |
| 2462 | mdss_edp_clk_deinit(edp_drv); |
| 2463 | return -EPERM; |
| 2464 | } |
| 2465 | |
| 2466 | int mdss_edp_aux_clk_enable(struct mdss_edp_drv_pdata *edp_drv) |
| 2467 | { |
| 2468 | int ret; |
| 2469 | |
| 2470 | if (clk_set_rate(edp_drv->aux_clk, 19200000) < 0) |
| 2471 | pr_err("%s: aux_clk - clk_set_rate failed\n", |
| 2472 | __func__); |
| 2473 | |
| 2474 | ret = clk_enable(edp_drv->aux_clk); |
| 2475 | if (ret) { |
| 2476 | pr_err("%s: Failed to enable aux clk\n", __func__); |
| 2477 | goto c2; |
| 2478 | } |
| 2479 | |
| 2480 | ret = clk_enable(edp_drv->ahb_clk); |
| 2481 | if (ret) { |
| 2482 | pr_err("%s: Failed to enable ahb clk\n", __func__); |
| 2483 | goto c1; |
| 2484 | } |
| 2485 | |
| 2486 | /* need mdss clock to receive irq */ |
| 2487 | ret = clk_enable(edp_drv->mdp_core_clk); |
| 2488 | if (ret) { |
| 2489 | pr_err("%s: Failed to enable mdp_core_clk\n", __func__); |
| 2490 | goto c0; |
| 2491 | } |
| 2492 | |
| 2493 | return 0; |
| 2494 | c0: |
| 2495 | clk_disable(edp_drv->ahb_clk); |
| 2496 | c1: |
| 2497 | clk_disable(edp_drv->aux_clk); |
| 2498 | c2: |
| 2499 | return ret; |
| 2500 | |
| 2501 | } |
| 2502 | |
| 2503 | void mdss_edp_aux_clk_disable(struct mdss_edp_drv_pdata *edp_drv) |
| 2504 | { |
| 2505 | clk_disable(edp_drv->aux_clk); |
| 2506 | clk_disable(edp_drv->ahb_clk); |
| 2507 | clk_disable(edp_drv->mdp_core_clk); |
| 2508 | } |
| 2509 | |
| 2510 | static void mdss_edp_clk_set_rate(struct mdss_edp_drv_pdata *edp_drv) |
| 2511 | { |
| 2512 | if (clk_set_rate(edp_drv->link_clk, edp_drv->link_rate * 27000000) < 0) |
| 2513 | pr_err("%s: link_clk - clk_set_rate failed\n", |
| 2514 | __func__); |
| 2515 | |
| 2516 | if (clk_set_rate(edp_drv->pixel_clk, edp_drv->pixel_rate) < 0) |
| 2517 | pr_err("%s: pixel_clk - clk_set_rate failed\n", |
| 2518 | __func__); |
| 2519 | } |
| 2520 | |
| 2521 | int mdss_edp_clk_enable(struct mdss_edp_drv_pdata *edp_drv) |
| 2522 | { |
| 2523 | int ret; |
| 2524 | |
| 2525 | if (edp_drv->clk_on) { |
| 2526 | pr_info("%s: edp clks are already ON\n", __func__); |
| 2527 | return 0; |
| 2528 | } |
| 2529 | |
| 2530 | if (clk_set_rate(edp_drv->link_clk, edp_drv->link_rate * 27000000) < 0) |
| 2531 | pr_err("%s: link_clk - clk_set_rate failed\n", |
| 2532 | __func__); |
| 2533 | |
| 2534 | if (clk_set_rate(edp_drv->aux_clk, edp_drv->aux_rate) < 0) |
| 2535 | pr_err("%s: aux_clk - clk_set_rate failed\n", |
| 2536 | __func__); |
| 2537 | |
| 2538 | if (clk_set_rate(edp_drv->pixel_clk, edp_drv->pixel_rate) < 0) |
| 2539 | pr_err("%s: pixel_clk - clk_set_rate failed\n", |
| 2540 | __func__); |
| 2541 | |
| 2542 | ret = clk_enable(edp_drv->aux_clk); |
| 2543 | if (ret) { |
| 2544 | pr_err("%s: Failed to enable aux clk\n", __func__); |
| 2545 | goto c4; |
| 2546 | } |
| 2547 | ret = clk_enable(edp_drv->pixel_clk); |
| 2548 | if (ret) { |
| 2549 | pr_err("%s: Failed to enable pixel clk\n", __func__); |
| 2550 | goto c3; |
| 2551 | } |
| 2552 | ret = clk_enable(edp_drv->ahb_clk); |
| 2553 | if (ret) { |
| 2554 | pr_err("%s: Failed to enable ahb clk\n", __func__); |
| 2555 | goto c2; |
| 2556 | } |
| 2557 | ret = clk_enable(edp_drv->link_clk); |
| 2558 | if (ret) { |
| 2559 | pr_err("%s: Failed to enable link clk\n", __func__); |
| 2560 | goto c1; |
| 2561 | } |
| 2562 | ret = clk_enable(edp_drv->mdp_core_clk); |
| 2563 | if (ret) { |
| 2564 | pr_err("%s: Failed to enable mdp_core_clk\n", __func__); |
| 2565 | goto c0; |
| 2566 | } |
| 2567 | |
| 2568 | edp_drv->clk_on = 1; |
| 2569 | |
| 2570 | return 0; |
| 2571 | |
| 2572 | c0: |
| 2573 | clk_disable(edp_drv->link_clk); |
| 2574 | c1: |
| 2575 | clk_disable(edp_drv->ahb_clk); |
| 2576 | c2: |
| 2577 | clk_disable(edp_drv->pixel_clk); |
| 2578 | c3: |
| 2579 | clk_disable(edp_drv->aux_clk); |
| 2580 | c4: |
| 2581 | return ret; |
| 2582 | } |
| 2583 | |
| 2584 | void mdss_edp_clk_disable(struct mdss_edp_drv_pdata *edp_drv) |
| 2585 | { |
| 2586 | if (edp_drv->clk_on == 0) { |
| 2587 | pr_info("%s: edp clks are already OFF\n", __func__); |
| 2588 | return; |
| 2589 | } |
| 2590 | |
| 2591 | clk_disable(edp_drv->aux_clk); |
| 2592 | clk_disable(edp_drv->pixel_clk); |
| 2593 | clk_disable(edp_drv->ahb_clk); |
| 2594 | clk_disable(edp_drv->link_clk); |
| 2595 | clk_disable(edp_drv->mdp_core_clk); |
| 2596 | |
| 2597 | edp_drv->clk_on = 0; |
| 2598 | } |
| 2599 | |
| 2600 | int mdss_edp_prepare_aux_clocks(struct mdss_edp_drv_pdata *edp_drv) |
| 2601 | { |
| 2602 | int ret; |
| 2603 | |
| 2604 | /* ahb clock should be prepared first */ |
| 2605 | ret = clk_prepare(edp_drv->ahb_clk); |
| 2606 | if (ret) { |
| 2607 | pr_err("%s: Failed to prepare ahb clk\n", __func__); |
| 2608 | goto c3; |
| 2609 | } |
| 2610 | ret = clk_prepare(edp_drv->aux_clk); |
| 2611 | if (ret) { |
| 2612 | pr_err("%s: Failed to prepare aux clk\n", __func__); |
| 2613 | goto c2; |
| 2614 | } |
| 2615 | |
| 2616 | /* need mdss clock to receive irq */ |
| 2617 | ret = clk_prepare(edp_drv->mdp_core_clk); |
| 2618 | if (ret) { |
| 2619 | pr_err("%s: Failed to prepare mdp_core clk\n", __func__); |
| 2620 | goto c1; |
| 2621 | } |
| 2622 | |
| 2623 | return 0; |
| 2624 | c1: |
| 2625 | clk_unprepare(edp_drv->aux_clk); |
| 2626 | c2: |
| 2627 | clk_unprepare(edp_drv->ahb_clk); |
| 2628 | c3: |
| 2629 | return ret; |
| 2630 | |
| 2631 | } |
| 2632 | |
| 2633 | void mdss_edp_unprepare_aux_clocks(struct mdss_edp_drv_pdata *edp_drv) |
| 2634 | { |
| 2635 | clk_unprepare(edp_drv->mdp_core_clk); |
| 2636 | clk_unprepare(edp_drv->aux_clk); |
| 2637 | clk_unprepare(edp_drv->ahb_clk); |
| 2638 | } |
| 2639 | |
| 2640 | int mdss_edp_prepare_clocks(struct mdss_edp_drv_pdata *edp_drv) |
| 2641 | { |
| 2642 | int ret; |
| 2643 | |
| 2644 | mdss_edp_clk_set_rate(edp_drv); |
| 2645 | |
| 2646 | /* ahb clock should be prepared first */ |
| 2647 | ret = clk_prepare(edp_drv->ahb_clk); |
| 2648 | if (ret) { |
| 2649 | pr_err("%s: Failed to prepare ahb clk\n", __func__); |
| 2650 | goto c4; |
| 2651 | } |
| 2652 | ret = clk_prepare(edp_drv->aux_clk); |
| 2653 | if (ret) { |
| 2654 | pr_err("%s: Failed to prepare aux clk\n", __func__); |
| 2655 | goto c3; |
| 2656 | } |
| 2657 | ret = clk_prepare(edp_drv->pixel_clk); |
| 2658 | if (ret) { |
| 2659 | pr_err("%s: Failed to prepare pixel clk\n", __func__); |
| 2660 | goto c2; |
| 2661 | } |
| 2662 | ret = clk_prepare(edp_drv->link_clk); |
| 2663 | if (ret) { |
| 2664 | pr_err("%s: Failed to prepare link clk\n", __func__); |
| 2665 | goto c1; |
| 2666 | } |
| 2667 | ret = clk_prepare(edp_drv->mdp_core_clk); |
| 2668 | if (ret) { |
| 2669 | pr_err("%s: Failed to prepare mdp_core clk\n", __func__); |
| 2670 | goto c0; |
| 2671 | } |
| 2672 | |
| 2673 | return 0; |
| 2674 | c0: |
| 2675 | clk_unprepare(edp_drv->link_clk); |
| 2676 | c1: |
| 2677 | clk_unprepare(edp_drv->pixel_clk); |
| 2678 | c2: |
| 2679 | clk_unprepare(edp_drv->aux_clk); |
| 2680 | c3: |
| 2681 | clk_unprepare(edp_drv->ahb_clk); |
| 2682 | c4: |
| 2683 | return ret; |
| 2684 | } |
| 2685 | |
| 2686 | void mdss_edp_unprepare_clocks(struct mdss_edp_drv_pdata *edp_drv) |
| 2687 | { |
| 2688 | clk_unprepare(edp_drv->mdp_core_clk); |
| 2689 | clk_unprepare(edp_drv->aux_clk); |
| 2690 | clk_unprepare(edp_drv->pixel_clk); |
| 2691 | clk_unprepare(edp_drv->link_clk); |
| 2692 | /* ahb clock should be last one to disable */ |
| 2693 | clk_unprepare(edp_drv->ahb_clk); |
| 2694 | } |
| 2695 | |
| 2696 | void mdss_edp_clk_debug(unsigned char *edp_base, unsigned char *mmss_cc_base) |
| 2697 | { |
| 2698 | u32 da4, da0, d32c; |
| 2699 | u32 dc4, dc0, d330; |
| 2700 | |
| 2701 | /* pixel clk */ |
| 2702 | da0 = edp_read(mmss_cc_base + 0x0a0); |
| 2703 | da4 = edp_read(mmss_cc_base + 0x0a4); |
| 2704 | d32c = edp_read(mmss_cc_base + 0x32c); |
| 2705 | |
| 2706 | /* main link clk */ |
| 2707 | dc0 = edp_read(mmss_cc_base + 0x0c0); |
| 2708 | dc4 = edp_read(mmss_cc_base + 0x0c4); |
| 2709 | d330 = edp_read(mmss_cc_base + 0x330); |
| 2710 | |
| 2711 | pr_err("%s: da0=%x da4=%x d32c=%x dc0=%x dc4=%x d330=%x\n", __func__, |
| 2712 | (int)da0, (int)da4, (int)d32c, (int)dc0, (int)dc4, (int)d330); |
| 2713 | |
| 2714 | } |