Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 1 | /* |
Hirokazu Takata | 3264f97 | 2007-08-01 21:09:31 +0900 | [diff] [blame] | 2 | * linux/arch/m32r/platforms/mappi3/setup.c |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 3 | * |
| 4 | * Setup routines for Renesas MAPPI-III(M3A-2170) Board |
| 5 | * |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 6 | * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata, |
| 7 | * Hitoshi Yamamoto, Mamoru Sakugawa |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 8 | */ |
| 9 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 10 | #include <linux/irq.h> |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 13 | #include <linux/platform_device.h> |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 14 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 15 | #include <asm/m32r.h> |
| 16 | #include <asm/io.h> |
| 17 | |
| 18 | #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long))) |
| 19 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 20 | icu_data_t icu_data[NR_IRQS]; |
| 21 | |
| 22 | static void disable_mappi3_irq(unsigned int irq) |
| 23 | { |
| 24 | unsigned long port, data; |
| 25 | |
| 26 | if ((irq == 0) ||(irq >= NR_IRQS)) { |
| 27 | printk("bad irq 0x%08x\n", irq); |
| 28 | return; |
| 29 | } |
| 30 | port = irq2port(irq); |
| 31 | data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7; |
| 32 | outl(data, port); |
| 33 | } |
| 34 | |
| 35 | static void enable_mappi3_irq(unsigned int irq) |
| 36 | { |
| 37 | unsigned long port, data; |
| 38 | |
| 39 | if ((irq == 0) ||(irq >= NR_IRQS)) { |
| 40 | printk("bad irq 0x%08x\n", irq); |
| 41 | return; |
| 42 | } |
| 43 | port = irq2port(irq); |
| 44 | data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; |
| 45 | outl(data, port); |
| 46 | } |
| 47 | |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 48 | static void mask_mappi3(struct irq_data *data) |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 49 | { |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 50 | disable_mappi3_irq(data->irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 51 | } |
| 52 | |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 53 | static void unmask_mappi3(struct irq_data *data) |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 54 | { |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 55 | enable_mappi3_irq(data->irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 56 | } |
| 57 | |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 58 | static void shutdown_mappi3(struct irq_data *data) |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 59 | { |
| 60 | unsigned long port; |
| 61 | |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 62 | port = irq2port(data->irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 63 | outl(M32R_ICUCR_ILEVEL7, port); |
| 64 | } |
| 65 | |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 66 | static struct irq_chip mappi3_irq_type = { |
| 67 | .name = "MAPPI3-IRQ", |
| 68 | .irq_shutdown = shutdown_mappi3, |
| 69 | .irq_mask = mask_mappi3, |
| 70 | .irq_unmask = unmask_mappi3, |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | void __init init_IRQ(void) |
| 74 | { |
| 75 | #if defined(CONFIG_SMC91X) |
| 76 | /* INT0 : LAN controller (SMC91111) */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 77 | irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 78 | handle_level_irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 79 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
| 80 | disable_mappi3_irq(M32R_IRQ_INT0); |
| 81 | #endif /* CONFIG_SMC91X */ |
| 82 | |
| 83 | /* MFT2 : system timer */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 84 | irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 85 | handle_level_irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 86 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
| 87 | disable_mappi3_irq(M32R_IRQ_MFT2); |
| 88 | |
| 89 | #ifdef CONFIG_SERIAL_M32R_SIO |
| 90 | /* SIO0_R : uart receive data */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 91 | irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 92 | handle_level_irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 93 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
| 94 | disable_mappi3_irq(M32R_IRQ_SIO0_R); |
| 95 | |
| 96 | /* SIO0_S : uart send data */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 97 | irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 98 | handle_level_irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 99 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
| 100 | disable_mappi3_irq(M32R_IRQ_SIO0_S); |
| 101 | /* SIO1_R : uart receive data */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 102 | irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 103 | handle_level_irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 104 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
| 105 | disable_mappi3_irq(M32R_IRQ_SIO1_R); |
| 106 | |
| 107 | /* SIO1_S : uart send data */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 108 | irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 109 | handle_level_irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 110 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
| 111 | disable_mappi3_irq(M32R_IRQ_SIO1_S); |
| 112 | #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ |
| 113 | |
| 114 | #if defined(CONFIG_USB) |
| 115 | /* INT1 : USB Host controller interrupt */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 116 | irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 117 | handle_level_irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 118 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; |
| 119 | disable_mappi3_irq(M32R_IRQ_INT1); |
| 120 | #endif /* CONFIG_USB */ |
| 121 | |
Hirokazu Takata | ad09d58 | 2005-11-28 13:44:00 -0800 | [diff] [blame] | 122 | /* CFC IREQ */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 123 | irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 124 | handle_level_irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 125 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; |
| 126 | disable_mappi3_irq(PLD_IRQ_CFIREQ); |
| 127 | |
| 128 | #if defined(CONFIG_M32R_CFC) |
Hirokazu Takata | ad09d58 | 2005-11-28 13:44:00 -0800 | [diff] [blame] | 129 | /* ICUCR41: CFC Insert & eject */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 130 | irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 131 | handle_level_irq); |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 132 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; |
| 133 | disable_mappi3_irq(PLD_IRQ_CFC_INSERT); |
| 134 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 135 | #endif /* CONFIG_M32R_CFC */ |
Hirokazu Takata | ad09d58 | 2005-11-28 13:44:00 -0800 | [diff] [blame] | 136 | |
| 137 | /* IDE IREQ */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 138 | irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, |
Thomas Gleixner | b82727e | 2011-01-19 18:39:27 +0100 | [diff] [blame] | 139 | handle_level_irq); |
Hirokazu Takata | ad09d58 | 2005-11-28 13:44:00 -0800 | [diff] [blame] | 140 | icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
| 141 | disable_mappi3_irq(PLD_IRQ_IDEIREQ); |
| 142 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 143 | } |
| 144 | |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 145 | #if defined(CONFIG_SMC91X) |
| 146 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 147 | #define LAN_IOSTART 0x300 |
| 148 | #define LAN_IOEND 0x320 |
| 149 | static struct resource smc91x_resources[] = { |
| 150 | [0] = { |
| 151 | .start = (LAN_IOSTART), |
| 152 | .end = (LAN_IOEND), |
| 153 | .flags = IORESOURCE_MEM, |
| 154 | }, |
| 155 | [1] = { |
| 156 | .start = M32R_IRQ_INT0, |
| 157 | .end = M32R_IRQ_INT0, |
| 158 | .flags = IORESOURCE_IRQ, |
| 159 | } |
| 160 | }; |
| 161 | |
| 162 | static struct platform_device smc91x_device = { |
| 163 | .name = "smc91x", |
| 164 | .id = 0, |
| 165 | .num_resources = ARRAY_SIZE(smc91x_resources), |
| 166 | .resource = smc91x_resources, |
| 167 | }; |
| 168 | |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 169 | #endif |
| 170 | |
| 171 | #if defined(CONFIG_FB_S1D13XXX) |
| 172 | |
| 173 | #include <video/s1d13xxxfb.h> |
| 174 | #include <asm/s1d13806.h> |
| 175 | |
| 176 | static struct s1d13xxxfb_pdata s1d13xxxfb_data = { |
| 177 | .initregs = s1d13xxxfb_initregs, |
| 178 | .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs), |
| 179 | .platform_init_video = NULL, |
| 180 | #ifdef CONFIG_PM |
| 181 | .platform_suspend_video = NULL, |
| 182 | .platform_resume_video = NULL, |
| 183 | #endif |
| 184 | }; |
| 185 | |
| 186 | static struct resource s1d13xxxfb_resources[] = { |
| 187 | [0] = { |
| 188 | .start = 0x1d600000UL, |
| 189 | .end = 0x1d73FFFFUL, |
| 190 | .flags = IORESOURCE_MEM, |
| 191 | }, |
| 192 | [1] = { |
| 193 | .start = 0x1d400000UL, |
| 194 | .end = 0x1d4001FFUL, |
| 195 | .flags = IORESOURCE_MEM, |
| 196 | } |
| 197 | }; |
| 198 | |
| 199 | static struct platform_device s1d13xxxfb_device = { |
| 200 | .name = S1D_DEVICENAME, |
| 201 | .id = 0, |
| 202 | .dev = { |
| 203 | .platform_data = &s1d13xxxfb_data, |
| 204 | }, |
| 205 | .num_resources = ARRAY_SIZE(s1d13xxxfb_resources), |
| 206 | .resource = s1d13xxxfb_resources, |
| 207 | }; |
| 208 | #endif |
| 209 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 210 | static int __init platform_init(void) |
| 211 | { |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 212 | #if defined(CONFIG_SMC91X) |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 213 | platform_device_register(&smc91x_device); |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 214 | #endif |
| 215 | #if defined(CONFIG_FB_S1D13XXX) |
| 216 | platform_device_register(&s1d13xxxfb_device); |
| 217 | #endif |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 218 | return 0; |
| 219 | } |
| 220 | arch_initcall(platform_init); |