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Thor Thayer71bcada2014-09-03 10:27:54 -05001/*
Thor Thayer143f4a52015-06-04 09:28:46 -05002 * Copyright Altera Corporation (C) 2014-2015. All rights reserved.
Thor Thayer71bcada2014-09-03 10:27:54 -05003 * Copyright 2011-2012 Calxeda, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 * Adapted from the highbank_mc_edac driver.
18 */
19
20#include <linux/ctype.h>
21#include <linux/edac.h>
22#include <linux/interrupt.h>
23#include <linux/kernel.h>
24#include <linux/mfd/syscon.h>
25#include <linux/of_platform.h>
26#include <linux/platform_device.h>
27#include <linux/regmap.h>
28#include <linux/types.h>
29#include <linux/uaccess.h>
30
Thor Thayer143f4a52015-06-04 09:28:46 -050031#include "altera_edac.h"
Thor Thayer71bcada2014-09-03 10:27:54 -050032#include "edac_core.h"
33#include "edac_module.h"
34
35#define EDAC_MOD_STR "altera_edac"
36#define EDAC_VERSION "1"
37
Thor Thayer143f4a52015-06-04 09:28:46 -050038static const struct altr_sdram_prv_data c5_data = {
39 .ecc_ctrl_offset = CV_CTLCFG_OFST,
40 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
41 .ecc_stat_offset = CV_DRAMSTS_OFST,
42 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
43 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
44 .ecc_saddr_offset = CV_ERRADDR_OFST,
45 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
46 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
47 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
48 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
49 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
50 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
51 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
52 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
53#ifdef CONFIG_EDAC_DEBUG
54 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
55 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
56 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
57#endif
Thor Thayer71bcada2014-09-03 10:27:54 -050058};
59
60static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
61{
62 struct mem_ctl_info *mci = dev_id;
63 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
Thor Thayer143f4a52015-06-04 09:28:46 -050064 const struct altr_sdram_prv_data *priv = drvdata->data;
Thor Thayer71bcada2014-09-03 10:27:54 -050065 u32 status, err_count, err_addr;
66
67 /* Error Address is shared by both SBE & DBE */
Thor Thayer143f4a52015-06-04 09:28:46 -050068 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, &err_addr);
Thor Thayer71bcada2014-09-03 10:27:54 -050069
Thor Thayer143f4a52015-06-04 09:28:46 -050070 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
Thor Thayer71bcada2014-09-03 10:27:54 -050071
Thor Thayer143f4a52015-06-04 09:28:46 -050072 if (status & priv->ecc_stat_ue_mask) {
73 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
74 &err_count);
Thor Thayer71bcada2014-09-03 10:27:54 -050075 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
76 err_count, err_addr);
77 }
Thor Thayer143f4a52015-06-04 09:28:46 -050078 if (status & priv->ecc_stat_ce_mask) {
79 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
80 &err_count);
Thor Thayer71bcada2014-09-03 10:27:54 -050081 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
82 err_addr >> PAGE_SHIFT,
83 err_addr & ~PAGE_MASK, 0,
84 0, 0, -1, mci->ctl_name, "");
85 }
86
Thor Thayer143f4a52015-06-04 09:28:46 -050087 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
88 priv->ecc_irq_clr_mask);
Thor Thayer71bcada2014-09-03 10:27:54 -050089
90 return IRQ_HANDLED;
91}
92
93#ifdef CONFIG_EDAC_DEBUG
94static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
95 const char __user *data,
96 size_t count, loff_t *ppos)
97{
98 struct mem_ctl_info *mci = file->private_data;
99 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
Thor Thayer143f4a52015-06-04 09:28:46 -0500100 const struct altr_sdram_prv_data *priv = drvdata->data;
Thor Thayer71bcada2014-09-03 10:27:54 -0500101 u32 *ptemp;
102 dma_addr_t dma_handle;
103 u32 reg, read_reg;
104
105 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
106 if (!ptemp) {
107 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
108 edac_printk(KERN_ERR, EDAC_MC,
109 "Inject: Buffer Allocation error\n");
110 return -ENOMEM;
111 }
112
Thor Thayer143f4a52015-06-04 09:28:46 -0500113 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
114 &read_reg);
115 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
Thor Thayer71bcada2014-09-03 10:27:54 -0500116
117 /* Error are injected by writing a word while the SBE or DBE
118 * bit in the CTLCFG register is set. Reading the word will
119 * trigger the SBE or DBE error and the corresponding IRQ.
120 */
121 if (count == 3) {
122 edac_printk(KERN_ALERT, EDAC_MC,
123 "Inject Double bit error\n");
Thor Thayer143f4a52015-06-04 09:28:46 -0500124 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
125 (read_reg | priv->ue_set_mask));
Thor Thayer71bcada2014-09-03 10:27:54 -0500126 } else {
127 edac_printk(KERN_ALERT, EDAC_MC,
128 "Inject Single bit error\n");
Thor Thayer143f4a52015-06-04 09:28:46 -0500129 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
130 (read_reg | priv->ce_set_mask));
Thor Thayer71bcada2014-09-03 10:27:54 -0500131 }
132
133 ptemp[0] = 0x5A5A5A5A;
134 ptemp[1] = 0xA5A5A5A5;
135
136 /* Clear the error injection bits */
Thor Thayer143f4a52015-06-04 09:28:46 -0500137 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
Thor Thayer71bcada2014-09-03 10:27:54 -0500138 /* Ensure it has been written out */
139 wmb();
140
141 /*
142 * To trigger the error, we need to read the data back
143 * (the data was written with errors above).
144 * The ACCESS_ONCE macros and printk are used to prevent the
145 * the compiler optimizing these reads out.
146 */
147 reg = ACCESS_ONCE(ptemp[0]);
148 read_reg = ACCESS_ONCE(ptemp[1]);
149 /* Force Read */
150 rmb();
151
152 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
153 reg, read_reg);
154
155 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
156
157 return count;
158}
159
160static const struct file_operations altr_sdr_mc_debug_inject_fops = {
161 .open = simple_open,
162 .write = altr_sdr_mc_err_inject_write,
163 .llseek = generic_file_llseek,
164};
165
166static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
167{
168 if (mci->debugfs)
169 debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
170 &altr_sdr_mc_debug_inject_fops);
171}
172#else
173static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
174{}
175#endif
176
Thor Thayerf9ae4872015-06-04 09:28:45 -0500177/* Get total memory size from Open Firmware DTB */
178static unsigned long get_total_mem(void)
Thor Thayer71bcada2014-09-03 10:27:54 -0500179{
Thor Thayerf9ae4872015-06-04 09:28:45 -0500180 struct device_node *np = NULL;
181 const unsigned int *reg, *reg_end;
182 int len, sw, aw;
183 unsigned long start, size, total_mem = 0;
Thor Thayer71bcada2014-09-03 10:27:54 -0500184
Thor Thayerf9ae4872015-06-04 09:28:45 -0500185 for_each_node_by_type(np, "memory") {
186 aw = of_n_addr_cells(np);
187 sw = of_n_size_cells(np);
188 reg = (const unsigned int *)of_get_property(np, "reg", &len);
189 reg_end = reg + (len / sizeof(u32));
Thor Thayer71bcada2014-09-03 10:27:54 -0500190
Thor Thayerf9ae4872015-06-04 09:28:45 -0500191 total_mem = 0;
192 do {
193 start = of_read_number(reg, aw);
194 reg += aw;
195 size = of_read_number(reg, sw);
196 reg += sw;
197 total_mem += size;
198 } while (reg < reg_end);
199 }
200 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
201 return total_mem;
Thor Thayer71bcada2014-09-03 10:27:54 -0500202}
203
Thor Thayer143f4a52015-06-04 09:28:46 -0500204static const struct of_device_id altr_sdram_ctrl_of_match[] = {
205 { .compatible = "altr,sdram-edac", .data = (void *)&c5_data},
206 {},
207};
208MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
209
Thor Thayer71bcada2014-09-03 10:27:54 -0500210static int altr_sdram_probe(struct platform_device *pdev)
211{
Thor Thayer143f4a52015-06-04 09:28:46 -0500212 const struct of_device_id *id;
Thor Thayer71bcada2014-09-03 10:27:54 -0500213 struct edac_mc_layer layers[2];
214 struct mem_ctl_info *mci;
215 struct altr_sdram_mc_data *drvdata;
Thor Thayer143f4a52015-06-04 09:28:46 -0500216 const struct altr_sdram_prv_data *priv;
Thor Thayer71bcada2014-09-03 10:27:54 -0500217 struct regmap *mc_vbase;
218 struct dimm_info *dimm;
Thor Thayer143f4a52015-06-04 09:28:46 -0500219 u32 read_reg;
220 int irq, res = 0;
221 unsigned long mem_size;
Thor Thayer71bcada2014-09-03 10:27:54 -0500222
Thor Thayer143f4a52015-06-04 09:28:46 -0500223 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
224 if (!id)
225 return -ENODEV;
226
Thor Thayer71bcada2014-09-03 10:27:54 -0500227 /* Grab the register range from the sdr controller in device tree */
228 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
229 "altr,sdr-syscon");
230 if (IS_ERR(mc_vbase)) {
231 edac_printk(KERN_ERR, EDAC_MC,
232 "regmap for altr,sdr-syscon lookup failed.\n");
233 return -ENODEV;
234 }
235
Thor Thayer143f4a52015-06-04 09:28:46 -0500236 /* Check specific dependencies for the module */
237 priv = of_match_node(altr_sdram_ctrl_of_match,
238 pdev->dev.of_node)->data;
239
240 /* Validate the SDRAM controller has ECC enabled */
241 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
242 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
Thor Thayer71bcada2014-09-03 10:27:54 -0500243 edac_printk(KERN_ERR, EDAC_MC,
244 "No ECC/ECC disabled [0x%08X]\n", read_reg);
245 return -ENODEV;
246 }
247
248 /* Grab memory size from device tree. */
Thor Thayerf9ae4872015-06-04 09:28:45 -0500249 mem_size = get_total_mem();
Thor Thayer71bcada2014-09-03 10:27:54 -0500250 if (!mem_size) {
Thor Thayerf9ae4872015-06-04 09:28:45 -0500251 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
Thor Thayer71bcada2014-09-03 10:27:54 -0500252 return -ENODEV;
253 }
254
Thor Thayer143f4a52015-06-04 09:28:46 -0500255 /* Ensure the SDRAM Interrupt is disabled */
256 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
257 priv->ecc_irq_en_mask, 0)) {
Thor Thayer71bcada2014-09-03 10:27:54 -0500258 edac_printk(KERN_ERR, EDAC_MC,
Thor Thayer143f4a52015-06-04 09:28:46 -0500259 "Error disabling SDRAM ECC IRQ\n");
260 return -ENODEV;
261 }
262
263 /* Toggle to clear the SDRAM Error count */
264 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
265 priv->ecc_cnt_rst_mask,
266 priv->ecc_cnt_rst_mask)) {
267 edac_printk(KERN_ERR, EDAC_MC,
268 "Error clearing SDRAM ECC count\n");
269 return -ENODEV;
270 }
271
272 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
273 priv->ecc_cnt_rst_mask, 0)) {
274 edac_printk(KERN_ERR, EDAC_MC,
275 "Error clearing SDRAM ECC count\n");
Thor Thayer71bcada2014-09-03 10:27:54 -0500276 return -ENODEV;
277 }
278
279 irq = platform_get_irq(pdev, 0);
280 if (irq < 0) {
281 edac_printk(KERN_ERR, EDAC_MC,
282 "No irq %d in DT\n", irq);
283 return -ENODEV;
284 }
285
286 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
287 layers[0].size = 1;
288 layers[0].is_virt_csrow = true;
289 layers[1].type = EDAC_MC_LAYER_CHANNEL;
290 layers[1].size = 1;
291 layers[1].is_virt_csrow = false;
292 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
293 sizeof(struct altr_sdram_mc_data));
294 if (!mci)
295 return -ENOMEM;
296
297 mci->pdev = &pdev->dev;
298 drvdata = mci->pvt_info;
299 drvdata->mc_vbase = mc_vbase;
Thor Thayer143f4a52015-06-04 09:28:46 -0500300 drvdata->data = priv;
Thor Thayer71bcada2014-09-03 10:27:54 -0500301 platform_set_drvdata(pdev, mci);
302
303 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
Thor Thayer143f4a52015-06-04 09:28:46 -0500304 edac_printk(KERN_ERR, EDAC_MC,
305 "Unable to get managed device resource\n");
Thor Thayer71bcada2014-09-03 10:27:54 -0500306 res = -ENOMEM;
307 goto free;
308 }
309
310 mci->mtype_cap = MEM_FLAG_DDR3;
311 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
312 mci->edac_cap = EDAC_FLAG_SECDED;
313 mci->mod_name = EDAC_MOD_STR;
314 mci->mod_ver = EDAC_VERSION;
315 mci->ctl_name = dev_name(&pdev->dev);
316 mci->scrub_mode = SCRUB_SW_SRC;
317 mci->dev_name = dev_name(&pdev->dev);
318
319 dimm = *mci->dimms;
320 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
321 dimm->grain = 8;
322 dimm->dtype = DEV_X8;
323 dimm->mtype = MEM_DDR3;
324 dimm->edac_mode = EDAC_SECDED;
325
326 res = edac_mc_add_mc(mci);
327 if (res < 0)
328 goto err;
329
330 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
331 0, dev_name(&pdev->dev), mci);
332 if (res < 0) {
333 edac_mc_printk(mci, KERN_ERR,
334 "Unable to request irq %d\n", irq);
335 res = -ENODEV;
336 goto err2;
337 }
338
Thor Thayer143f4a52015-06-04 09:28:46 -0500339 /* Infrastructure ready - enable the IRQ */
340 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
341 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
Thor Thayer71bcada2014-09-03 10:27:54 -0500342 edac_mc_printk(mci, KERN_ERR,
343 "Error enabling SDRAM ECC IRQ\n");
344 res = -ENODEV;
345 goto err2;
346 }
347
348 altr_sdr_mc_create_debugfs_nodes(mci);
349
350 devres_close_group(&pdev->dev, NULL);
351
352 return 0;
353
354err2:
355 edac_mc_del_mc(&pdev->dev);
356err:
357 devres_release_group(&pdev->dev, NULL);
358free:
359 edac_mc_free(mci);
360 edac_printk(KERN_ERR, EDAC_MC,
361 "EDAC Probe Failed; Error %d\n", res);
362
363 return res;
364}
365
366static int altr_sdram_remove(struct platform_device *pdev)
367{
368 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
369
370 edac_mc_del_mc(&pdev->dev);
371 edac_mc_free(mci);
372 platform_set_drvdata(pdev, NULL);
373
374 return 0;
375}
376
Thor Thayer71bcada2014-09-03 10:27:54 -0500377static struct platform_driver altr_sdram_edac_driver = {
378 .probe = altr_sdram_probe,
379 .remove = altr_sdram_remove,
380 .driver = {
381 .name = "altr_sdram_edac",
382 .of_match_table = altr_sdram_ctrl_of_match,
383 },
384};
385
386module_platform_driver(altr_sdram_edac_driver);
387
388MODULE_LICENSE("GPL v2");
389MODULE_AUTHOR("Thor Thayer");
390MODULE_DESCRIPTION("EDAC Driver for Altera SDRAM Controller");