ymohanma | be4fc04 | 2013-08-27 23:40:56 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Shobhit Kumar <shobhit.kumar@intel.com> |
| 25 | * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> |
| 26 | */ |
| 27 | |
| 28 | #include <linux/kernel.h> |
| 29 | #include "intel_drv.h" |
| 30 | #include "i915_drv.h" |
| 31 | #include "intel_dsi.h" |
| 32 | |
| 33 | #define DSI_HSS_PACKET_SIZE 4 |
| 34 | #define DSI_HSE_PACKET_SIZE 4 |
| 35 | #define DSI_HSA_PACKET_EXTRA_SIZE 6 |
| 36 | #define DSI_HBP_PACKET_EXTRA_SIZE 6 |
| 37 | #define DSI_HACTIVE_PACKET_EXTRA_SIZE 6 |
| 38 | #define DSI_HFP_PACKET_EXTRA_SIZE 6 |
| 39 | #define DSI_EOTP_PACKET_SIZE 4 |
| 40 | |
| 41 | struct dsi_mnp { |
| 42 | u32 dsi_pll_ctrl; |
| 43 | u32 dsi_pll_div; |
| 44 | }; |
| 45 | |
| 46 | static const u32 lfsr_converts[] = { |
| 47 | 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ |
| 48 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ |
| 49 | 106, 53, 282, 397, 354, 227, 113, 56, 284, 142, /* 81 - 90 */ |
| 50 | 71, 35 /* 91 - 92 */ |
| 51 | }; |
| 52 | |
Ville Syrjälä | a748214 | 2013-09-04 18:25:27 +0300 | [diff] [blame] | 53 | static u32 dsi_rr_formula(const struct drm_display_mode *mode, |
ymohanma | be4fc04 | 2013-08-27 23:40:56 +0300 | [diff] [blame] | 54 | int pixel_format, int video_mode_format, |
| 55 | int lane_count, bool eotp) |
| 56 | { |
| 57 | u32 bpp; |
| 58 | u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; |
| 59 | u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; |
| 60 | u32 bytes_per_line, bytes_per_frame; |
| 61 | u32 num_frames; |
| 62 | u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; |
| 63 | u32 dsi_bit_clock_hz; |
| 64 | u32 dsi_clk; |
| 65 | |
| 66 | switch (pixel_format) { |
| 67 | default: |
| 68 | case VID_MODE_FORMAT_RGB888: |
| 69 | case VID_MODE_FORMAT_RGB666_LOOSE: |
| 70 | bpp = 24; |
| 71 | break; |
| 72 | case VID_MODE_FORMAT_RGB666: |
| 73 | bpp = 18; |
| 74 | break; |
| 75 | case VID_MODE_FORMAT_RGB565: |
| 76 | bpp = 16; |
| 77 | break; |
| 78 | } |
| 79 | |
| 80 | hactive = mode->hdisplay; |
| 81 | vactive = mode->vdisplay; |
| 82 | hfp = mode->hsync_start - mode->hdisplay; |
| 83 | hsync = mode->hsync_end - mode->hsync_start; |
| 84 | hbp = mode->htotal - mode->hsync_end; |
| 85 | |
| 86 | vfp = mode->vsync_start - mode->vdisplay; |
| 87 | vsync = mode->vsync_end - mode->vsync_start; |
| 88 | vbp = mode->vtotal - mode->vsync_end; |
| 89 | |
| 90 | hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); |
| 91 | hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); |
| 92 | hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); |
| 93 | hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); |
| 94 | |
| 95 | bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes + |
| 96 | DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE + |
| 97 | hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE + |
| 98 | hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE + |
| 99 | hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE; |
| 100 | |
| 101 | /* |
| 102 | * XXX: Need to accurately calculate LP to HS transition timeout and add |
| 103 | * it to bytes_per_line/bytes_per_frame. |
| 104 | */ |
| 105 | |
| 106 | if (eotp && video_mode_format == VIDEO_MODE_BURST) |
| 107 | bytes_per_line += DSI_EOTP_PACKET_SIZE; |
| 108 | |
| 109 | bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + |
| 110 | vactive * bytes_per_line + vfp * bytes_per_line; |
| 111 | |
| 112 | if (eotp && |
| 113 | (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || |
| 114 | video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS)) |
| 115 | bytes_per_frame += DSI_EOTP_PACKET_SIZE; |
| 116 | |
| 117 | num_frames = drm_mode_vrefresh(mode); |
| 118 | bytes_per_x_frames = num_frames * bytes_per_frame; |
| 119 | |
| 120 | bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; |
| 121 | |
| 122 | /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ |
| 123 | dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8; |
| 124 | dsi_clk = dsi_bit_clock_hz / (1000 * 1000); |
| 125 | |
| 126 | if (eotp && video_mode_format == VIDEO_MODE_BURST) |
| 127 | dsi_clk *= 2; |
| 128 | |
| 129 | return dsi_clk; |
| 130 | } |
| 131 | |
| 132 | #ifdef MNP_FROM_TABLE |
| 133 | |
| 134 | struct dsi_clock_table { |
| 135 | u32 freq; |
| 136 | u8 m; |
| 137 | u8 p; |
| 138 | }; |
| 139 | |
| 140 | static const struct dsi_clock_table dsi_clk_tbl[] = { |
| 141 | {300, 72, 6}, {313, 75, 6}, {323, 78, 6}, {333, 80, 6}, |
| 142 | {343, 82, 6}, {353, 85, 6}, {363, 87, 6}, {373, 90, 6}, |
| 143 | {383, 92, 6}, {390, 78, 5}, {393, 79, 5}, {400, 80, 5}, |
| 144 | {401, 80, 5}, {402, 80, 5}, {403, 81, 5}, {404, 81, 5}, |
| 145 | {405, 81, 5}, {406, 81, 5}, {407, 81, 5}, {408, 82, 5}, |
| 146 | {409, 82, 5}, {410, 82, 5}, {411, 82, 5}, {412, 82, 5}, |
| 147 | {413, 83, 5}, {414, 83, 5}, {415, 83, 5}, {416, 83, 5}, |
| 148 | {417, 83, 5}, {418, 84, 5}, {419, 84, 5}, {420, 84, 5}, |
| 149 | {430, 86, 5}, {440, 88, 5}, {450, 90, 5}, {460, 92, 5}, |
| 150 | {470, 75, 4}, {480, 77, 4}, {490, 78, 4}, {500, 80, 4}, |
| 151 | {510, 82, 4}, {520, 83, 4}, {530, 85, 4}, {540, 86, 4}, |
| 152 | {550, 88, 4}, {560, 90, 4}, {570, 91, 4}, {580, 70, 3}, |
| 153 | {590, 71, 3}, {600, 72, 3}, {610, 73, 3}, {620, 74, 3}, |
| 154 | {630, 76, 3}, {640, 77, 3}, {650, 78, 3}, {660, 79, 3}, |
| 155 | {670, 80, 3}, {680, 82, 3}, {690, 83, 3}, {700, 84, 3}, |
| 156 | {710, 85, 3}, {720, 86, 3}, {730, 88, 3}, {740, 89, 3}, |
| 157 | {750, 90, 3}, {760, 91, 3}, {770, 92, 3}, {780, 62, 2}, |
| 158 | {790, 63, 2}, {800, 64, 2}, {880, 70, 2}, {900, 72, 2}, |
| 159 | {1000, 80, 2}, /* dsi clock frequency in Mhz*/ |
| 160 | }; |
| 161 | |
| 162 | static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) |
| 163 | { |
| 164 | unsigned int i; |
| 165 | u8 m; |
| 166 | u8 n; |
| 167 | u8 p; |
| 168 | u32 m_seed; |
| 169 | |
| 170 | if (dsi_clk < 300 || dsi_clk > 1000) |
| 171 | return -ECHRNG; |
| 172 | |
| 173 | for (i = 0; i <= ARRAY_SIZE(dsi_clk_tbl); i++) { |
| 174 | if (dsi_clk_tbl[i].freq > dsi_clk) |
| 175 | break; |
| 176 | } |
| 177 | |
| 178 | m = dsi_clk_tbl[i].m; |
| 179 | p = dsi_clk_tbl[i].p; |
| 180 | m_seed = lfsr_converts[m - 62]; |
| 181 | n = 1; |
| 182 | dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + p - 2); |
| 183 | dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT | |
| 184 | m_seed << DSI_PLL_M1_DIV_SHIFT; |
| 185 | |
| 186 | return 0; |
| 187 | } |
| 188 | |
| 189 | #else |
| 190 | |
| 191 | static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) |
| 192 | { |
| 193 | u32 m, n, p; |
| 194 | u32 ref_clk; |
| 195 | u32 error; |
| 196 | u32 tmp_error; |
| 197 | u32 target_dsi_clk; |
| 198 | u32 calc_dsi_clk; |
| 199 | u32 calc_m; |
| 200 | u32 calc_p; |
| 201 | u32 m_seed; |
| 202 | |
| 203 | if (dsi_clk < 300 || dsi_clk > 1150) { |
| 204 | DRM_ERROR("DSI CLK Out of Range\n"); |
| 205 | return -ECHRNG; |
| 206 | } |
| 207 | |
| 208 | ref_clk = 25000; |
| 209 | target_dsi_clk = dsi_clk * 1000; |
| 210 | error = 0xFFFFFFFF; |
| 211 | calc_m = 0; |
| 212 | calc_p = 0; |
| 213 | |
| 214 | for (m = 62; m <= 92; m++) { |
| 215 | for (p = 2; p <= 6; p++) { |
| 216 | |
| 217 | calc_dsi_clk = (m * ref_clk) / p; |
| 218 | if (calc_dsi_clk >= target_dsi_clk) { |
| 219 | tmp_error = calc_dsi_clk - target_dsi_clk; |
| 220 | if (tmp_error < error) { |
| 221 | error = tmp_error; |
| 222 | calc_m = m; |
| 223 | calc_p = p; |
| 224 | } |
| 225 | } |
| 226 | } |
| 227 | } |
| 228 | |
| 229 | m_seed = lfsr_converts[calc_m - 62]; |
| 230 | n = 1; |
| 231 | dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); |
| 232 | dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT | |
| 233 | m_seed << DSI_PLL_M1_DIV_SHIFT; |
| 234 | |
| 235 | return 0; |
| 236 | } |
| 237 | |
| 238 | #endif |
| 239 | |
| 240 | /* |
| 241 | * XXX: The muxing and gating is hard coded for now. Need to add support for |
| 242 | * sharing PLLs with two DSI outputs. |
| 243 | */ |
| 244 | static void vlv_configure_dsi_pll(struct intel_encoder *encoder) |
| 245 | { |
| 246 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 247 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | a748214 | 2013-09-04 18:25:27 +0300 | [diff] [blame] | 248 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
ymohanma | be4fc04 | 2013-08-27 23:40:56 +0300 | [diff] [blame] | 249 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 250 | int ret; |
| 251 | struct dsi_mnp dsi_mnp; |
| 252 | u32 dsi_clk; |
| 253 | |
| 254 | dsi_clk = dsi_rr_formula(mode, intel_dsi->pixel_format, |
| 255 | intel_dsi->video_mode_format, |
| 256 | intel_dsi->lane_count, !intel_dsi->eot_disable); |
| 257 | |
| 258 | ret = dsi_calc_mnp(dsi_clk, &dsi_mnp); |
| 259 | if (ret) { |
| 260 | DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); |
| 261 | return; |
| 262 | } |
| 263 | |
| 264 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; |
| 265 | |
| 266 | DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", |
| 267 | dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); |
| 268 | |
| 269 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); |
| 270 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); |
| 271 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); |
| 272 | } |
| 273 | |
| 274 | void vlv_enable_dsi_pll(struct intel_encoder *encoder) |
| 275 | { |
| 276 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 277 | u32 tmp; |
| 278 | |
| 279 | DRM_DEBUG_KMS("\n"); |
| 280 | |
| 281 | mutex_lock(&dev_priv->dpio_lock); |
| 282 | |
| 283 | vlv_configure_dsi_pll(encoder); |
| 284 | |
| 285 | /* wait at least 0.5 us after ungating before enabling VCO */ |
| 286 | usleep_range(1, 10); |
| 287 | |
| 288 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
| 289 | tmp |= DSI_PLL_VCO_EN; |
| 290 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); |
| 291 | |
| 292 | mutex_unlock(&dev_priv->dpio_lock); |
| 293 | |
| 294 | if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) { |
| 295 | DRM_ERROR("DSI PLL lock failed\n"); |
| 296 | return; |
| 297 | } |
| 298 | |
| 299 | DRM_DEBUG_KMS("DSI PLL locked\n"); |
| 300 | } |
| 301 | |
| 302 | void vlv_disable_dsi_pll(struct intel_encoder *encoder) |
| 303 | { |
| 304 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 305 | u32 tmp; |
| 306 | |
| 307 | DRM_DEBUG_KMS("\n"); |
| 308 | |
| 309 | mutex_lock(&dev_priv->dpio_lock); |
| 310 | |
| 311 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
| 312 | tmp &= ~DSI_PLL_VCO_EN; |
| 313 | tmp |= DSI_PLL_LDO_GATE; |
| 314 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); |
| 315 | |
| 316 | mutex_unlock(&dev_priv->dpio_lock); |
| 317 | } |