Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: |
| 28 | * Jerome Glisse <glisse@freedesktop.org> |
| 29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> |
| 30 | * Dave Airlie |
| 31 | */ |
| 32 | #include <linux/list.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 33 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 34 | #include <drm/drmP.h> |
| 35 | #include "radeon_drm.h" |
| 36 | #include "radeon.h" |
| 37 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 38 | |
| 39 | int radeon_ttm_init(struct radeon_device *rdev); |
| 40 | void radeon_ttm_fini(struct radeon_device *rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 41 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 42 | |
| 43 | /* |
| 44 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
| 45 | * function are calling it. |
| 46 | */ |
| 47 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 48 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 49 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 50 | struct radeon_bo *bo; |
| 51 | |
| 52 | bo = container_of(tbo, struct radeon_bo, tbo); |
| 53 | mutex_lock(&bo->rdev->gem.mutex); |
| 54 | list_del_init(&bo->list); |
| 55 | mutex_unlock(&bo->rdev->gem.mutex); |
| 56 | radeon_bo_clear_surface_reg(bo); |
| 57 | kfree(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 58 | } |
| 59 | |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 60 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
| 61 | { |
| 62 | if (bo->destroy == &radeon_ttm_bo_destroy) |
| 63 | return true; |
| 64 | return false; |
| 65 | } |
| 66 | |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 67 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
| 68 | { |
| 69 | u32 c = 0; |
| 70 | |
| 71 | rbo->placement.fpfn = 0; |
Jerome Glisse | c919b37 | 2010-08-10 17:41:31 -0400 | [diff] [blame] | 72 | rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 73 | rbo->placement.placement = rbo->placements; |
| 74 | rbo->placement.busy_placement = rbo->placements; |
| 75 | if (domain & RADEON_GEM_DOMAIN_VRAM) |
| 76 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | |
| 77 | TTM_PL_FLAG_VRAM; |
| 78 | if (domain & RADEON_GEM_DOMAIN_GTT) |
| 79 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
| 80 | if (domain & RADEON_GEM_DOMAIN_CPU) |
| 81 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
Jerome Glisse | 9fb03e6 | 2009-12-11 15:13:22 +0100 | [diff] [blame] | 82 | if (!c) |
| 83 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 84 | rbo->placement.num_placement = c; |
| 85 | rbo->placement.num_busy_placement = c; |
| 86 | } |
| 87 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 88 | int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, |
Alex Deucher | 268b251 | 2010-11-17 19:00:26 -0500 | [diff] [blame] | 89 | unsigned long size, int byte_align, bool kernel, u32 domain, |
| 90 | struct radeon_bo **bo_ptr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 91 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 92 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 93 | enum ttm_bo_type type; |
Alex Deucher | 268b251 | 2010-11-17 19:00:26 -0500 | [diff] [blame] | 94 | int page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 95 | int r; |
| 96 | |
| 97 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
| 98 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
| 99 | } |
| 100 | if (kernel) { |
| 101 | type = ttm_bo_type_kernel; |
| 102 | } else { |
| 103 | type = ttm_bo_type_device; |
| 104 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 105 | *bo_ptr = NULL; |
Michel Dänzer | 2b66b50 | 2010-11-09 11:50:05 +0100 | [diff] [blame] | 106 | |
| 107 | retry: |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 108 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
| 109 | if (bo == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 110 | return -ENOMEM; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 111 | bo->rdev = rdev; |
| 112 | bo->gobj = gobj; |
| 113 | bo->surface_reg = -1; |
| 114 | INIT_LIST_HEAD(&bo->list); |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 115 | radeon_ttm_placement_from_domain(bo, domain); |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 116 | /* Kernel allocation are uninterruptible */ |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 117 | mutex_lock(&rdev->vram_mutex); |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 118 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
Alex Deucher | 268b251 | 2010-11-17 19:00:26 -0500 | [diff] [blame] | 119 | &bo->placement, page_align, 0, !kernel, NULL, size, |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 120 | &radeon_ttm_bo_destroy); |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 121 | mutex_unlock(&rdev->vram_mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 122 | if (unlikely(r != 0)) { |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 123 | if (r != -ERESTARTSYS) { |
| 124 | if (domain == RADEON_GEM_DOMAIN_VRAM) { |
| 125 | domain |= RADEON_GEM_DOMAIN_GTT; |
| 126 | goto retry; |
| 127 | } |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 128 | dev_err(rdev->dev, |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 129 | "object_init failed for (%lu, 0x%08X)\n", |
| 130 | size, domain); |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 131 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 132 | return r; |
| 133 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 134 | *bo_ptr = bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 135 | if (gobj) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 136 | mutex_lock(&bo->rdev->gem.mutex); |
| 137 | list_add_tail(&bo->list, &rdev->gem.objects); |
| 138 | mutex_unlock(&bo->rdev->gem.mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 139 | } |
| 140 | return 0; |
| 141 | } |
| 142 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 143 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 144 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 145 | bool is_iomem; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 146 | int r; |
| 147 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 148 | if (bo->kptr) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 149 | if (ptr) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 150 | *ptr = bo->kptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 151 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 152 | return 0; |
| 153 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 154 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 155 | if (r) { |
| 156 | return r; |
| 157 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 158 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 159 | if (ptr) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 160 | *ptr = bo->kptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 161 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 162 | radeon_bo_check_tiling(bo, 0, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 163 | return 0; |
| 164 | } |
| 165 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 166 | void radeon_bo_kunmap(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 167 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 168 | if (bo->kptr == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 169 | return; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 170 | bo->kptr = NULL; |
| 171 | radeon_bo_check_tiling(bo, 0, 0); |
| 172 | ttm_bo_kunmap(&bo->kmap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 173 | } |
| 174 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 175 | void radeon_bo_unref(struct radeon_bo **bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 176 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 177 | struct ttm_buffer_object *tbo; |
Dave Airlie | f4b7fb9 | 2010-04-29 18:37:59 +1000 | [diff] [blame] | 178 | struct radeon_device *rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 179 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 180 | if ((*bo) == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 181 | return; |
Dave Airlie | f4b7fb9 | 2010-04-29 18:37:59 +1000 | [diff] [blame] | 182 | rdev = (*bo)->rdev; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 183 | tbo = &((*bo)->tbo); |
Dave Airlie | f4b7fb9 | 2010-04-29 18:37:59 +1000 | [diff] [blame] | 184 | mutex_lock(&rdev->vram_mutex); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 185 | ttm_bo_unref(&tbo); |
Dave Airlie | f4b7fb9 | 2010-04-29 18:37:59 +1000 | [diff] [blame] | 186 | mutex_unlock(&rdev->vram_mutex); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 187 | if (tbo == NULL) |
| 188 | *bo = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 189 | } |
| 190 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 191 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 192 | { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 193 | int r, i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 194 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 195 | if (bo->pin_count) { |
| 196 | bo->pin_count++; |
| 197 | if (gpu_addr) |
| 198 | *gpu_addr = radeon_bo_gpu_offset(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 199 | return 0; |
| 200 | } |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 201 | radeon_ttm_placement_from_domain(bo, domain); |
Michel Dänzer | 3ca82da | 2010-03-26 19:18:55 +0000 | [diff] [blame] | 202 | if (domain == RADEON_GEM_DOMAIN_VRAM) { |
| 203 | /* force to pin into visible video ram */ |
| 204 | bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; |
| 205 | } |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 206 | for (i = 0; i < bo->placement.num_placement; i++) |
| 207 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 208 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 209 | if (likely(r == 0)) { |
| 210 | bo->pin_count = 1; |
| 211 | if (gpu_addr != NULL) |
| 212 | *gpu_addr = radeon_bo_gpu_offset(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 213 | } |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 214 | if (unlikely(r != 0)) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 215 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 216 | return r; |
| 217 | } |
| 218 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 219 | int radeon_bo_unpin(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 220 | { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 221 | int r, i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 222 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 223 | if (!bo->pin_count) { |
| 224 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
| 225 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 226 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 227 | bo->pin_count--; |
| 228 | if (bo->pin_count) |
| 229 | return 0; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 230 | for (i = 0; i < bo->placement.num_placement; i++) |
| 231 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 232 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 233 | if (unlikely(r != 0)) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 234 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 235 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 236 | } |
| 237 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 238 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 239 | { |
Dave Airlie | d796d84 | 2010-01-25 13:08:08 +1000 | [diff] [blame] | 240 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
| 241 | if (0 && (rdev->flags & RADEON_IS_IGP)) { |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 242 | if (rdev->mc.igp_sideport_enabled == false) |
| 243 | /* Useless to evict on IGP chips */ |
| 244 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 245 | } |
| 246 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
| 247 | } |
| 248 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 249 | void radeon_bo_force_delete(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 250 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 251 | struct radeon_bo *bo, *n; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 252 | struct drm_gem_object *gobj; |
| 253 | |
| 254 | if (list_empty(&rdev->gem.objects)) { |
| 255 | return; |
| 256 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 257 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
| 258 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 259 | mutex_lock(&rdev->ddev->struct_mutex); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 260 | gobj = bo->gobj; |
| 261 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", |
| 262 | gobj, bo, (unsigned long)gobj->size, |
| 263 | *((unsigned long *)&gobj->refcount)); |
| 264 | mutex_lock(&bo->rdev->gem.mutex); |
| 265 | list_del_init(&bo->list); |
| 266 | mutex_unlock(&bo->rdev->gem.mutex); |
| 267 | radeon_bo_unref(&bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 268 | gobj->driver_private = NULL; |
| 269 | drm_gem_object_unreference(gobj); |
| 270 | mutex_unlock(&rdev->ddev->struct_mutex); |
| 271 | } |
| 272 | } |
| 273 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 274 | int radeon_bo_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 275 | { |
Jerome Glisse | a4d6827 | 2009-09-11 13:00:43 +0200 | [diff] [blame] | 276 | /* Add an MTRR for the VRAM */ |
| 277 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, |
| 278 | MTRR_TYPE_WRCOMB, 1); |
| 279 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
| 280 | rdev->mc.mc_vram_size >> 20, |
| 281 | (unsigned long long)rdev->mc.aper_size >> 20); |
| 282 | DRM_INFO("RAM width %dbits %cDR\n", |
| 283 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 284 | return radeon_ttm_init(rdev); |
| 285 | } |
| 286 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 287 | void radeon_bo_fini(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 288 | { |
| 289 | radeon_ttm_fini(rdev); |
| 290 | } |
| 291 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 292 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
| 293 | struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 294 | { |
| 295 | if (lobj->wdomain) { |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame^] | 296 | list_add(&lobj->tv.head, head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 297 | } else { |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame^] | 298 | list_add_tail(&lobj->tv.head, head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 299 | } |
| 300 | } |
| 301 | |
Jerome Glisse | 6cb8e1f | 2010-02-15 21:36:33 +0100 | [diff] [blame] | 302 | int radeon_bo_list_validate(struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 303 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 304 | struct radeon_bo_list *lobj; |
| 305 | struct radeon_bo *bo; |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 306 | u32 domain; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 307 | int r; |
| 308 | |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame^] | 309 | r = ttm_eu_reserve_buffers(head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 310 | if (unlikely(r != 0)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 311 | return r; |
| 312 | } |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame^] | 313 | list_for_each_entry(lobj, head, tv.head) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 314 | bo = lobj->bo; |
| 315 | if (!bo->pin_count) { |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 316 | domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; |
| 317 | |
| 318 | retry: |
| 319 | radeon_ttm_placement_from_domain(bo, domain); |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 320 | r = ttm_bo_validate(&bo->tbo, &bo->placement, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 321 | true, false, false); |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 322 | if (unlikely(r)) { |
| 323 | if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { |
| 324 | domain |= RADEON_GEM_DOMAIN_GTT; |
| 325 | goto retry; |
| 326 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 327 | return r; |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 328 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 329 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 330 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
| 331 | lobj->tiling_flags = bo->tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 332 | } |
| 333 | return 0; |
| 334 | } |
| 335 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 336 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 337 | struct vm_area_struct *vma) |
| 338 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 339 | return ttm_fbdev_mmap(vma, &bo->tbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 340 | } |
| 341 | |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 342 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 343 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 344 | struct radeon_device *rdev = bo->rdev; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 345 | struct radeon_surface_reg *reg; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 346 | struct radeon_bo *old_object; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 347 | int steal; |
| 348 | int i; |
| 349 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 350 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
| 351 | |
| 352 | if (!bo->tiling_flags) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 353 | return 0; |
| 354 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 355 | if (bo->surface_reg >= 0) { |
| 356 | reg = &rdev->surface_regs[bo->surface_reg]; |
| 357 | i = bo->surface_reg; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 358 | goto out; |
| 359 | } |
| 360 | |
| 361 | steal = -1; |
| 362 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
| 363 | |
| 364 | reg = &rdev->surface_regs[i]; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 365 | if (!reg->bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 366 | break; |
| 367 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 368 | old_object = reg->bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 369 | if (old_object->pin_count == 0) |
| 370 | steal = i; |
| 371 | } |
| 372 | |
| 373 | /* if we are all out */ |
| 374 | if (i == RADEON_GEM_MAX_SURFACES) { |
| 375 | if (steal == -1) |
| 376 | return -ENOMEM; |
| 377 | /* find someone with a surface reg and nuke their BO */ |
| 378 | reg = &rdev->surface_regs[steal]; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 379 | old_object = reg->bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 380 | /* blow away the mapping */ |
| 381 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 382 | ttm_bo_unmap_virtual(&old_object->tbo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 383 | old_object->surface_reg = -1; |
| 384 | i = steal; |
| 385 | } |
| 386 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 387 | bo->surface_reg = i; |
| 388 | reg->bo = bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 389 | |
| 390 | out: |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 391 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 392 | bo->tbo.mem.start << PAGE_SHIFT, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 393 | bo->tbo.num_pages << PAGE_SHIFT); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 394 | return 0; |
| 395 | } |
| 396 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 397 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 398 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 399 | struct radeon_device *rdev = bo->rdev; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 400 | struct radeon_surface_reg *reg; |
| 401 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 402 | if (bo->surface_reg == -1) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 403 | return; |
| 404 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 405 | reg = &rdev->surface_regs[bo->surface_reg]; |
| 406 | radeon_clear_surface_reg(rdev, bo->surface_reg); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 407 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 408 | reg->bo = NULL; |
| 409 | bo->surface_reg = -1; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 410 | } |
| 411 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 412 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
| 413 | uint32_t tiling_flags, uint32_t pitch) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 414 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 415 | int r; |
| 416 | |
| 417 | r = radeon_bo_reserve(bo, false); |
| 418 | if (unlikely(r != 0)) |
| 419 | return r; |
| 420 | bo->tiling_flags = tiling_flags; |
| 421 | bo->pitch = pitch; |
| 422 | radeon_bo_unreserve(bo); |
| 423 | return 0; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 424 | } |
| 425 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 426 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
| 427 | uint32_t *tiling_flags, |
| 428 | uint32_t *pitch) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 429 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 430 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 431 | if (tiling_flags) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 432 | *tiling_flags = bo->tiling_flags; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 433 | if (pitch) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 434 | *pitch = bo->pitch; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 435 | } |
| 436 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 437 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
| 438 | bool force_drop) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 439 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 440 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
| 441 | |
| 442 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 443 | return 0; |
| 444 | |
| 445 | if (force_drop) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 446 | radeon_bo_clear_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 447 | return 0; |
| 448 | } |
| 449 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 450 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 451 | if (!has_moved) |
| 452 | return 0; |
| 453 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 454 | if (bo->surface_reg >= 0) |
| 455 | radeon_bo_clear_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 456 | return 0; |
| 457 | } |
| 458 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 459 | if ((bo->surface_reg >= 0) && !has_moved) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 460 | return 0; |
| 461 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 462 | return radeon_bo_get_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 463 | } |
| 464 | |
| 465 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 466 | struct ttm_mem_reg *mem) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 467 | { |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 468 | struct radeon_bo *rbo; |
| 469 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
| 470 | return; |
| 471 | rbo = container_of(bo, struct radeon_bo, tbo); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 472 | radeon_bo_check_tiling(rbo, 0, 1); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 473 | } |
| 474 | |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 475 | int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 476 | { |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 477 | struct radeon_device *rdev; |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 478 | struct radeon_bo *rbo; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 479 | unsigned long offset, size; |
| 480 | int r; |
| 481 | |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 482 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 483 | return 0; |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 484 | rbo = container_of(bo, struct radeon_bo, tbo); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 485 | radeon_bo_check_tiling(rbo, 0, 0); |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 486 | rdev = rbo->rdev; |
| 487 | if (bo->mem.mem_type == TTM_PL_VRAM) { |
| 488 | size = bo->mem.num_pages << PAGE_SHIFT; |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 489 | offset = bo->mem.start << PAGE_SHIFT; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 490 | if ((offset + size) > rdev->mc.visible_vram_size) { |
| 491 | /* hurrah the memory is not visible ! */ |
| 492 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); |
| 493 | rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; |
| 494 | r = ttm_bo_validate(bo, &rbo->placement, false, true, false); |
| 495 | if (unlikely(r != 0)) |
| 496 | return r; |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 497 | offset = bo->mem.start << PAGE_SHIFT; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 498 | /* this should not happen */ |
| 499 | if ((offset + size) > rdev->mc.visible_vram_size) |
| 500 | return -EINVAL; |
| 501 | } |
| 502 | } |
| 503 | return 0; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 504 | } |