Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
Girish Mahadevan | 57e4771 | 2017-04-19 16:55:10 -0600 | [diff] [blame] | 13 | #include <dt-bindings/msm/msm-bus-ids.h> |
| 14 | |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 15 | &soc { |
| 16 | /* QUPv3 South instances */ |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 17 | qupv3_0: qcom,qupv3_0_geni_se@8c0000 { |
| 18 | compatible = "qcom,qupv3-geni-se"; |
| 19 | reg = <0x8c0000 0x6000>; |
| 20 | qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_1>; |
| 21 | qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| 22 | qcom,iommu-s1-bypass; |
| 23 | |
| 24 | iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { |
| 25 | compatible = "qcom,qupv3-geni-se-cb"; |
| 26 | iommus = <&apps_smmu 0x003 0x0>; |
| 27 | }; |
| 28 | }; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * HS UART instances. HS UART usecases can be supported on these |
| 32 | * instances only. |
| 33 | */ |
| 34 | qupv3_se6_4uart: qcom,qup_uart@0x898000 { |
| 35 | compatible = "qcom,msm-geni-serial-hs", "qcom,msm-geni-uart"; |
| 36 | reg = <0x898000 0x4000>; |
| 37 | reg-names = "se_phys"; |
| 38 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 39 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 40 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 41 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 42 | pinctrl-names = "default", "sleep"; |
| 43 | pinctrl-0 = <&qupv3_se6_4uart_active>; |
| 44 | pinctrl-1 = <&qupv3_se6_4uart_sleep>; |
Archana Sathyakumar | 00a36ab | 2017-03-03 14:38:26 -0700 | [diff] [blame] | 45 | interrupts-extended = <&pdc GIC_SPI 607 0>, |
Girish Mahadevan | 1d38bd3 | 2017-04-11 17:59:47 -0600 | [diff] [blame] | 46 | <&tlmm 48 0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 47 | status = "disabled"; |
Girish Mahadevan | 1d38bd3 | 2017-04-11 17:59:47 -0600 | [diff] [blame] | 48 | qcom,wakeup-byte = <0xFD>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 49 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | qupv3_se7_4uart: qcom,qup_uart@0x89c000 { |
| 53 | compatible = "qcom,msm-geni-serial-hs", "qcom,msm-geni-uart"; |
| 54 | reg = <0x89c000 0x4000>; |
| 55 | reg-names = "se_phys"; |
| 56 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 57 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 58 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 59 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 60 | pinctrl-names = "default", "sleep"; |
| 61 | pinctrl-0 = <&qupv3_se7_4uart_active>; |
| 62 | pinctrl-1 = <&qupv3_se7_4uart_sleep>; |
Archana Sathyakumar | 00a36ab | 2017-03-03 14:38:26 -0700 | [diff] [blame] | 63 | interrupts-extended = <&pdc GIC_SPI 608 0>, |
Girish Mahadevan | 1d38bd3 | 2017-04-11 17:59:47 -0600 | [diff] [blame] | 64 | <&tlmm 96 0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 65 | status = "disabled"; |
Girish Mahadevan | 1d38bd3 | 2017-04-11 17:59:47 -0600 | [diff] [blame] | 66 | qcom,wakeup-byte = <0xFD>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 67 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | /* I2C */ |
| 71 | qupv3_se0_i2c: i2c@880000 { |
| 72 | compatible = "qcom,i2c-geni"; |
| 73 | reg = <0x880000 0x4000>; |
| 74 | interrupts = <GIC_SPI 601 0>; |
| 75 | #address-cells = <1>; |
| 76 | #size-cells = <0>; |
| 77 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 78 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| 79 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 80 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 81 | pinctrl-names = "default", "sleep"; |
| 82 | pinctrl-0 = <&qupv3_se0_i2c_active>; |
| 83 | pinctrl-1 = <&qupv3_se0_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 84 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 85 | status = "disabled"; |
| 86 | }; |
| 87 | |
| 88 | qupv3_se1_i2c: i2c@884000 { |
| 89 | compatible = "qcom,i2c-geni"; |
| 90 | reg = <0x884000 0x4000>; |
| 91 | interrupts = <GIC_SPI 602 0>; |
| 92 | #address-cells = <1>; |
| 93 | #size-cells = <0>; |
| 94 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 95 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| 96 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 97 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 98 | pinctrl-names = "default", "sleep"; |
| 99 | pinctrl-0 = <&qupv3_se1_i2c_active>; |
| 100 | pinctrl-1 = <&qupv3_se1_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 101 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 102 | status = "disabled"; |
| 103 | }; |
| 104 | |
| 105 | qupv3_se2_i2c: i2c@888000 { |
| 106 | compatible = "qcom,i2c-geni"; |
| 107 | reg = <0x888000 0x4000>; |
| 108 | interrupts = <GIC_SPI 603 0>; |
| 109 | #address-cells = <1>; |
| 110 | #size-cells = <0>; |
| 111 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 112 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| 113 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 114 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 115 | pinctrl-names = "default", "sleep"; |
| 116 | pinctrl-0 = <&qupv3_se2_i2c_active>; |
| 117 | pinctrl-1 = <&qupv3_se2_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 118 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 119 | status = "disabled"; |
| 120 | }; |
| 121 | |
| 122 | qupv3_se3_i2c: i2c@88c000 { |
| 123 | compatible = "qcom,i2c-geni"; |
| 124 | reg = <0x88c000 0x4000>; |
| 125 | interrupts = <GIC_SPI 604 0>; |
| 126 | #address-cells = <1>; |
| 127 | #size-cells = <0>; |
| 128 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 129 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| 130 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 131 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 132 | pinctrl-names = "default", "sleep"; |
| 133 | pinctrl-0 = <&qupv3_se3_i2c_active>; |
| 134 | pinctrl-1 = <&qupv3_se3_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 135 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 136 | status = "disabled"; |
| 137 | }; |
| 138 | |
| 139 | qupv3_se4_i2c: i2c@890000 { |
| 140 | compatible = "qcom,i2c-geni"; |
| 141 | reg = <0x890000 0x4000>; |
| 142 | interrupts = <GIC_SPI 605 0>; |
| 143 | #address-cells = <1>; |
| 144 | #size-cells = <0>; |
| 145 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 146 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, |
| 147 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 148 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 149 | pinctrl-names = "default", "sleep"; |
| 150 | pinctrl-0 = <&qupv3_se4_i2c_active>; |
| 151 | pinctrl-1 = <&qupv3_se4_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 152 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 153 | status = "disabled"; |
| 154 | }; |
| 155 | |
| 156 | qupv3_se5_i2c: i2c@894000 { |
| 157 | compatible = "qcom,i2c-geni"; |
| 158 | reg = <0x894000 0x4000>; |
| 159 | interrupts = <GIC_SPI 606 0>; |
| 160 | #address-cells = <1>; |
| 161 | #size-cells = <0>; |
| 162 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 163 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, |
| 164 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 165 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 166 | pinctrl-names = "default", "sleep"; |
| 167 | pinctrl-0 = <&qupv3_se5_i2c_active>; |
| 168 | pinctrl-1 = <&qupv3_se5_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 169 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 170 | status = "disabled"; |
| 171 | }; |
| 172 | |
| 173 | qupv3_se6_i2c: i2c@898000 { |
| 174 | compatible = "qcom,i2c-geni"; |
| 175 | reg = <0x898000 0x4000>; |
| 176 | interrupts = <GIC_SPI 607 0>; |
| 177 | #address-cells = <1>; |
| 178 | #size-cells = <0>; |
| 179 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 180 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 181 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 182 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 183 | pinctrl-names = "default", "sleep"; |
| 184 | pinctrl-0 = <&qupv3_se6_i2c_active>; |
| 185 | pinctrl-1 = <&qupv3_se6_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 186 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 187 | status = "disabled"; |
| 188 | }; |
| 189 | |
| 190 | qupv3_se7_i2c: i2c@89c000 { |
| 191 | compatible = "qcom,i2c-geni"; |
| 192 | reg = <0x89c000 0x4000>; |
| 193 | interrupts = <GIC_SPI 608 0>; |
| 194 | #address-cells = <1>; |
| 195 | #size-cells = <0>; |
| 196 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 197 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 198 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 199 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 200 | pinctrl-names = "default", "sleep"; |
| 201 | pinctrl-0 = <&qupv3_se7_i2c_active>; |
| 202 | pinctrl-1 = <&qupv3_se7_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 203 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 204 | status = "disabled"; |
| 205 | }; |
| 206 | |
| 207 | /* SPI */ |
| 208 | qupv3_se0_spi: spi@880000 { |
| 209 | compatible = "qcom,spi-geni"; |
| 210 | #address-cells = <1>; |
| 211 | #size-cells = <0>; |
| 212 | reg = <0x880000 0x4000>; |
| 213 | reg-names = "se_phys"; |
| 214 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 215 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| 216 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 217 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 218 | pinctrl-names = "default", "sleep"; |
| 219 | pinctrl-0 = <&qupv3_se0_spi_active>; |
| 220 | pinctrl-1 = <&qupv3_se0_spi_sleep>; |
| 221 | interrupts = <GIC_SPI 601 0>; |
| 222 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 223 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 224 | dmas = <&gpi_dma0 0 0 1 64 0>, |
| 225 | <&gpi_dma0 1 0 1 64 0>; |
| 226 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 227 | status = "disabled"; |
| 228 | }; |
| 229 | |
| 230 | qupv3_se1_spi: spi@884000 { |
| 231 | compatible = "qcom,spi-geni"; |
| 232 | #address-cells = <1>; |
| 233 | #size-cells = <0>; |
| 234 | reg = <0x884000 0x4000>; |
| 235 | reg-names = "se_phys"; |
| 236 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 237 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| 238 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 239 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 240 | pinctrl-names = "default", "sleep"; |
| 241 | pinctrl-0 = <&qupv3_se1_spi_active>; |
| 242 | pinctrl-1 = <&qupv3_se1_spi_sleep>; |
| 243 | interrupts = <GIC_SPI 602 0>; |
| 244 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 245 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 246 | dmas = <&gpi_dma0 0 1 1 64 0>, |
| 247 | <&gpi_dma0 1 1 1 64 0>; |
| 248 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 249 | status = "disabled"; |
| 250 | }; |
| 251 | |
| 252 | qupv3_se2_spi: spi@888000 { |
| 253 | compatible = "qcom,spi-geni"; |
| 254 | #address-cells = <1>; |
| 255 | #size-cells = <0>; |
| 256 | reg = <0x888000 0x4000>; |
| 257 | reg-names = "se_phys"; |
| 258 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 259 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| 260 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 261 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 262 | pinctrl-names = "default", "sleep"; |
| 263 | pinctrl-0 = <&qupv3_se2_spi_active>; |
| 264 | pinctrl-1 = <&qupv3_se2_spi_sleep>; |
| 265 | interrupts = <GIC_SPI 603 0>; |
| 266 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 267 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 268 | dmas = <&gpi_dma0 0 2 1 64 0>, |
| 269 | <&gpi_dma0 1 2 1 64 0>; |
| 270 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 271 | status = "disabled"; |
| 272 | }; |
| 273 | |
| 274 | qupv3_se3_spi: spi@88c000 { |
| 275 | compatible = "qcom,spi-geni"; |
| 276 | #address-cells = <1>; |
| 277 | #size-cells = <0>; |
| 278 | reg = <0x88c000 0x4000>; |
| 279 | reg-names = "se_phys"; |
| 280 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 281 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| 282 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 283 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 284 | pinctrl-names = "default", "sleep"; |
| 285 | pinctrl-0 = <&qupv3_se3_spi_active>; |
| 286 | pinctrl-1 = <&qupv3_se3_spi_sleep>; |
| 287 | interrupts = <GIC_SPI 604 0>; |
| 288 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 289 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 290 | dmas = <&gpi_dma0 0 3 1 64 0>, |
| 291 | <&gpi_dma0 1 3 1 64 0>; |
| 292 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 293 | status = "disabled"; |
| 294 | }; |
| 295 | |
| 296 | qupv3_se4_spi: spi@890000 { |
| 297 | compatible = "qcom,spi-geni"; |
| 298 | #address-cells = <1>; |
| 299 | #size-cells = <0>; |
| 300 | reg = <0x890000 0x4000>; |
| 301 | reg-names = "se_phys"; |
| 302 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 303 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, |
| 304 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 305 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 306 | pinctrl-names = "default", "sleep"; |
| 307 | pinctrl-0 = <&qupv3_se4_spi_active>; |
| 308 | pinctrl-1 = <&qupv3_se4_spi_sleep>; |
| 309 | interrupts = <GIC_SPI 605 0>; |
| 310 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 311 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 312 | dmas = <&gpi_dma0 0 4 1 64 0>, |
| 313 | <&gpi_dma0 1 4 1 64 0>; |
| 314 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 315 | status = "disabled"; |
| 316 | }; |
| 317 | |
| 318 | qupv3_se5_spi: spi@894000 { |
| 319 | compatible = "qcom,spi-geni"; |
| 320 | #address-cells = <1>; |
| 321 | #size-cells = <0>; |
| 322 | reg = <0x894000 0x4000>; |
| 323 | reg-names = "se_phys"; |
| 324 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 325 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, |
| 326 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 327 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 328 | pinctrl-names = "default", "sleep"; |
| 329 | pinctrl-0 = <&qupv3_se5_spi_active>; |
| 330 | pinctrl-1 = <&qupv3_se5_spi_sleep>; |
| 331 | interrupts = <GIC_SPI 606 0>; |
| 332 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 333 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 334 | dmas = <&gpi_dma0 0 5 1 64 0>, |
| 335 | <&gpi_dma0 1 5 1 64 0>; |
| 336 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 337 | status = "disabled"; |
| 338 | }; |
| 339 | |
| 340 | qupv3_se6_spi: spi@898000 { |
| 341 | compatible = "qcom,spi-geni"; |
| 342 | #address-cells = <1>; |
| 343 | #size-cells = <0>; |
| 344 | reg = <0x898000 0x4000>; |
| 345 | reg-names = "se_phys"; |
| 346 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 347 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 348 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 349 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 350 | pinctrl-names = "default", "sleep"; |
| 351 | pinctrl-0 = <&qupv3_se6_spi_active>; |
| 352 | pinctrl-1 = <&qupv3_se6_spi_sleep>; |
| 353 | interrupts = <GIC_SPI 607 0>; |
| 354 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 355 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 356 | dmas = <&gpi_dma0 0 6 1 64 0>, |
| 357 | <&gpi_dma0 1 6 1 64 0>; |
| 358 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 359 | status = "disabled"; |
| 360 | }; |
| 361 | |
| 362 | qupv3_se7_spi: spi@89c000 { |
| 363 | compatible = "qcom,spi-geni"; |
| 364 | #address-cells = <1>; |
| 365 | #size-cells = <0>; |
| 366 | reg = <0x89c000 0x4000>; |
| 367 | reg-names = "se_phys"; |
| 368 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 369 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 370 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 371 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 372 | pinctrl-names = "default", "sleep"; |
| 373 | pinctrl-0 = <&qupv3_se7_spi_active>; |
| 374 | pinctrl-1 = <&qupv3_se7_spi_sleep>; |
| 375 | interrupts = <GIC_SPI 608 0>; |
| 376 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 377 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 378 | dmas = <&gpi_dma0 0 7 1 64 0>, |
| 379 | <&gpi_dma0 1 7 1 64 0>; |
| 380 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 381 | status = "disabled"; |
| 382 | }; |
| 383 | |
| 384 | /* QUPv3 North Instances */ |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 385 | qupv3_1: qcom,qupv3_1_geni_se@ac0000 { |
| 386 | compatible = "qcom,qupv3-geni-se"; |
| 387 | reg = <0xac0000 0x6000>; |
| 388 | qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_2>; |
| 389 | qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| 390 | qcom,iommu-s1-bypass; |
| 391 | |
| 392 | iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { |
| 393 | compatible = "qcom,qupv3-geni-se-cb"; |
| 394 | iommus = <&apps_smmu 0x6c3 0x0>; |
| 395 | }; |
| 396 | }; |
| 397 | |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 398 | /* 2-wire UART */ |
| 399 | |
| 400 | /* Debug UART Instance for CDP/MTP platform */ |
| 401 | qupv3_se9_2uart: qcom,qup_uart@0xa84000 { |
| 402 | compatible = "qcom,msm-geni-console", "qcom,msm-geni-uart"; |
| 403 | reg = <0xa84000 0x4000>; |
| 404 | reg-names = "se_phys"; |
| 405 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 406 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 407 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 408 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 409 | pinctrl-names = "default", "sleep"; |
| 410 | pinctrl-0 = <&qupv3_se9_2uart_active>; |
| 411 | pinctrl-1 = <&qupv3_se9_2uart_sleep>; |
| 412 | interrupts = <GIC_SPI 354 0>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 413 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 414 | status = "disabled"; |
| 415 | }; |
| 416 | |
| 417 | /* Debug UART Instance for RUMI platform */ |
| 418 | qupv3_se10_2uart: qcom,qup_uart@0xa88000 { |
| 419 | compatible = "qcom,msm-geni-console", "qcom,msm-geni-uart"; |
| 420 | reg = <0xa88000 0x4000>; |
| 421 | reg-names = "se_phys"; |
| 422 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 423 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 424 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 425 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 426 | pinctrl-names = "default", "sleep"; |
| 427 | pinctrl-0 = <&qupv3_se10_2uart_active>; |
| 428 | pinctrl-1 = <&qupv3_se10_2uart_sleep>; |
| 429 | interrupts = <GIC_SPI 355 0>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 430 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 431 | status = "disabled"; |
| 432 | }; |
| 433 | |
| 434 | /* I2C */ |
| 435 | qupv3_se8_i2c: i2c@a80000 { |
| 436 | compatible = "qcom,i2c-geni"; |
| 437 | reg = <0xa80000 0x4000>; |
| 438 | interrupts = <GIC_SPI 353 0>; |
| 439 | #address-cells = <1>; |
| 440 | #size-cells = <0>; |
| 441 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 442 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| 443 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 444 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 445 | pinctrl-names = "default", "sleep"; |
| 446 | pinctrl-0 = <&qupv3_se8_i2c_active>; |
| 447 | pinctrl-1 = <&qupv3_se8_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 448 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 449 | status = "disabled"; |
| 450 | }; |
| 451 | |
| 452 | qupv3_se9_i2c: i2c@a84000 { |
| 453 | compatible = "qcom,i2c-geni"; |
| 454 | reg = <0xa84000 0x4000>; |
| 455 | interrupts = <GIC_SPI 354 0>; |
| 456 | #address-cells = <1>; |
| 457 | #size-cells = <0>; |
| 458 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 459 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 460 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 461 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 462 | pinctrl-names = "default", "sleep"; |
| 463 | pinctrl-0 = <&qupv3_se9_i2c_active>; |
| 464 | pinctrl-1 = <&qupv3_se9_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 465 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 466 | status = "disabled"; |
| 467 | }; |
| 468 | |
| 469 | qupv3_se10_i2c: i2c@a88000 { |
| 470 | compatible = "qcom,i2c-geni"; |
| 471 | reg = <0xa88000 0x4000>; |
| 472 | interrupts = <GIC_SPI 355 0>; |
| 473 | #address-cells = <1>; |
| 474 | #size-cells = <0>; |
| 475 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 476 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 477 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 478 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 479 | pinctrl-names = "default", "sleep"; |
| 480 | pinctrl-0 = <&qupv3_se10_i2c_active>; |
| 481 | pinctrl-1 = <&qupv3_se10_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 482 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 483 | status = "disabled"; |
| 484 | }; |
| 485 | |
| 486 | qupv3_se11_i2c: i2c@a8c000 { |
| 487 | compatible = "qcom,i2c-geni"; |
| 488 | reg = <0xa8c000 0x4000>; |
| 489 | interrupts = <GIC_SPI 356 0>; |
| 490 | #address-cells = <1>; |
| 491 | #size-cells = <0>; |
| 492 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 493 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| 494 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 495 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 496 | pinctrl-names = "default", "sleep"; |
| 497 | pinctrl-0 = <&qupv3_se11_i2c_active>; |
| 498 | pinctrl-1 = <&qupv3_se11_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 499 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 500 | status = "disabled"; |
| 501 | }; |
| 502 | |
| 503 | qupv3_se12_i2c: i2c@a90000 { |
| 504 | compatible = "qcom,i2c-geni"; |
| 505 | reg = <0xa90000 0x4000>; |
| 506 | interrupts = <GIC_SPI 357 0>; |
| 507 | #address-cells = <1>; |
| 508 | #size-cells = <0>; |
| 509 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 510 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| 511 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 512 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 513 | pinctrl-names = "default", "sleep"; |
| 514 | pinctrl-0 = <&qupv3_se12_i2c_active>; |
| 515 | pinctrl-1 = <&qupv3_se12_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 516 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 517 | status = "disabled"; |
| 518 | }; |
| 519 | |
| 520 | qupv3_se13_i2c: i2c@a94000 { |
| 521 | compatible = "qcom,i2c-geni"; |
| 522 | reg = <0xa94000 0x4000>; |
| 523 | interrupts = <GIC_SPI 358 0>; |
| 524 | #address-cells = <1>; |
| 525 | #size-cells = <0>; |
| 526 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 527 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| 528 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 529 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 530 | pinctrl-names = "default", "sleep"; |
| 531 | pinctrl-0 = <&qupv3_se13_i2c_active>; |
| 532 | pinctrl-1 = <&qupv3_se13_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 533 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 534 | status = "disabled"; |
| 535 | }; |
| 536 | |
| 537 | qupv3_se14_i2c: i2c@a98000 { |
| 538 | compatible = "qcom,i2c-geni"; |
| 539 | reg = <0xa98000 0x4000>; |
| 540 | interrupts = <GIC_SPI 359 0>; |
| 541 | #address-cells = <1>; |
| 542 | #size-cells = <0>; |
| 543 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 544 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>, |
| 545 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 546 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 547 | pinctrl-names = "default", "sleep"; |
| 548 | pinctrl-0 = <&qupv3_se14_i2c_active>; |
| 549 | pinctrl-1 = <&qupv3_se14_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 550 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 551 | status = "disabled"; |
| 552 | }; |
| 553 | |
| 554 | qupv3_se15_i2c: i2c@a9c000 { |
| 555 | compatible = "qcom,i2c-geni"; |
| 556 | reg = <0xa9c000 0x4000>; |
| 557 | interrupts = <GIC_SPI 360 0>; |
| 558 | #address-cells = <1>; |
| 559 | #size-cells = <0>; |
| 560 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 561 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S7_CLK>, |
| 562 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 563 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 564 | pinctrl-names = "default", "sleep"; |
| 565 | pinctrl-0 = <&qupv3_se15_i2c_active>; |
| 566 | pinctrl-1 = <&qupv3_se15_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 567 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 568 | status = "disabled"; |
| 569 | }; |
| 570 | |
| 571 | /* SPI */ |
| 572 | qupv3_se8_spi: spi@a80000 { |
| 573 | compatible = "qcom,spi-geni"; |
| 574 | #address-cells = <1>; |
| 575 | #size-cells = <0>; |
| 576 | reg = <0xa80000 0x4000>; |
| 577 | reg-names = "se_phys"; |
| 578 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 579 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| 580 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 581 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 582 | pinctrl-names = "default", "sleep"; |
| 583 | pinctrl-0 = <&qupv3_se8_spi_active>; |
| 584 | pinctrl-1 = <&qupv3_se8_spi_sleep>; |
| 585 | interrupts = <GIC_SPI 353 0>; |
| 586 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 587 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 588 | dmas = <&gpi_dma1 0 0 1 64 0>, |
| 589 | <&gpi_dma1 1 0 1 64 0>; |
| 590 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 591 | status = "disabled"; |
| 592 | }; |
| 593 | |
| 594 | qupv3_se9_spi: spi@a84000 { |
| 595 | compatible = "qcom,spi-geni"; |
| 596 | #address-cells = <1>; |
| 597 | #size-cells = <0>; |
| 598 | reg = <0xa84000 0x4000>; |
| 599 | reg-names = "se_phys"; |
| 600 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 601 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 602 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 603 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 604 | pinctrl-names = "default", "sleep"; |
| 605 | pinctrl-0 = <&qupv3_se9_spi_active>; |
| 606 | pinctrl-1 = <&qupv3_se9_spi_sleep>; |
| 607 | interrupts = <GIC_SPI 354 0>; |
| 608 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 609 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 610 | dmas = <&gpi_dma1 0 1 1 64 0>, |
| 611 | <&gpi_dma1 1 1 1 64 0>; |
| 612 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 613 | status = "disabled"; |
| 614 | }; |
| 615 | |
| 616 | qupv3_se10_spi: spi@a88000 { |
| 617 | compatible = "qcom,spi-geni"; |
| 618 | #address-cells = <1>; |
| 619 | #size-cells = <0>; |
| 620 | reg = <0xa88000 0x4000>; |
| 621 | reg-names = "se_phys"; |
| 622 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 623 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 624 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 625 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 626 | pinctrl-names = "default", "sleep"; |
| 627 | pinctrl-0 = <&qupv3_se10_spi_active>; |
| 628 | pinctrl-1 = <&qupv3_se10_spi_sleep>; |
| 629 | interrupts = <GIC_SPI 355 0>; |
| 630 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 631 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 632 | dmas = <&gpi_dma1 0 2 1 64 0>, |
| 633 | <&gpi_dma1 1 2 1 64 0>; |
| 634 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 635 | status = "disabled"; |
| 636 | }; |
| 637 | |
| 638 | qupv3_se11_spi: spi@a8c000 { |
| 639 | compatible = "qcom,spi-geni"; |
| 640 | #address-cells = <1>; |
| 641 | #size-cells = <0>; |
| 642 | reg = <0xa8c000 0x4000>; |
| 643 | reg-names = "se_phys"; |
| 644 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 645 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| 646 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 647 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 648 | pinctrl-names = "default", "sleep"; |
| 649 | pinctrl-0 = <&qupv3_se11_spi_active>; |
| 650 | pinctrl-1 = <&qupv3_se11_spi_sleep>; |
| 651 | interrupts = <GIC_SPI 356 0>; |
| 652 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 653 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 654 | dmas = <&gpi_dma1 0 3 1 64 0>, |
| 655 | <&gpi_dma1 1 3 1 64 0>; |
| 656 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 657 | status = "disabled"; |
| 658 | }; |
| 659 | |
| 660 | qupv3_se12_spi: spi@a90000 { |
| 661 | compatible = "qcom,spi-geni"; |
| 662 | #address-cells = <1>; |
| 663 | #size-cells = <0>; |
| 664 | reg = <0xa90000 0x4000>; |
| 665 | reg-names = "se_phys"; |
| 666 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 667 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| 668 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 669 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 670 | pinctrl-names = "default", "sleep"; |
| 671 | pinctrl-0 = <&qupv3_se12_spi_active>; |
| 672 | pinctrl-1 = <&qupv3_se12_spi_sleep>; |
| 673 | interrupts = <GIC_SPI 357 0>; |
| 674 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 675 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 676 | dmas = <&gpi_dma1 0 4 1 64 0>, |
| 677 | <&gpi_dma1 1 4 1 64 0>; |
| 678 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 679 | status = "disabled"; |
| 680 | }; |
| 681 | |
| 682 | qupv3_se13_spi: spi@a94000 { |
| 683 | compatible = "qcom,spi-geni"; |
| 684 | #address-cells = <1>; |
| 685 | #size-cells = <0>; |
| 686 | reg = <0xa94000 0x4000>; |
| 687 | reg-names = "se_phys"; |
| 688 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 689 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| 690 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 691 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 692 | pinctrl-names = "default", "sleep"; |
| 693 | pinctrl-0 = <&qupv3_se13_spi_active>; |
| 694 | pinctrl-1 = <&qupv3_se13_spi_sleep>; |
| 695 | interrupts = <GIC_SPI 358 0>; |
| 696 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 697 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 698 | dmas = <&gpi_dma1 0 5 1 64 0>, |
| 699 | <&gpi_dma1 1 5 1 64 0>; |
| 700 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 701 | status = "disabled"; |
| 702 | }; |
| 703 | |
| 704 | qupv3_se14_spi: spi@a98000 { |
| 705 | compatible = "qcom,spi-geni"; |
| 706 | #address-cells = <1>; |
| 707 | #size-cells = <0>; |
| 708 | reg = <0xa98000 0x4000>; |
| 709 | reg-names = "se_phys"; |
| 710 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 711 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>, |
| 712 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 713 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 714 | pinctrl-names = "default", "sleep"; |
| 715 | pinctrl-0 = <&qupv3_se14_spi_active>; |
| 716 | pinctrl-1 = <&qupv3_se14_spi_sleep>; |
| 717 | interrupts = <GIC_SPI 359 0>; |
| 718 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 719 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 720 | dmas = <&gpi_dma1 0 6 1 64 0>, |
| 721 | <&gpi_dma1 1 6 1 64 0>; |
| 722 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 723 | status = "disabled"; |
| 724 | }; |
| 725 | |
| 726 | qupv3_se15_spi: spi@a9c000 { |
| 727 | compatible = "qcom,spi-geni"; |
| 728 | #address-cells = <1>; |
| 729 | #size-cells = <0>; |
| 730 | reg = <0xa9c000 0x4000>; |
| 731 | reg-names = "se_phys"; |
| 732 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 733 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S7_CLK>, |
| 734 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 735 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 736 | pinctrl-names = "default", "sleep"; |
| 737 | pinctrl-0 = <&qupv3_se15_spi_active>; |
| 738 | pinctrl-1 = <&qupv3_se15_spi_sleep>; |
| 739 | interrupts = <GIC_SPI 360 0>; |
| 740 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 741 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 742 | dmas = <&gpi_dma1 0 7 1 64 0>, |
| 743 | <&gpi_dma1 1 7 1 64 0>; |
| 744 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 745 | status = "disabled"; |
| 746 | }; |
| 747 | }; |