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Sascha Hauera1365272005-05-05 15:14:15 -07001/*
2 * dm9000 Ethernet
3 */
4
5#ifndef _DM9000X_H_
6#define _DM9000X_H_
7
8#define DM9000_ID 0x90000A46
9
10/* although the registers are 16 bit, they are 32-bit aligned.
11 */
12
13#define DM9000_NCR 0x00
14#define DM9000_NSR 0x01
15#define DM9000_TCR 0x02
16#define DM9000_TSR1 0x03
17#define DM9000_TSR2 0x04
18#define DM9000_RCR 0x05
19#define DM9000_RSR 0x06
20#define DM9000_ROCR 0x07
21#define DM9000_BPTR 0x08
22#define DM9000_FCTR 0x09
23#define DM9000_FCR 0x0A
24#define DM9000_EPCR 0x0B
25#define DM9000_EPAR 0x0C
26#define DM9000_EPDRL 0x0D
27#define DM9000_EPDRH 0x0E
28#define DM9000_WCR 0x0F
29
30#define DM9000_PAR 0x10
31#define DM9000_MAR 0x16
32
33#define DM9000_GPCR 0x1e
34#define DM9000_GPR 0x1f
35#define DM9000_TRPAL 0x22
36#define DM9000_TRPAH 0x23
37#define DM9000_RWPAL 0x24
38#define DM9000_RWPAH 0x25
39
40#define DM9000_VIDL 0x28
41#define DM9000_VIDH 0x29
42#define DM9000_PIDL 0x2A
43#define DM9000_PIDH 0x2B
44
45#define DM9000_CHIPR 0x2C
46#define DM9000_SMCR 0x2F
47
Yeasah Pell5dcc60b2009-07-06 18:12:33 -070048#define DM9000_ETXCSR 0x30
49#define DM9000_TCCR 0x31
50#define DM9000_RCSR 0x32
51
Ben Dooks6d406b32008-06-24 22:15:59 +010052#define CHIPR_DM9000A 0x19
Ben Dooks62e20a62009-10-24 06:53:07 -070053#define CHIPR_DM9000B 0x1A
Ben Dooks6d406b32008-06-24 22:15:59 +010054
Sascha Hauera1365272005-05-05 15:14:15 -070055#define DM9000_MRCMDX 0xF0
56#define DM9000_MRCMD 0xF2
57#define DM9000_MRRL 0xF4
58#define DM9000_MRRH 0xF5
59#define DM9000_MWCMDX 0xF6
60#define DM9000_MWCMD 0xF8
61#define DM9000_MWRL 0xFA
62#define DM9000_MWRH 0xFB
63#define DM9000_TXPLL 0xFC
64#define DM9000_TXPLH 0xFD
65#define DM9000_ISR 0xFE
66#define DM9000_IMR 0xFF
67
68#define NCR_EXT_PHY (1<<7)
69#define NCR_WAKEEN (1<<6)
70#define NCR_FCOL (1<<4)
71#define NCR_FDX (1<<3)
72#define NCR_LBK (3<<1)
73#define NCR_RST (1<<0)
74
75#define NSR_SPEED (1<<7)
76#define NSR_LINKST (1<<6)
77#define NSR_WAKEST (1<<5)
78#define NSR_TX2END (1<<3)
79#define NSR_TX1END (1<<2)
80#define NSR_RXOV (1<<1)
81
82#define TCR_TJDIS (1<<6)
83#define TCR_EXCECM (1<<5)
84#define TCR_PAD_DIS2 (1<<4)
85#define TCR_CRC_DIS2 (1<<3)
86#define TCR_PAD_DIS1 (1<<2)
87#define TCR_CRC_DIS1 (1<<1)
88#define TCR_TXREQ (1<<0)
89
90#define TSR_TJTO (1<<7)
91#define TSR_LC (1<<6)
92#define TSR_NC (1<<5)
93#define TSR_LCOL (1<<4)
94#define TSR_COL (1<<3)
95#define TSR_EC (1<<2)
96
97#define RCR_WTDIS (1<<6)
98#define RCR_DIS_LONG (1<<5)
99#define RCR_DIS_CRC (1<<4)
100#define RCR_ALL (1<<3)
101#define RCR_RUNT (1<<2)
102#define RCR_PRMSC (1<<1)
103#define RCR_RXEN (1<<0)
104
105#define RSR_RF (1<<7)
106#define RSR_MF (1<<6)
107#define RSR_LCS (1<<5)
108#define RSR_RWTO (1<<4)
109#define RSR_PLE (1<<3)
110#define RSR_AE (1<<2)
111#define RSR_CE (1<<1)
112#define RSR_FOE (1<<0)
113
Ben Dooksc029f442009-11-10 07:22:24 +0000114#define WCR_LINKEN (1 << 5)
115#define WCR_SAMPLEEN (1 << 4)
116#define WCR_MAGICEN (1 << 3)
117#define WCR_LINKST (1 << 2)
118#define WCR_SAMPLEST (1 << 1)
119#define WCR_MAGICST (1 << 0)
120
Sascha Hauera1365272005-05-05 15:14:15 -0700121#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
122#define FCTR_LWOT(ot) ( ot & 0xf )
123
124#define IMR_PAR (1<<7)
125#define IMR_ROOM (1<<3)
126#define IMR_ROM (1<<2)
127#define IMR_PTM (1<<1)
128#define IMR_PRM (1<<0)
129
130#define ISR_ROOS (1<<3)
131#define ISR_ROS (1<<2)
132#define ISR_PTS (1<<1)
133#define ISR_PRS (1<<0)
134#define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
135
136#define EPCR_REEP (1<<5)
137#define EPCR_WEP (1<<4)
138#define EPCR_EPOS (1<<3)
139#define EPCR_ERPRR (1<<2)
140#define EPCR_ERPRW (1<<1)
141#define EPCR_ERRE (1<<0)
142
143#define GPCR_GEP_CNTL (1<<0)
144
Yeasah Pell5dcc60b2009-07-06 18:12:33 -0700145#define TCCR_IP (1<<0)
146#define TCCR_TCP (1<<1)
147#define TCCR_UDP (1<<2)
148
149#define RCSR_UDP_BAD (1<<7)
150#define RCSR_TCP_BAD (1<<6)
151#define RCSR_IP_BAD (1<<5)
152#define RCSR_UDP (1<<4)
153#define RCSR_TCP (1<<3)
154#define RCSR_IP (1<<2)
155#define RCSR_CSUM (1<<1)
156#define RCSR_DISCARD (1<<0)
157
Sascha Hauera1365272005-05-05 15:14:15 -0700158#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
Yeasah Pell5dcc60b2009-07-06 18:12:33 -0700159#define DM9000_PKT_ERR 0x02
Sascha Hauera1365272005-05-05 15:14:15 -0700160#define DM9000_PKT_MAX 1536 /* Received packet max size */
161
Ben Dooks6d406b32008-06-24 22:15:59 +0100162/* DM9000A / DM9000B definitions */
163
164#define IMR_LNKCHNG (1<<5)
165#define IMR_UNDERRUN (1<<4)
166
167#define ISR_LNKCHNG (1<<5)
168#define ISR_UNDERRUN (1<<4)
169
Sascha Hauera1365272005-05-05 15:14:15 -0700170#endif /* _DM9000X_H_ */
171