Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 15cbbc44cc4abaaebc37caf0ec9410a3f83d1deb / . / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
blob: 5ffeda25bf14e1f86b32d952994eff8dfff09040 [file] [log] [blame]
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_phy.h"
19#include "ar9003_eeprom.h"
20
21#define COMP_HDR_LEN 4
22#define COMP_CKSUM_LEN 2
23
24#define AR_CH0_TOP (0x00016288)
Vasanthakumar Thiagarajan52a0e242010-11-10 05:03:11 -0800[diff] [blame]25#define AR_CH0_TOP_XPABIASLVL (0x300)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]26#define AR_CH0_TOP_XPABIASLVL_S (8)
27
28#define AR_CH0_THERM (0x00016290)
Vasanthakumar Thiagarajan52a0e242010-11-10 05:03:11 -0800[diff] [blame]29#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
30#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
31#define AR_CH0_THERM_XPASHORT2GND 0x4
32#define AR_CH0_THERM_XPASHORT2GND_S 2
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]33
34#define AR_SWITCH_TABLE_COM_ALL (0xffff)
35#define AR_SWITCH_TABLE_COM_ALL_S (0)
36
37#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
38#define AR_SWITCH_TABLE_COM2_ALL_S (0)
39
40#define AR_SWITCH_TABLE_ALL (0xfff)
41#define AR_SWITCH_TABLE_ALL_S (0)
42
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]43#define LE16(x) __constant_cpu_to_le16(x)
44#define LE32(x) __constant_cpu_to_le32(x)
45
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]46/* Local defines to distinguish between extension and control CTL's */
47#define EXT_ADDITIVE (0x8000)
48#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
49#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
50#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
51#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
52#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
53#define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
54#define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
55#define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
56
57#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
58#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
59
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]60static int ar9003_hw_power_interpolate(int32_t x,
61 int32_t *px, int32_t *py, u_int16_t np);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]62static const struct ar9300_eeprom ar9300_default = {
63 .eepromVersion = 2,
64 .templateVersion = 2,
65 .macAddr = {1, 2, 3, 4, 5, 6},
66 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
67 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
68 .baseEepHeader = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]69 .regDmn = { LE16(0), LE16(0x1f) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]70 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
71 .opCapFlags = {
72 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
73 .eepMisc = 0,
74 },
75 .rfSilent = 0,
76 .blueToothOptions = 0,
77 .deviceCap = 0,
78 .deviceType = 5, /* takes lower byte in eeprom location */
79 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
80 .params_for_tuning_caps = {0, 0},
81 .featureEnable = 0x0c,
82 /*
83 * bit0 - enable tx temp comp - disabled
84 * bit1 - enable tx volt comp - disabled
85 * bit2 - enable fastClock - enabled
86 * bit3 - enable doubling - enabled
87 * bit4 - enable internal regulator - disabled
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]88 * bit5 - enable pa predistortion - disabled
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]89 */
90 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
91 .eepromWriteEnableGpio = 3,
92 .wlanDisableGpio = 0,
93 .wlanLedGpio = 8,
94 .rxBandSelectGpio = 0xff,
95 .txrxgain = 0,
96 .swreg = 0,
97 },
98 .modalHeader2G = {
99 /* ar9300_modal_eep_header 2g */
100 /* 4 idle,t1,t2,b(4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]101 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]102 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]103 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]104
105 /*
106 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
107 * rx1, rx12, b (2 bits each)
108 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]109 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]110
111 /*
112 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
113 * for ar9280 (0xa20c/b20c 5:0)
114 */
115 .xatten1DB = {0, 0, 0},
116
117 /*
118 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
119 * for ar9280 (0xa20c/b20c 16:12
120 */
121 .xatten1Margin = {0, 0, 0},
122 .tempSlope = 36,
123 .voltSlope = 0,
124
125 /*
126 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
127 * channels in usual fbin coding format
128 */
129 .spurChans = {0, 0, 0, 0, 0},
130
131 /*
132 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
133 * if the register is per chain
134 */
135 .noiseFloorThreshCh = {-1, 0, 0},
136 .ob = {1, 1, 1},/* 3 chain */
137 .db_stage2 = {1, 1, 1}, /* 3 chain */
138 .db_stage3 = {0, 0, 0},
139 .db_stage4 = {0, 0, 0},
140 .xpaBiasLvl = 0,
141 .txFrameToDataStart = 0x0e,
142 .txFrameToPaOn = 0x0e,
143 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
144 .antennaGain = 0,
145 .switchSettling = 0x2c,
146 .adcDesiredSize = -30,
147 .txEndToXpaOff = 0,
148 .txEndToRxOn = 0x2,
149 .txFrameToXpaOn = 0xe,
150 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]151 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
152 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]153 .futureModal = {
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]155 },
156 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]157 .base_ext1 = {
158 .ant_div_control = 0,
159 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
160 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]161 .calFreqPier2G = {
162 FREQ2FBIN(2412, 1),
163 FREQ2FBIN(2437, 1),
164 FREQ2FBIN(2472, 1),
165 },
166 /* ar9300_cal_data_per_freq_op_loop 2g */
167 .calPierData2G = {
168 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
169 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
170 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
171 },
172 .calTarget_freqbin_Cck = {
173 FREQ2FBIN(2412, 1),
174 FREQ2FBIN(2484, 1),
175 },
176 .calTarget_freqbin_2G = {
177 FREQ2FBIN(2412, 1),
178 FREQ2FBIN(2437, 1),
179 FREQ2FBIN(2472, 1)
180 },
181 .calTarget_freqbin_2GHT20 = {
182 FREQ2FBIN(2412, 1),
183 FREQ2FBIN(2437, 1),
184 FREQ2FBIN(2472, 1)
185 },
186 .calTarget_freqbin_2GHT40 = {
187 FREQ2FBIN(2412, 1),
188 FREQ2FBIN(2437, 1),
189 FREQ2FBIN(2472, 1)
190 },
191 .calTargetPowerCck = {
192 /* 1L-5L,5S,11L,11S */
193 { {36, 36, 36, 36} },
194 { {36, 36, 36, 36} },
195 },
196 .calTargetPower2G = {
197 /* 6-24,36,48,54 */
198 { {32, 32, 28, 24} },
199 { {32, 32, 28, 24} },
200 { {32, 32, 28, 24} },
201 },
202 .calTargetPower2GHT20 = {
203 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
204 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
205 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
206 },
207 .calTargetPower2GHT40 = {
208 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
209 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
210 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
211 },
212 .ctlIndex_2G = {
213 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
214 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
215 },
216 .ctl_freqbin_2G = {
217 {
218 FREQ2FBIN(2412, 1),
219 FREQ2FBIN(2417, 1),
220 FREQ2FBIN(2457, 1),
221 FREQ2FBIN(2462, 1)
222 },
223 {
224 FREQ2FBIN(2412, 1),
225 FREQ2FBIN(2417, 1),
226 FREQ2FBIN(2462, 1),
227 0xFF,
228 },
229
230 {
231 FREQ2FBIN(2412, 1),
232 FREQ2FBIN(2417, 1),
233 FREQ2FBIN(2462, 1),
234 0xFF,
235 },
236 {
237 FREQ2FBIN(2422, 1),
238 FREQ2FBIN(2427, 1),
239 FREQ2FBIN(2447, 1),
240 FREQ2FBIN(2452, 1)
241 },
242
243 {
244 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
245 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
246 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
247 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
248 },
249
250 {
251 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
252 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
253 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
254 0,
255 },
256
257 {
258 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
259 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
260 FREQ2FBIN(2472, 1),
261 0,
262 },
263
264 {
265 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
266 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
267 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
268 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
269 },
270
271 {
272 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
273 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
274 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
275 },
276
277 {
278 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
279 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
280 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
281 0
282 },
283
284 {
285 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
286 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
287 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
288 0
289 },
290
291 {
292 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
293 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
294 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]295 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]296 }
297 },
298 .ctlPowerData_2G = {
299 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
300 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
301 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
302
303 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
304 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
305 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
306
307 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
308 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
309 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
310
311 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
312 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
Senthil Balasubramanianef5a6a72010-11-10 05:03:08 -0800[diff] [blame]313 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]314 },
315 .modalHeader5G = {
316 /* 4 idle,t1,t2,b (4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]317 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]318 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]319 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]320 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
321 .antCtrlChain = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]322 LE16(0x000), LE16(0x000), LE16(0x000),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]323 },
324 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
325 .xatten1DB = {0, 0, 0},
326
327 /*
328 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
329 * for merlin (0xa20c/b20c 16:12
330 */
331 .xatten1Margin = {0, 0, 0},
332 .tempSlope = 68,
333 .voltSlope = 0,
334 /* spurChans spur channels in usual fbin coding format */
335 .spurChans = {0, 0, 0, 0, 0},
336 /* noiseFloorThreshCh Check if the register is per chain */
337 .noiseFloorThreshCh = {-1, 0, 0},
338 .ob = {3, 3, 3}, /* 3 chain */
339 .db_stage2 = {3, 3, 3}, /* 3 chain */
340 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
341 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
342 .xpaBiasLvl = 0,
343 .txFrameToDataStart = 0x0e,
344 .txFrameToPaOn = 0x0e,
345 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
346 .antennaGain = 0,
347 .switchSettling = 0x2d,
348 .adcDesiredSize = -30,
349 .txEndToXpaOff = 0,
350 .txEndToRxOn = 0x2,
351 .txFrameToXpaOn = 0xe,
352 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]353 .papdRateMaskHt20 = LE32(0x0c80c080),
354 .papdRateMaskHt40 = LE32(0x0080c080),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]355 .futureModal = {
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]356 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]357 },
358 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]359 .base_ext2 = {
360 .tempSlopeLow = 0,
361 .tempSlopeHigh = 0,
362 .xatten1DBLow = {0, 0, 0},
363 .xatten1MarginLow = {0, 0, 0},
364 .xatten1DBHigh = {0, 0, 0},
365 .xatten1MarginHigh = {0, 0, 0}
366 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]367 .calFreqPier5G = {
368 FREQ2FBIN(5180, 0),
369 FREQ2FBIN(5220, 0),
370 FREQ2FBIN(5320, 0),
371 FREQ2FBIN(5400, 0),
372 FREQ2FBIN(5500, 0),
373 FREQ2FBIN(5600, 0),
374 FREQ2FBIN(5725, 0),
375 FREQ2FBIN(5825, 0)
376 },
377 .calPierData5G = {
378 {
379 {0, 0, 0, 0, 0},
380 {0, 0, 0, 0, 0},
381 {0, 0, 0, 0, 0},
382 {0, 0, 0, 0, 0},
383 {0, 0, 0, 0, 0},
384 {0, 0, 0, 0, 0},
385 {0, 0, 0, 0, 0},
386 {0, 0, 0, 0, 0},
387 },
388 {
389 {0, 0, 0, 0, 0},
390 {0, 0, 0, 0, 0},
391 {0, 0, 0, 0, 0},
392 {0, 0, 0, 0, 0},
393 {0, 0, 0, 0, 0},
394 {0, 0, 0, 0, 0},
395 {0, 0, 0, 0, 0},
396 {0, 0, 0, 0, 0},
397 },
398 {
399 {0, 0, 0, 0, 0},
400 {0, 0, 0, 0, 0},
401 {0, 0, 0, 0, 0},
402 {0, 0, 0, 0, 0},
403 {0, 0, 0, 0, 0},
404 {0, 0, 0, 0, 0},
405 {0, 0, 0, 0, 0},
406 {0, 0, 0, 0, 0},
407 },
408
409 },
410 .calTarget_freqbin_5G = {
411 FREQ2FBIN(5180, 0),
412 FREQ2FBIN(5220, 0),
413 FREQ2FBIN(5320, 0),
414 FREQ2FBIN(5400, 0),
415 FREQ2FBIN(5500, 0),
416 FREQ2FBIN(5600, 0),
417 FREQ2FBIN(5725, 0),
418 FREQ2FBIN(5825, 0)
419 },
420 .calTarget_freqbin_5GHT20 = {
421 FREQ2FBIN(5180, 0),
422 FREQ2FBIN(5240, 0),
423 FREQ2FBIN(5320, 0),
424 FREQ2FBIN(5500, 0),
425 FREQ2FBIN(5700, 0),
426 FREQ2FBIN(5745, 0),
427 FREQ2FBIN(5725, 0),
428 FREQ2FBIN(5825, 0)
429 },
430 .calTarget_freqbin_5GHT40 = {
431 FREQ2FBIN(5180, 0),
432 FREQ2FBIN(5240, 0),
433 FREQ2FBIN(5320, 0),
434 FREQ2FBIN(5500, 0),
435 FREQ2FBIN(5700, 0),
436 FREQ2FBIN(5745, 0),
437 FREQ2FBIN(5725, 0),
438 FREQ2FBIN(5825, 0)
439 },
440 .calTargetPower5G = {
441 /* 6-24,36,48,54 */
442 { {20, 20, 20, 10} },
443 { {20, 20, 20, 10} },
444 { {20, 20, 20, 10} },
445 { {20, 20, 20, 10} },
446 { {20, 20, 20, 10} },
447 { {20, 20, 20, 10} },
448 { {20, 20, 20, 10} },
449 { {20, 20, 20, 10} },
450 },
451 .calTargetPower5GHT20 = {
452 /*
453 * 0_8_16,1-3_9-11_17-19,
454 * 4,5,6,7,12,13,14,15,20,21,22,23
455 */
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
457 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
461 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
462 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
463 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
464 },
465 .calTargetPower5GHT40 = {
466 /*
467 * 0_8_16,1-3_9-11_17-19,
468 * 4,5,6,7,12,13,14,15,20,21,22,23
469 */
470 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
471 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
472 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
473 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
474 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
475 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
476 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
477 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
478 },
479 .ctlIndex_5G = {
480 0x10, 0x16, 0x18, 0x40, 0x46,
481 0x48, 0x30, 0x36, 0x38
482 },
483 .ctl_freqbin_5G = {
484 {
485 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
486 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
487 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
488 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
489 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
490 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
491 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
492 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
493 },
494 {
495 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
496 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
497 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
498 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
499 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
500 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
501 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
502 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
503 },
504
505 {
506 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
507 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
508 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
509 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
510 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
511 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
512 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
513 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
514 },
515
516 {
517 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
518 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
519 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
520 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
521 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
522 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
523 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
524 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
525 },
526
527 {
528 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
529 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
530 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
531 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
532 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
533 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
534 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
535 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
536 },
537
538 {
539 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
540 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
541 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
542 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
543 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
544 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
545 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
546 /* Data[5].ctlEdges[7].bChannel */ 0xFF
547 },
548
549 {
550 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
551 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
552 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
553 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
554 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
555 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
556 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
557 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
558 },
559
560 {
561 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
562 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
563 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
564 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
565 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
566 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
567 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
568 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
569 },
570
571 {
572 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
573 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
574 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
575 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
576 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
577 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
578 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
579 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
580 }
581 },
582 .ctlPowerData_5G = {
583 {
584 {
585 {60, 1}, {60, 1}, {60, 1}, {60, 1},
586 {60, 1}, {60, 1}, {60, 1}, {60, 0},
587 }
588 },
589 {
590 {
591 {60, 1}, {60, 1}, {60, 1}, {60, 1},
592 {60, 1}, {60, 1}, {60, 1}, {60, 0},
593 }
594 },
595 {
596 {
597 {60, 0}, {60, 1}, {60, 0}, {60, 1},
598 {60, 1}, {60, 1}, {60, 1}, {60, 1},
599 }
600 },
601 {
602 {
603 {60, 0}, {60, 1}, {60, 1}, {60, 0},
604 {60, 1}, {60, 0}, {60, 0}, {60, 0},
605 }
606 },
607 {
608 {
609 {60, 1}, {60, 1}, {60, 1}, {60, 0},
610 {60, 0}, {60, 0}, {60, 0}, {60, 0},
611 }
612 },
613 {
614 {
615 {60, 1}, {60, 1}, {60, 1}, {60, 1},
616 {60, 1}, {60, 0}, {60, 0}, {60, 0},
617 }
618 },
619 {
620 {
621 {60, 1}, {60, 1}, {60, 1}, {60, 1},
622 {60, 1}, {60, 1}, {60, 1}, {60, 1},
623 }
624 },
625 {
626 {
627 {60, 1}, {60, 1}, {60, 0}, {60, 1},
628 {60, 1}, {60, 1}, {60, 1}, {60, 0},
629 }
630 },
631 {
632 {
633 {60, 1}, {60, 0}, {60, 1}, {60, 1},
634 {60, 1}, {60, 1}, {60, 0}, {60, 1},
635 }
636 },
637 }
638};
639
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]640static const struct ar9300_eeprom ar9300_x113 = {
641 .eepromVersion = 2,
642 .templateVersion = 6,
643 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
644 .custData = {"x113-023-f0000"},
645 .baseEepHeader = {
646 .regDmn = { LE16(0), LE16(0x1f) },
647 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
648 .opCapFlags = {
649 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
650 .eepMisc = 0,
651 },
652 .rfSilent = 0,
653 .blueToothOptions = 0,
654 .deviceCap = 0,
655 .deviceType = 5, /* takes lower byte in eeprom location */
656 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
657 .params_for_tuning_caps = {0, 0},
658 .featureEnable = 0x0d,
659 /*
660 * bit0 - enable tx temp comp - disabled
661 * bit1 - enable tx volt comp - disabled
662 * bit2 - enable fastClock - enabled
663 * bit3 - enable doubling - enabled
664 * bit4 - enable internal regulator - disabled
665 * bit5 - enable pa predistortion - disabled
666 */
667 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
668 .eepromWriteEnableGpio = 6,
669 .wlanDisableGpio = 0,
670 .wlanLedGpio = 8,
671 .rxBandSelectGpio = 0xff,
672 .txrxgain = 0x21,
673 .swreg = 0,
674 },
675 .modalHeader2G = {
676 /* ar9300_modal_eep_header 2g */
677 /* 4 idle,t1,t2,b(4 bits per setting) */
678 .antCtrlCommon = LE32(0x110),
679 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
680 .antCtrlCommon2 = LE32(0x44444),
681
682 /*
683 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
684 * rx1, rx12, b (2 bits each)
685 */
686 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
687
688 /*
689 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
690 * for ar9280 (0xa20c/b20c 5:0)
691 */
692 .xatten1DB = {0, 0, 0},
693
694 /*
695 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
696 * for ar9280 (0xa20c/b20c 16:12
697 */
698 .xatten1Margin = {0, 0, 0},
699 .tempSlope = 25,
700 .voltSlope = 0,
701
702 /*
703 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
704 * channels in usual fbin coding format
705 */
706 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
707
708 /*
709 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
710 * if the register is per chain
711 */
712 .noiseFloorThreshCh = {-1, 0, 0},
713 .ob = {1, 1, 1},/* 3 chain */
714 .db_stage2 = {1, 1, 1}, /* 3 chain */
715 .db_stage3 = {0, 0, 0},
716 .db_stage4 = {0, 0, 0},
717 .xpaBiasLvl = 0,
718 .txFrameToDataStart = 0x0e,
719 .txFrameToPaOn = 0x0e,
720 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
721 .antennaGain = 0,
722 .switchSettling = 0x2c,
723 .adcDesiredSize = -30,
724 .txEndToXpaOff = 0,
725 .txEndToRxOn = 0x2,
726 .txFrameToXpaOn = 0xe,
727 .thresh62 = 28,
728 .papdRateMaskHt20 = LE32(0x0c80c080),
729 .papdRateMaskHt40 = LE32(0x0080c080),
730 .futureModal = {
731 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
732 },
733 },
734 .base_ext1 = {
735 .ant_div_control = 0,
736 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
737 },
738 .calFreqPier2G = {
739 FREQ2FBIN(2412, 1),
740 FREQ2FBIN(2437, 1),
741 FREQ2FBIN(2472, 1),
742 },
743 /* ar9300_cal_data_per_freq_op_loop 2g */
744 .calPierData2G = {
745 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
746 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
747 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
748 },
749 .calTarget_freqbin_Cck = {
750 FREQ2FBIN(2412, 1),
751 FREQ2FBIN(2472, 1),
752 },
753 .calTarget_freqbin_2G = {
754 FREQ2FBIN(2412, 1),
755 FREQ2FBIN(2437, 1),
756 FREQ2FBIN(2472, 1)
757 },
758 .calTarget_freqbin_2GHT20 = {
759 FREQ2FBIN(2412, 1),
760 FREQ2FBIN(2437, 1),
761 FREQ2FBIN(2472, 1)
762 },
763 .calTarget_freqbin_2GHT40 = {
764 FREQ2FBIN(2412, 1),
765 FREQ2FBIN(2437, 1),
766 FREQ2FBIN(2472, 1)
767 },
768 .calTargetPowerCck = {
769 /* 1L-5L,5S,11L,11S */
770 { {34, 34, 34, 34} },
771 { {34, 34, 34, 34} },
772 },
773 .calTargetPower2G = {
774 /* 6-24,36,48,54 */
775 { {34, 34, 32, 32} },
776 { {34, 34, 32, 32} },
777 { {34, 34, 32, 32} },
778 },
779 .calTargetPower2GHT20 = {
780 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
781 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
782 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
783 },
784 .calTargetPower2GHT40 = {
785 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
786 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
787 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
788 },
789 .ctlIndex_2G = {
790 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
791 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
792 },
793 .ctl_freqbin_2G = {
794 {
795 FREQ2FBIN(2412, 1),
796 FREQ2FBIN(2417, 1),
797 FREQ2FBIN(2457, 1),
798 FREQ2FBIN(2462, 1)
799 },
800 {
801 FREQ2FBIN(2412, 1),
802 FREQ2FBIN(2417, 1),
803 FREQ2FBIN(2462, 1),
804 0xFF,
805 },
806
807 {
808 FREQ2FBIN(2412, 1),
809 FREQ2FBIN(2417, 1),
810 FREQ2FBIN(2462, 1),
811 0xFF,
812 },
813 {
814 FREQ2FBIN(2422, 1),
815 FREQ2FBIN(2427, 1),
816 FREQ2FBIN(2447, 1),
817 FREQ2FBIN(2452, 1)
818 },
819
820 {
821 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
822 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
823 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
824 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
825 },
826
827 {
828 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
829 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
830 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
831 0,
832 },
833
834 {
835 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
836 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
837 FREQ2FBIN(2472, 1),
838 0,
839 },
840
841 {
842 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
843 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
844 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
845 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
846 },
847
848 {
849 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
850 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
851 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
852 },
853
854 {
855 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
856 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
857 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
858 0
859 },
860
861 {
862 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
863 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
864 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
865 0
866 },
867
868 {
869 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
870 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
871 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
872 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
873 }
874 },
875 .ctlPowerData_2G = {
876 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
877 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
878 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
879
880 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
881 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
882 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
883
884 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
885 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
886 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
887
888 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
889 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
890 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
891 },
892 .modalHeader5G = {
893 /* 4 idle,t1,t2,b (4 bits per setting) */
894 .antCtrlCommon = LE32(0x220),
895 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
896 .antCtrlCommon2 = LE32(0x11111),
897 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
898 .antCtrlChain = {
899 LE16(0x150), LE16(0x150), LE16(0x150),
900 },
901 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
902 .xatten1DB = {0, 0, 0},
903
904 /*
905 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
906 * for merlin (0xa20c/b20c 16:12
907 */
908 .xatten1Margin = {0, 0, 0},
909 .tempSlope = 68,
910 .voltSlope = 0,
911 /* spurChans spur channels in usual fbin coding format */
912 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
913 /* noiseFloorThreshCh Check if the register is per chain */
914 .noiseFloorThreshCh = {-1, 0, 0},
915 .ob = {3, 3, 3}, /* 3 chain */
916 .db_stage2 = {3, 3, 3}, /* 3 chain */
917 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
918 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
919 .xpaBiasLvl = 0,
920 .txFrameToDataStart = 0x0e,
921 .txFrameToPaOn = 0x0e,
922 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
923 .antennaGain = 0,
924 .switchSettling = 0x2d,
925 .adcDesiredSize = -30,
926 .txEndToXpaOff = 0,
927 .txEndToRxOn = 0x2,
928 .txFrameToXpaOn = 0xe,
929 .thresh62 = 28,
930 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
931 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
932 .futureModal = {
933 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
934 },
935 },
936 .base_ext2 = {
937 .tempSlopeLow = 72,
938 .tempSlopeHigh = 105,
939 .xatten1DBLow = {0, 0, 0},
940 .xatten1MarginLow = {0, 0, 0},
941 .xatten1DBHigh = {0, 0, 0},
942 .xatten1MarginHigh = {0, 0, 0}
943 },
944 .calFreqPier5G = {
945 FREQ2FBIN(5180, 0),
946 FREQ2FBIN(5240, 0),
947 FREQ2FBIN(5320, 0),
948 FREQ2FBIN(5400, 0),
949 FREQ2FBIN(5500, 0),
950 FREQ2FBIN(5600, 0),
951 FREQ2FBIN(5745, 0),
952 FREQ2FBIN(5785, 0)
953 },
954 .calPierData5G = {
955 {
956 {0, 0, 0, 0, 0},
957 {0, 0, 0, 0, 0},
958 {0, 0, 0, 0, 0},
959 {0, 0, 0, 0, 0},
960 {0, 0, 0, 0, 0},
961 {0, 0, 0, 0, 0},
962 {0, 0, 0, 0, 0},
963 {0, 0, 0, 0, 0},
964 },
965 {
966 {0, 0, 0, 0, 0},
967 {0, 0, 0, 0, 0},
968 {0, 0, 0, 0, 0},
969 {0, 0, 0, 0, 0},
970 {0, 0, 0, 0, 0},
971 {0, 0, 0, 0, 0},
972 {0, 0, 0, 0, 0},
973 {0, 0, 0, 0, 0},
974 },
975 {
976 {0, 0, 0, 0, 0},
977 {0, 0, 0, 0, 0},
978 {0, 0, 0, 0, 0},
979 {0, 0, 0, 0, 0},
980 {0, 0, 0, 0, 0},
981 {0, 0, 0, 0, 0},
982 {0, 0, 0, 0, 0},
983 {0, 0, 0, 0, 0},
984 },
985
986 },
987 .calTarget_freqbin_5G = {
988 FREQ2FBIN(5180, 0),
989 FREQ2FBIN(5220, 0),
990 FREQ2FBIN(5320, 0),
991 FREQ2FBIN(5400, 0),
992 FREQ2FBIN(5500, 0),
993 FREQ2FBIN(5600, 0),
994 FREQ2FBIN(5745, 0),
995 FREQ2FBIN(5785, 0)
996 },
997 .calTarget_freqbin_5GHT20 = {
998 FREQ2FBIN(5180, 0),
999 FREQ2FBIN(5240, 0),
1000 FREQ2FBIN(5320, 0),
1001 FREQ2FBIN(5400, 0),
1002 FREQ2FBIN(5500, 0),
1003 FREQ2FBIN(5700, 0),
1004 FREQ2FBIN(5745, 0),
1005 FREQ2FBIN(5825, 0)
1006 },
1007 .calTarget_freqbin_5GHT40 = {
1008 FREQ2FBIN(5190, 0),
1009 FREQ2FBIN(5230, 0),
1010 FREQ2FBIN(5320, 0),
1011 FREQ2FBIN(5410, 0),
1012 FREQ2FBIN(5510, 0),
1013 FREQ2FBIN(5670, 0),
1014 FREQ2FBIN(5755, 0),
1015 FREQ2FBIN(5825, 0)
1016 },
1017 .calTargetPower5G = {
1018 /* 6-24,36,48,54 */
1019 { {42, 40, 40, 34} },
1020 { {42, 40, 40, 34} },
1021 { {42, 40, 40, 34} },
1022 { {42, 40, 40, 34} },
1023 { {42, 40, 40, 34} },
1024 { {42, 40, 40, 34} },
1025 { {42, 40, 40, 34} },
1026 { {42, 40, 40, 34} },
1027 },
1028 .calTargetPower5GHT20 = {
1029 /*
1030 * 0_8_16,1-3_9-11_17-19,
1031 * 4,5,6,7,12,13,14,15,20,21,22,23
1032 */
1033 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1034 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1035 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1036 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1037 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1038 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1039 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1040 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1041 },
1042 .calTargetPower5GHT40 = {
1043 /*
1044 * 0_8_16,1-3_9-11_17-19,
1045 * 4,5,6,7,12,13,14,15,20,21,22,23
1046 */
1047 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1048 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1049 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1050 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1051 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1052 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1053 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1054 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1055 },
1056 .ctlIndex_5G = {
1057 0x10, 0x16, 0x18, 0x40, 0x46,
1058 0x48, 0x30, 0x36, 0x38
1059 },
1060 .ctl_freqbin_5G = {
1061 {
1062 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1063 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1064 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1065 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1066 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1067 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1068 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1069 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1070 },
1071 {
1072 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1073 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1074 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1075 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1076 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1077 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1078 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1079 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1080 },
1081
1082 {
1083 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1084 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1085 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1086 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1087 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1088 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1089 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1090 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1091 },
1092
1093 {
1094 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1095 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1096 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1097 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1098 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1099 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1100 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1101 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1102 },
1103
1104 {
1105 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1106 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1107 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1108 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1109 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1110 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1111 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1112 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1113 },
1114
1115 {
1116 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1117 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1118 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1119 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1120 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1121 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1122 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1123 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1124 },
1125
1126 {
1127 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1128 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1129 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1130 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1131 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1132 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1133 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1134 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1135 },
1136
1137 {
1138 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1139 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1140 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1141 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1142 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1143 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1144 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1145 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1146 },
1147
1148 {
1149 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1150 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1151 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1152 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1153 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1154 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1155 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1156 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1157 }
1158 },
1159 .ctlPowerData_5G = {
1160 {
1161 {
1162 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1163 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1164 }
1165 },
1166 {
1167 {
1168 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1169 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1170 }
1171 },
1172 {
1173 {
1174 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1175 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1176 }
1177 },
1178 {
1179 {
1180 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1181 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1182 }
1183 },
1184 {
1185 {
1186 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1187 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1188 }
1189 },
1190 {
1191 {
1192 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1193 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1194 }
1195 },
1196 {
1197 {
1198 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1199 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1200 }
1201 },
1202 {
1203 {
1204 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1205 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1206 }
1207 },
1208 {
1209 {
1210 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1211 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1212 }
1213 },
1214 }
1215};
1216
1217
1218static const struct ar9300_eeprom ar9300_h112 = {
1219 .eepromVersion = 2,
1220 .templateVersion = 3,
1221 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1222 .custData = {"h112-241-f0000"},
1223 .baseEepHeader = {
1224 .regDmn = { LE16(0), LE16(0x1f) },
1225 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1226 .opCapFlags = {
1227 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1228 .eepMisc = 0,
1229 },
1230 .rfSilent = 0,
1231 .blueToothOptions = 0,
1232 .deviceCap = 0,
1233 .deviceType = 5, /* takes lower byte in eeprom location */
1234 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1235 .params_for_tuning_caps = {0, 0},
1236 .featureEnable = 0x0d,
1237 /*
1238 * bit0 - enable tx temp comp - disabled
1239 * bit1 - enable tx volt comp - disabled
1240 * bit2 - enable fastClock - enabled
1241 * bit3 - enable doubling - enabled
1242 * bit4 - enable internal regulator - disabled
1243 * bit5 - enable pa predistortion - disabled
1244 */
1245 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1246 .eepromWriteEnableGpio = 6,
1247 .wlanDisableGpio = 0,
1248 .wlanLedGpio = 8,
1249 .rxBandSelectGpio = 0xff,
1250 .txrxgain = 0x10,
1251 .swreg = 0,
1252 },
1253 .modalHeader2G = {
1254 /* ar9300_modal_eep_header 2g */
1255 /* 4 idle,t1,t2,b(4 bits per setting) */
1256 .antCtrlCommon = LE32(0x110),
1257 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1258 .antCtrlCommon2 = LE32(0x44444),
1259
1260 /*
1261 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1262 * rx1, rx12, b (2 bits each)
1263 */
1264 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1265
1266 /*
1267 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1268 * for ar9280 (0xa20c/b20c 5:0)
1269 */
1270 .xatten1DB = {0, 0, 0},
1271
1272 /*
1273 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1274 * for ar9280 (0xa20c/b20c 16:12
1275 */
1276 .xatten1Margin = {0, 0, 0},
1277 .tempSlope = 25,
1278 .voltSlope = 0,
1279
1280 /*
1281 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1282 * channels in usual fbin coding format
1283 */
1284 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1285
1286 /*
1287 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1288 * if the register is per chain
1289 */
1290 .noiseFloorThreshCh = {-1, 0, 0},
1291 .ob = {1, 1, 1},/* 3 chain */
1292 .db_stage2 = {1, 1, 1}, /* 3 chain */
1293 .db_stage3 = {0, 0, 0},
1294 .db_stage4 = {0, 0, 0},
1295 .xpaBiasLvl = 0,
1296 .txFrameToDataStart = 0x0e,
1297 .txFrameToPaOn = 0x0e,
1298 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1299 .antennaGain = 0,
1300 .switchSettling = 0x2c,
1301 .adcDesiredSize = -30,
1302 .txEndToXpaOff = 0,
1303 .txEndToRxOn = 0x2,
1304 .txFrameToXpaOn = 0xe,
1305 .thresh62 = 28,
1306 .papdRateMaskHt20 = LE32(0x80c080),
1307 .papdRateMaskHt40 = LE32(0x80c080),
1308 .futureModal = {
1309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1310 },
1311 },
1312 .base_ext1 = {
1313 .ant_div_control = 0,
1314 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1315 },
1316 .calFreqPier2G = {
1317 FREQ2FBIN(2412, 1),
1318 FREQ2FBIN(2437, 1),
1319 FREQ2FBIN(2472, 1),
1320 },
1321 /* ar9300_cal_data_per_freq_op_loop 2g */
1322 .calPierData2G = {
1323 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1324 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1325 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1326 },
1327 .calTarget_freqbin_Cck = {
1328 FREQ2FBIN(2412, 1),
1329 FREQ2FBIN(2484, 1),
1330 },
1331 .calTarget_freqbin_2G = {
1332 FREQ2FBIN(2412, 1),
1333 FREQ2FBIN(2437, 1),
1334 FREQ2FBIN(2472, 1)
1335 },
1336 .calTarget_freqbin_2GHT20 = {
1337 FREQ2FBIN(2412, 1),
1338 FREQ2FBIN(2437, 1),
1339 FREQ2FBIN(2472, 1)
1340 },
1341 .calTarget_freqbin_2GHT40 = {
1342 FREQ2FBIN(2412, 1),
1343 FREQ2FBIN(2437, 1),
1344 FREQ2FBIN(2472, 1)
1345 },
1346 .calTargetPowerCck = {
1347 /* 1L-5L,5S,11L,11S */
1348 { {34, 34, 34, 34} },
1349 { {34, 34, 34, 34} },
1350 },
1351 .calTargetPower2G = {
1352 /* 6-24,36,48,54 */
1353 { {34, 34, 32, 32} },
1354 { {34, 34, 32, 32} },
1355 { {34, 34, 32, 32} },
1356 },
1357 .calTargetPower2GHT20 = {
1358 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1359 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1360 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1361 },
1362 .calTargetPower2GHT40 = {
1363 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1364 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1365 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1366 },
1367 .ctlIndex_2G = {
1368 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1369 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1370 },
1371 .ctl_freqbin_2G = {
1372 {
1373 FREQ2FBIN(2412, 1),
1374 FREQ2FBIN(2417, 1),
1375 FREQ2FBIN(2457, 1),
1376 FREQ2FBIN(2462, 1)
1377 },
1378 {
1379 FREQ2FBIN(2412, 1),
1380 FREQ2FBIN(2417, 1),
1381 FREQ2FBIN(2462, 1),
1382 0xFF,
1383 },
1384
1385 {
1386 FREQ2FBIN(2412, 1),
1387 FREQ2FBIN(2417, 1),
1388 FREQ2FBIN(2462, 1),
1389 0xFF,
1390 },
1391 {
1392 FREQ2FBIN(2422, 1),
1393 FREQ2FBIN(2427, 1),
1394 FREQ2FBIN(2447, 1),
1395 FREQ2FBIN(2452, 1)
1396 },
1397
1398 {
1399 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1400 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1401 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1402 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1403 },
1404
1405 {
1406 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1409 0,
1410 },
1411
1412 {
1413 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415 FREQ2FBIN(2472, 1),
1416 0,
1417 },
1418
1419 {
1420 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1421 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1422 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1423 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1424 },
1425
1426 {
1427 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1428 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1429 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1430 },
1431
1432 {
1433 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1434 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1435 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1436 0
1437 },
1438
1439 {
1440 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1441 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1442 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1443 0
1444 },
1445
1446 {
1447 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1448 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1449 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1450 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1451 }
1452 },
1453 .ctlPowerData_2G = {
1454 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1455 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1456 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
1457
1458 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
1459 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1460 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1461
1462 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
1463 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1464 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1465
1466 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1467 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1468 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1469 },
1470 .modalHeader5G = {
1471 /* 4 idle,t1,t2,b (4 bits per setting) */
1472 .antCtrlCommon = LE32(0x220),
1473 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1474 .antCtrlCommon2 = LE32(0x44444),
1475 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1476 .antCtrlChain = {
1477 LE16(0x150), LE16(0x150), LE16(0x150),
1478 },
1479 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1480 .xatten1DB = {0, 0, 0},
1481
1482 /*
1483 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1484 * for merlin (0xa20c/b20c 16:12
1485 */
1486 .xatten1Margin = {0, 0, 0},
1487 .tempSlope = 45,
1488 .voltSlope = 0,
1489 /* spurChans spur channels in usual fbin coding format */
1490 .spurChans = {0, 0, 0, 0, 0},
1491 /* noiseFloorThreshCh Check if the register is per chain */
1492 .noiseFloorThreshCh = {-1, 0, 0},
1493 .ob = {3, 3, 3}, /* 3 chain */
1494 .db_stage2 = {3, 3, 3}, /* 3 chain */
1495 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1496 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1497 .xpaBiasLvl = 0,
1498 .txFrameToDataStart = 0x0e,
1499 .txFrameToPaOn = 0x0e,
1500 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1501 .antennaGain = 0,
1502 .switchSettling = 0x2d,
1503 .adcDesiredSize = -30,
1504 .txEndToXpaOff = 0,
1505 .txEndToRxOn = 0x2,
1506 .txFrameToXpaOn = 0xe,
1507 .thresh62 = 28,
1508 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1509 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1510 .futureModal = {
1511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1512 },
1513 },
1514 .base_ext2 = {
1515 .tempSlopeLow = 40,
1516 .tempSlopeHigh = 50,
1517 .xatten1DBLow = {0, 0, 0},
1518 .xatten1MarginLow = {0, 0, 0},
1519 .xatten1DBHigh = {0, 0, 0},
1520 .xatten1MarginHigh = {0, 0, 0}
1521 },
1522 .calFreqPier5G = {
1523 FREQ2FBIN(5180, 0),
1524 FREQ2FBIN(5220, 0),
1525 FREQ2FBIN(5320, 0),
1526 FREQ2FBIN(5400, 0),
1527 FREQ2FBIN(5500, 0),
1528 FREQ2FBIN(5600, 0),
1529 FREQ2FBIN(5700, 0),
1530 FREQ2FBIN(5825, 0)
1531 },
1532 .calPierData5G = {
1533 {
1534 {0, 0, 0, 0, 0},
1535 {0, 0, 0, 0, 0},
1536 {0, 0, 0, 0, 0},
1537 {0, 0, 0, 0, 0},
1538 {0, 0, 0, 0, 0},
1539 {0, 0, 0, 0, 0},
1540 {0, 0, 0, 0, 0},
1541 {0, 0, 0, 0, 0},
1542 },
1543 {
1544 {0, 0, 0, 0, 0},
1545 {0, 0, 0, 0, 0},
1546 {0, 0, 0, 0, 0},
1547 {0, 0, 0, 0, 0},
1548 {0, 0, 0, 0, 0},
1549 {0, 0, 0, 0, 0},
1550 {0, 0, 0, 0, 0},
1551 {0, 0, 0, 0, 0},
1552 },
1553 {
1554 {0, 0, 0, 0, 0},
1555 {0, 0, 0, 0, 0},
1556 {0, 0, 0, 0, 0},
1557 {0, 0, 0, 0, 0},
1558 {0, 0, 0, 0, 0},
1559 {0, 0, 0, 0, 0},
1560 {0, 0, 0, 0, 0},
1561 {0, 0, 0, 0, 0},
1562 },
1563
1564 },
1565 .calTarget_freqbin_5G = {
1566 FREQ2FBIN(5180, 0),
1567 FREQ2FBIN(5240, 0),
1568 FREQ2FBIN(5320, 0),
1569 FREQ2FBIN(5400, 0),
1570 FREQ2FBIN(5500, 0),
1571 FREQ2FBIN(5600, 0),
1572 FREQ2FBIN(5700, 0),
1573 FREQ2FBIN(5825, 0)
1574 },
1575 .calTarget_freqbin_5GHT20 = {
1576 FREQ2FBIN(5180, 0),
1577 FREQ2FBIN(5240, 0),
1578 FREQ2FBIN(5320, 0),
1579 FREQ2FBIN(5400, 0),
1580 FREQ2FBIN(5500, 0),
1581 FREQ2FBIN(5700, 0),
1582 FREQ2FBIN(5745, 0),
1583 FREQ2FBIN(5825, 0)
1584 },
1585 .calTarget_freqbin_5GHT40 = {
1586 FREQ2FBIN(5180, 0),
1587 FREQ2FBIN(5240, 0),
1588 FREQ2FBIN(5320, 0),
1589 FREQ2FBIN(5400, 0),
1590 FREQ2FBIN(5500, 0),
1591 FREQ2FBIN(5700, 0),
1592 FREQ2FBIN(5745, 0),
1593 FREQ2FBIN(5825, 0)
1594 },
1595 .calTargetPower5G = {
1596 /* 6-24,36,48,54 */
1597 { {30, 30, 28, 24} },
1598 { {30, 30, 28, 24} },
1599 { {30, 30, 28, 24} },
1600 { {30, 30, 28, 24} },
1601 { {30, 30, 28, 24} },
1602 { {30, 30, 28, 24} },
1603 { {30, 30, 28, 24} },
1604 { {30, 30, 28, 24} },
1605 },
1606 .calTargetPower5GHT20 = {
1607 /*
1608 * 0_8_16,1-3_9-11_17-19,
1609 * 4,5,6,7,12,13,14,15,20,21,22,23
1610 */
1611 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1612 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1613 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1614 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1615 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1616 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1617 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1618 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1619 },
1620 .calTargetPower5GHT40 = {
1621 /*
1622 * 0_8_16,1-3_9-11_17-19,
1623 * 4,5,6,7,12,13,14,15,20,21,22,23
1624 */
1625 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1626 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1627 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1628 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1629 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1630 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1631 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1632 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1633 },
1634 .ctlIndex_5G = {
1635 0x10, 0x16, 0x18, 0x40, 0x46,
1636 0x48, 0x30, 0x36, 0x38
1637 },
1638 .ctl_freqbin_5G = {
1639 {
1640 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1641 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1642 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1643 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1644 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1645 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1646 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1647 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1648 },
1649 {
1650 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1651 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1652 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1653 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1654 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1655 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1656 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1657 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1658 },
1659
1660 {
1661 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1662 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1663 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1664 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1665 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1666 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1667 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1668 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1669 },
1670
1671 {
1672 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1673 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1674 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1675 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1676 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1677 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1678 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1679 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1680 },
1681
1682 {
1683 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1684 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1685 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1686 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1687 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1688 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1689 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1690 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1691 },
1692
1693 {
1694 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1695 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1696 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1697 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1698 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1699 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1700 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1701 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1702 },
1703
1704 {
1705 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1706 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1707 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1708 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1709 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1710 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1711 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1712 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1713 },
1714
1715 {
1716 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1717 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1718 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1719 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1720 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1721 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1722 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1723 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1724 },
1725
1726 {
1727 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1728 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1729 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1730 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1731 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1732 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1733 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1734 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1735 }
1736 },
1737 .ctlPowerData_5G = {
1738 {
1739 {
1740 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1741 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1742 }
1743 },
1744 {
1745 {
1746 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1747 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1748 }
1749 },
1750 {
1751 {
1752 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1753 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1754 }
1755 },
1756 {
1757 {
1758 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1759 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1760 }
1761 },
1762 {
1763 {
1764 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1765 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1766 }
1767 },
1768 {
1769 {
1770 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1771 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1772 }
1773 },
1774 {
1775 {
1776 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1777 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1778 }
1779 },
1780 {
1781 {
1782 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1783 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1784 }
1785 },
1786 {
1787 {
1788 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1789 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1790 }
1791 },
1792 }
1793};
1794
1795
1796static const struct ar9300_eeprom ar9300_x112 = {
1797 .eepromVersion = 2,
1798 .templateVersion = 5,
1799 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1800 .custData = {"x112-041-f0000"},
1801 .baseEepHeader = {
1802 .regDmn = { LE16(0), LE16(0x1f) },
1803 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1804 .opCapFlags = {
1805 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1806 .eepMisc = 0,
1807 },
1808 .rfSilent = 0,
1809 .blueToothOptions = 0,
1810 .deviceCap = 0,
1811 .deviceType = 5, /* takes lower byte in eeprom location */
1812 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1813 .params_for_tuning_caps = {0, 0},
1814 .featureEnable = 0x0d,
1815 /*
1816 * bit0 - enable tx temp comp - disabled
1817 * bit1 - enable tx volt comp - disabled
1818 * bit2 - enable fastclock - enabled
1819 * bit3 - enable doubling - enabled
1820 * bit4 - enable internal regulator - disabled
1821 * bit5 - enable pa predistortion - disabled
1822 */
1823 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1824 .eepromWriteEnableGpio = 6,
1825 .wlanDisableGpio = 0,
1826 .wlanLedGpio = 8,
1827 .rxBandSelectGpio = 0xff,
1828 .txrxgain = 0x0,
1829 .swreg = 0,
1830 },
1831 .modalHeader2G = {
1832 /* ar9300_modal_eep_header 2g */
1833 /* 4 idle,t1,t2,b(4 bits per setting) */
1834 .antCtrlCommon = LE32(0x110),
1835 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1836 .antCtrlCommon2 = LE32(0x22222),
1837
1838 /*
1839 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1840 * rx1, rx12, b (2 bits each)
1841 */
1842 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1843
1844 /*
1845 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1846 * for ar9280 (0xa20c/b20c 5:0)
1847 */
1848 .xatten1DB = {0x1b, 0x1b, 0x1b},
1849
1850 /*
1851 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1852 * for ar9280 (0xa20c/b20c 16:12
1853 */
1854 .xatten1Margin = {0x15, 0x15, 0x15},
1855 .tempSlope = 50,
1856 .voltSlope = 0,
1857
1858 /*
1859 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1860 * channels in usual fbin coding format
1861 */
1862 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1863
1864 /*
1865 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1866 * if the register is per chain
1867 */
1868 .noiseFloorThreshCh = {-1, 0, 0},
1869 .ob = {1, 1, 1},/* 3 chain */
1870 .db_stage2 = {1, 1, 1}, /* 3 chain */
1871 .db_stage3 = {0, 0, 0},
1872 .db_stage4 = {0, 0, 0},
1873 .xpaBiasLvl = 0,
1874 .txFrameToDataStart = 0x0e,
1875 .txFrameToPaOn = 0x0e,
1876 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1877 .antennaGain = 0,
1878 .switchSettling = 0x2c,
1879 .adcDesiredSize = -30,
1880 .txEndToXpaOff = 0,
1881 .txEndToRxOn = 0x2,
1882 .txFrameToXpaOn = 0xe,
1883 .thresh62 = 28,
1884 .papdRateMaskHt20 = LE32(0x0c80c080),
1885 .papdRateMaskHt40 = LE32(0x0080c080),
1886 .futureModal = {
1887 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1888 },
1889 },
1890 .base_ext1 = {
1891 .ant_div_control = 0,
1892 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1893 },
1894 .calFreqPier2G = {
1895 FREQ2FBIN(2412, 1),
1896 FREQ2FBIN(2437, 1),
1897 FREQ2FBIN(2472, 1),
1898 },
1899 /* ar9300_cal_data_per_freq_op_loop 2g */
1900 .calPierData2G = {
1901 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1902 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1903 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1904 },
1905 .calTarget_freqbin_Cck = {
1906 FREQ2FBIN(2412, 1),
1907 FREQ2FBIN(2472, 1),
1908 },
1909 .calTarget_freqbin_2G = {
1910 FREQ2FBIN(2412, 1),
1911 FREQ2FBIN(2437, 1),
1912 FREQ2FBIN(2472, 1)
1913 },
1914 .calTarget_freqbin_2GHT20 = {
1915 FREQ2FBIN(2412, 1),
1916 FREQ2FBIN(2437, 1),
1917 FREQ2FBIN(2472, 1)
1918 },
1919 .calTarget_freqbin_2GHT40 = {
1920 FREQ2FBIN(2412, 1),
1921 FREQ2FBIN(2437, 1),
1922 FREQ2FBIN(2472, 1)
1923 },
1924 .calTargetPowerCck = {
1925 /* 1L-5L,5S,11L,11s */
1926 { {38, 38, 38, 38} },
1927 { {38, 38, 38, 38} },
1928 },
1929 .calTargetPower2G = {
1930 /* 6-24,36,48,54 */
1931 { {38, 38, 36, 34} },
1932 { {38, 38, 36, 34} },
1933 { {38, 38, 34, 32} },
1934 },
1935 .calTargetPower2GHT20 = {
1936 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1937 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1938 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1939 },
1940 .calTargetPower2GHT40 = {
1941 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1942 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1943 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1944 },
1945 .ctlIndex_2G = {
1946 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1947 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1948 },
1949 .ctl_freqbin_2G = {
1950 {
1951 FREQ2FBIN(2412, 1),
1952 FREQ2FBIN(2417, 1),
1953 FREQ2FBIN(2457, 1),
1954 FREQ2FBIN(2462, 1)
1955 },
1956 {
1957 FREQ2FBIN(2412, 1),
1958 FREQ2FBIN(2417, 1),
1959 FREQ2FBIN(2462, 1),
1960 0xFF,
1961 },
1962
1963 {
1964 FREQ2FBIN(2412, 1),
1965 FREQ2FBIN(2417, 1),
1966 FREQ2FBIN(2462, 1),
1967 0xFF,
1968 },
1969 {
1970 FREQ2FBIN(2422, 1),
1971 FREQ2FBIN(2427, 1),
1972 FREQ2FBIN(2447, 1),
1973 FREQ2FBIN(2452, 1)
1974 },
1975
1976 {
1977 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1978 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1979 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1980 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1981 },
1982
1983 {
1984 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1985 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1986 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1987 0,
1988 },
1989
1990 {
1991 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1993 FREQ2FBIN(2472, 1),
1994 0,
1995 },
1996
1997 {
1998 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1999 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2000 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2001 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2002 },
2003
2004 {
2005 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2006 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2007 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2008 },
2009
2010 {
2011 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2012 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2013 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2014 0
2015 },
2016
2017 {
2018 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2019 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2020 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2021 0
2022 },
2023
2024 {
2025 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2026 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2027 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2028 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2029 }
2030 },
2031 .ctlPowerData_2G = {
2032 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2033 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2034 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2035
2036 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2037 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2038 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2039
2040 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2041 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2042 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2043
2044 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2045 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2046 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2047 },
2048 .modalHeader5G = {
2049 /* 4 idle,t1,t2,b (4 bits per setting) */
2050 .antCtrlCommon = LE32(0x110),
2051 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2052 .antCtrlCommon2 = LE32(0x22222),
2053 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2054 .antCtrlChain = {
2055 LE16(0x0), LE16(0x0), LE16(0x0),
2056 },
2057 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2058 .xatten1DB = {0x13, 0x19, 0x17},
2059
2060 /*
2061 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2062 * for merlin (0xa20c/b20c 16:12
2063 */
2064 .xatten1Margin = {0x19, 0x19, 0x19},
2065 .tempSlope = 70,
2066 .voltSlope = 15,
2067 /* spurChans spur channels in usual fbin coding format */
2068 .spurChans = {0, 0, 0, 0, 0},
2069 /* noiseFloorThreshch check if the register is per chain */
2070 .noiseFloorThreshCh = {-1, 0, 0},
2071 .ob = {3, 3, 3}, /* 3 chain */
2072 .db_stage2 = {3, 3, 3}, /* 3 chain */
2073 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2074 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2075 .xpaBiasLvl = 0,
2076 .txFrameToDataStart = 0x0e,
2077 .txFrameToPaOn = 0x0e,
2078 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2079 .antennaGain = 0,
2080 .switchSettling = 0x2d,
2081 .adcDesiredSize = -30,
2082 .txEndToXpaOff = 0,
2083 .txEndToRxOn = 0x2,
2084 .txFrameToXpaOn = 0xe,
2085 .thresh62 = 28,
2086 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2087 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2088 .futureModal = {
2089 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2090 },
2091 },
2092 .base_ext2 = {
2093 .tempSlopeLow = 72,
2094 .tempSlopeHigh = 105,
2095 .xatten1DBLow = {0x10, 0x14, 0x10},
2096 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2097 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2098 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2099 },
2100 .calFreqPier5G = {
2101 FREQ2FBIN(5180, 0),
2102 FREQ2FBIN(5220, 0),
2103 FREQ2FBIN(5320, 0),
2104 FREQ2FBIN(5400, 0),
2105 FREQ2FBIN(5500, 0),
2106 FREQ2FBIN(5600, 0),
2107 FREQ2FBIN(5700, 0),
2108 FREQ2FBIN(5785, 0)
2109 },
2110 .calPierData5G = {
2111 {
2112 {0, 0, 0, 0, 0},
2113 {0, 0, 0, 0, 0},
2114 {0, 0, 0, 0, 0},
2115 {0, 0, 0, 0, 0},
2116 {0, 0, 0, 0, 0},
2117 {0, 0, 0, 0, 0},
2118 {0, 0, 0, 0, 0},
2119 {0, 0, 0, 0, 0},
2120 },
2121 {
2122 {0, 0, 0, 0, 0},
2123 {0, 0, 0, 0, 0},
2124 {0, 0, 0, 0, 0},
2125 {0, 0, 0, 0, 0},
2126 {0, 0, 0, 0, 0},
2127 {0, 0, 0, 0, 0},
2128 {0, 0, 0, 0, 0},
2129 {0, 0, 0, 0, 0},
2130 },
2131 {
2132 {0, 0, 0, 0, 0},
2133 {0, 0, 0, 0, 0},
2134 {0, 0, 0, 0, 0},
2135 {0, 0, 0, 0, 0},
2136 {0, 0, 0, 0, 0},
2137 {0, 0, 0, 0, 0},
2138 {0, 0, 0, 0, 0},
2139 {0, 0, 0, 0, 0},
2140 },
2141
2142 },
2143 .calTarget_freqbin_5G = {
2144 FREQ2FBIN(5180, 0),
2145 FREQ2FBIN(5220, 0),
2146 FREQ2FBIN(5320, 0),
2147 FREQ2FBIN(5400, 0),
2148 FREQ2FBIN(5500, 0),
2149 FREQ2FBIN(5600, 0),
2150 FREQ2FBIN(5725, 0),
2151 FREQ2FBIN(5825, 0)
2152 },
2153 .calTarget_freqbin_5GHT20 = {
2154 FREQ2FBIN(5180, 0),
2155 FREQ2FBIN(5220, 0),
2156 FREQ2FBIN(5320, 0),
2157 FREQ2FBIN(5400, 0),
2158 FREQ2FBIN(5500, 0),
2159 FREQ2FBIN(5600, 0),
2160 FREQ2FBIN(5725, 0),
2161 FREQ2FBIN(5825, 0)
2162 },
2163 .calTarget_freqbin_5GHT40 = {
2164 FREQ2FBIN(5180, 0),
2165 FREQ2FBIN(5220, 0),
2166 FREQ2FBIN(5320, 0),
2167 FREQ2FBIN(5400, 0),
2168 FREQ2FBIN(5500, 0),
2169 FREQ2FBIN(5600, 0),
2170 FREQ2FBIN(5725, 0),
2171 FREQ2FBIN(5825, 0)
2172 },
2173 .calTargetPower5G = {
2174 /* 6-24,36,48,54 */
2175 { {32, 32, 28, 26} },
2176 { {32, 32, 28, 26} },
2177 { {32, 32, 28, 26} },
2178 { {32, 32, 26, 24} },
2179 { {32, 32, 26, 24} },
2180 { {32, 32, 24, 22} },
2181 { {30, 30, 24, 22} },
2182 { {30, 30, 24, 22} },
2183 },
2184 .calTargetPower5GHT20 = {
2185 /*
2186 * 0_8_16,1-3_9-11_17-19,
2187 * 4,5,6,7,12,13,14,15,20,21,22,23
2188 */
2189 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2190 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2191 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2192 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2193 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2194 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2195 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2196 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2197 },
2198 .calTargetPower5GHT40 = {
2199 /*
2200 * 0_8_16,1-3_9-11_17-19,
2201 * 4,5,6,7,12,13,14,15,20,21,22,23
2202 */
2203 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2204 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2205 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2206 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2207 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2208 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2209 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2210 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2211 },
2212 .ctlIndex_5G = {
2213 0x10, 0x16, 0x18, 0x40, 0x46,
2214 0x48, 0x30, 0x36, 0x38
2215 },
2216 .ctl_freqbin_5G = {
2217 {
2218 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2219 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2220 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2221 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2222 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2223 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2224 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2225 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2226 },
2227 {
2228 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2229 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2230 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2231 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2232 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2233 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2234 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2235 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2236 },
2237
2238 {
2239 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2240 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2241 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2242 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2243 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2244 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2245 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2246 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2247 },
2248
2249 {
2250 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2251 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2252 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2253 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2254 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2255 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2256 /* Data[3].ctledges[6].bchannel */ 0xFF,
2257 /* Data[3].ctledges[7].bchannel */ 0xFF,
2258 },
2259
2260 {
2261 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2262 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2263 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2264 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2265 /* Data[4].ctledges[4].bchannel */ 0xFF,
2266 /* Data[4].ctledges[5].bchannel */ 0xFF,
2267 /* Data[4].ctledges[6].bchannel */ 0xFF,
2268 /* Data[4].ctledges[7].bchannel */ 0xFF,
2269 },
2270
2271 {
2272 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2273 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2274 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2275 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2276 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2277 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2278 /* Data[5].ctledges[6].bchannel */ 0xFF,
2279 /* Data[5].ctledges[7].bchannel */ 0xFF
2280 },
2281
2282 {
2283 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2284 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2285 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2286 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2287 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2288 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2289 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2290 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2291 },
2292
2293 {
2294 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2295 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2296 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2297 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2298 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2299 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2300 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2301 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2302 },
2303
2304 {
2305 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2306 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2307 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2308 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2309 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2310 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2311 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2312 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2313 }
2314 },
2315 .ctlPowerData_5G = {
2316 {
2317 {
2318 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2319 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2320 }
2321 },
2322 {
2323 {
2324 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2325 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2326 }
2327 },
2328 {
2329 {
2330 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2331 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2332 }
2333 },
2334 {
2335 {
2336 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2337 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2338 }
2339 },
2340 {
2341 {
2342 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2343 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2344 }
2345 },
2346 {
2347 {
2348 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2349 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2350 }
2351 },
2352 {
2353 {
2354 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2355 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2356 }
2357 },
2358 {
2359 {
2360 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2361 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2362 }
2363 },
2364 {
2365 {
2366 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2367 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2368 }
2369 },
2370 }
2371};
2372
2373static const struct ar9300_eeprom ar9300_h116 = {
2374 .eepromVersion = 2,
2375 .templateVersion = 4,
2376 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2377 .custData = {"h116-041-f0000"},
2378 .baseEepHeader = {
2379 .regDmn = { LE16(0), LE16(0x1f) },
2380 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2381 .opCapFlags = {
2382 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
2383 .eepMisc = 0,
2384 },
2385 .rfSilent = 0,
2386 .blueToothOptions = 0,
2387 .deviceCap = 0,
2388 .deviceType = 5, /* takes lower byte in eeprom location */
2389 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2390 .params_for_tuning_caps = {0, 0},
2391 .featureEnable = 0x0d,
2392 /*
2393 * bit0 - enable tx temp comp - disabled
2394 * bit1 - enable tx volt comp - disabled
2395 * bit2 - enable fastClock - enabled
2396 * bit3 - enable doubling - enabled
2397 * bit4 - enable internal regulator - disabled
2398 * bit5 - enable pa predistortion - disabled
2399 */
2400 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2401 .eepromWriteEnableGpio = 6,
2402 .wlanDisableGpio = 0,
2403 .wlanLedGpio = 8,
2404 .rxBandSelectGpio = 0xff,
2405 .txrxgain = 0x10,
2406 .swreg = 0,
2407 },
2408 .modalHeader2G = {
2409 /* ar9300_modal_eep_header 2g */
2410 /* 4 idle,t1,t2,b(4 bits per setting) */
2411 .antCtrlCommon = LE32(0x110),
2412 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2413 .antCtrlCommon2 = LE32(0x44444),
2414
2415 /*
2416 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2417 * rx1, rx12, b (2 bits each)
2418 */
2419 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2420
2421 /*
2422 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2423 * for ar9280 (0xa20c/b20c 5:0)
2424 */
2425 .xatten1DB = {0x1f, 0x1f, 0x1f},
2426
2427 /*
2428 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2429 * for ar9280 (0xa20c/b20c 16:12
2430 */
2431 .xatten1Margin = {0x12, 0x12, 0x12},
2432 .tempSlope = 25,
2433 .voltSlope = 0,
2434
2435 /*
2436 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2437 * channels in usual fbin coding format
2438 */
2439 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2440
2441 /*
2442 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2443 * if the register is per chain
2444 */
2445 .noiseFloorThreshCh = {-1, 0, 0},
2446 .ob = {1, 1, 1},/* 3 chain */
2447 .db_stage2 = {1, 1, 1}, /* 3 chain */
2448 .db_stage3 = {0, 0, 0},
2449 .db_stage4 = {0, 0, 0},
2450 .xpaBiasLvl = 0,
2451 .txFrameToDataStart = 0x0e,
2452 .txFrameToPaOn = 0x0e,
2453 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2454 .antennaGain = 0,
2455 .switchSettling = 0x2c,
2456 .adcDesiredSize = -30,
2457 .txEndToXpaOff = 0,
2458 .txEndToRxOn = 0x2,
2459 .txFrameToXpaOn = 0xe,
2460 .thresh62 = 28,
2461 .papdRateMaskHt20 = LE32(0x0c80C080),
2462 .papdRateMaskHt40 = LE32(0x0080C080),
2463 .futureModal = {
2464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2465 },
2466 },
2467 .base_ext1 = {
2468 .ant_div_control = 0,
2469 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2470 },
2471 .calFreqPier2G = {
2472 FREQ2FBIN(2412, 1),
2473 FREQ2FBIN(2437, 1),
2474 FREQ2FBIN(2472, 1),
2475 },
2476 /* ar9300_cal_data_per_freq_op_loop 2g */
2477 .calPierData2G = {
2478 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2479 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2480 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2481 },
2482 .calTarget_freqbin_Cck = {
2483 FREQ2FBIN(2412, 1),
2484 FREQ2FBIN(2472, 1),
2485 },
2486 .calTarget_freqbin_2G = {
2487 FREQ2FBIN(2412, 1),
2488 FREQ2FBIN(2437, 1),
2489 FREQ2FBIN(2472, 1)
2490 },
2491 .calTarget_freqbin_2GHT20 = {
2492 FREQ2FBIN(2412, 1),
2493 FREQ2FBIN(2437, 1),
2494 FREQ2FBIN(2472, 1)
2495 },
2496 .calTarget_freqbin_2GHT40 = {
2497 FREQ2FBIN(2412, 1),
2498 FREQ2FBIN(2437, 1),
2499 FREQ2FBIN(2472, 1)
2500 },
2501 .calTargetPowerCck = {
2502 /* 1L-5L,5S,11L,11S */
2503 { {34, 34, 34, 34} },
2504 { {34, 34, 34, 34} },
2505 },
2506 .calTargetPower2G = {
2507 /* 6-24,36,48,54 */
2508 { {34, 34, 32, 32} },
2509 { {34, 34, 32, 32} },
2510 { {34, 34, 32, 32} },
2511 },
2512 .calTargetPower2GHT20 = {
2513 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2514 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2515 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2516 },
2517 .calTargetPower2GHT40 = {
2518 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2519 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2520 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2521 },
2522 .ctlIndex_2G = {
2523 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2524 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2525 },
2526 .ctl_freqbin_2G = {
2527 {
2528 FREQ2FBIN(2412, 1),
2529 FREQ2FBIN(2417, 1),
2530 FREQ2FBIN(2457, 1),
2531 FREQ2FBIN(2462, 1)
2532 },
2533 {
2534 FREQ2FBIN(2412, 1),
2535 FREQ2FBIN(2417, 1),
2536 FREQ2FBIN(2462, 1),
2537 0xFF,
2538 },
2539
2540 {
2541 FREQ2FBIN(2412, 1),
2542 FREQ2FBIN(2417, 1),
2543 FREQ2FBIN(2462, 1),
2544 0xFF,
2545 },
2546 {
2547 FREQ2FBIN(2422, 1),
2548 FREQ2FBIN(2427, 1),
2549 FREQ2FBIN(2447, 1),
2550 FREQ2FBIN(2452, 1)
2551 },
2552
2553 {
2554 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2555 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2556 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2557 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2558 },
2559
2560 {
2561 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2562 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2563 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2564 0,
2565 },
2566
2567 {
2568 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2569 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2570 FREQ2FBIN(2472, 1),
2571 0,
2572 },
2573
2574 {
2575 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2576 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2577 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2578 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2579 },
2580
2581 {
2582 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2583 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2584 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2585 },
2586
2587 {
2588 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2589 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2590 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2591 0
2592 },
2593
2594 {
2595 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2596 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2597 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2598 0
2599 },
2600
2601 {
2602 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2603 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2604 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2605 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2606 }
2607 },
2608 .ctlPowerData_2G = {
2609 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2610 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2611 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2612
2613 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2614 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2615 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2616
2617 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2618 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2619 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2620
2621 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2622 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2623 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2624 },
2625 .modalHeader5G = {
2626 /* 4 idle,t1,t2,b (4 bits per setting) */
2627 .antCtrlCommon = LE32(0x220),
2628 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2629 .antCtrlCommon2 = LE32(0x44444),
2630 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2631 .antCtrlChain = {
2632 LE16(0x150), LE16(0x150), LE16(0x150),
2633 },
2634 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2635 .xatten1DB = {0x19, 0x19, 0x19},
2636
2637 /*
2638 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2639 * for merlin (0xa20c/b20c 16:12
2640 */
2641 .xatten1Margin = {0x14, 0x14, 0x14},
2642 .tempSlope = 70,
2643 .voltSlope = 0,
2644 /* spurChans spur channels in usual fbin coding format */
2645 .spurChans = {0, 0, 0, 0, 0},
2646 /* noiseFloorThreshCh Check if the register is per chain */
2647 .noiseFloorThreshCh = {-1, 0, 0},
2648 .ob = {3, 3, 3}, /* 3 chain */
2649 .db_stage2 = {3, 3, 3}, /* 3 chain */
2650 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2651 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2652 .xpaBiasLvl = 0,
2653 .txFrameToDataStart = 0x0e,
2654 .txFrameToPaOn = 0x0e,
2655 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2656 .antennaGain = 0,
2657 .switchSettling = 0x2d,
2658 .adcDesiredSize = -30,
2659 .txEndToXpaOff = 0,
2660 .txEndToRxOn = 0x2,
2661 .txFrameToXpaOn = 0xe,
2662 .thresh62 = 28,
2663 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2664 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2665 .futureModal = {
2666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2667 },
2668 },
2669 .base_ext2 = {
2670 .tempSlopeLow = 35,
2671 .tempSlopeHigh = 50,
2672 .xatten1DBLow = {0, 0, 0},
2673 .xatten1MarginLow = {0, 0, 0},
2674 .xatten1DBHigh = {0, 0, 0},
2675 .xatten1MarginHigh = {0, 0, 0}
2676 },
2677 .calFreqPier5G = {
2678 FREQ2FBIN(5180, 0),
2679 FREQ2FBIN(5220, 0),
2680 FREQ2FBIN(5320, 0),
2681 FREQ2FBIN(5400, 0),
2682 FREQ2FBIN(5500, 0),
2683 FREQ2FBIN(5600, 0),
2684 FREQ2FBIN(5700, 0),
2685 FREQ2FBIN(5785, 0)
2686 },
2687 .calPierData5G = {
2688 {
2689 {0, 0, 0, 0, 0},
2690 {0, 0, 0, 0, 0},
2691 {0, 0, 0, 0, 0},
2692 {0, 0, 0, 0, 0},
2693 {0, 0, 0, 0, 0},
2694 {0, 0, 0, 0, 0},
2695 {0, 0, 0, 0, 0},
2696 {0, 0, 0, 0, 0},
2697 },
2698 {
2699 {0, 0, 0, 0, 0},
2700 {0, 0, 0, 0, 0},
2701 {0, 0, 0, 0, 0},
2702 {0, 0, 0, 0, 0},
2703 {0, 0, 0, 0, 0},
2704 {0, 0, 0, 0, 0},
2705 {0, 0, 0, 0, 0},
2706 {0, 0, 0, 0, 0},
2707 },
2708 {
2709 {0, 0, 0, 0, 0},
2710 {0, 0, 0, 0, 0},
2711 {0, 0, 0, 0, 0},
2712 {0, 0, 0, 0, 0},
2713 {0, 0, 0, 0, 0},
2714 {0, 0, 0, 0, 0},
2715 {0, 0, 0, 0, 0},
2716 {0, 0, 0, 0, 0},
2717 },
2718
2719 },
2720 .calTarget_freqbin_5G = {
2721 FREQ2FBIN(5180, 0),
2722 FREQ2FBIN(5240, 0),
2723 FREQ2FBIN(5320, 0),
2724 FREQ2FBIN(5400, 0),
2725 FREQ2FBIN(5500, 0),
2726 FREQ2FBIN(5600, 0),
2727 FREQ2FBIN(5700, 0),
2728 FREQ2FBIN(5825, 0)
2729 },
2730 .calTarget_freqbin_5GHT20 = {
2731 FREQ2FBIN(5180, 0),
2732 FREQ2FBIN(5240, 0),
2733 FREQ2FBIN(5320, 0),
2734 FREQ2FBIN(5400, 0),
2735 FREQ2FBIN(5500, 0),
2736 FREQ2FBIN(5700, 0),
2737 FREQ2FBIN(5745, 0),
2738 FREQ2FBIN(5825, 0)
2739 },
2740 .calTarget_freqbin_5GHT40 = {
2741 FREQ2FBIN(5180, 0),
2742 FREQ2FBIN(5240, 0),
2743 FREQ2FBIN(5320, 0),
2744 FREQ2FBIN(5400, 0),
2745 FREQ2FBIN(5500, 0),
2746 FREQ2FBIN(5700, 0),
2747 FREQ2FBIN(5745, 0),
2748 FREQ2FBIN(5825, 0)
2749 },
2750 .calTargetPower5G = {
2751 /* 6-24,36,48,54 */
2752 { {30, 30, 28, 24} },
2753 { {30, 30, 28, 24} },
2754 { {30, 30, 28, 24} },
2755 { {30, 30, 28, 24} },
2756 { {30, 30, 28, 24} },
2757 { {30, 30, 28, 24} },
2758 { {30, 30, 28, 24} },
2759 { {30, 30, 28, 24} },
2760 },
2761 .calTargetPower5GHT20 = {
2762 /*
2763 * 0_8_16,1-3_9-11_17-19,
2764 * 4,5,6,7,12,13,14,15,20,21,22,23
2765 */
2766 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2767 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2768 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2769 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2770 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2771 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2772 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2773 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2774 },
2775 .calTargetPower5GHT40 = {
2776 /*
2777 * 0_8_16,1-3_9-11_17-19,
2778 * 4,5,6,7,12,13,14,15,20,21,22,23
2779 */
2780 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2781 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2782 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2783 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2784 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2785 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2786 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2787 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2788 },
2789 .ctlIndex_5G = {
2790 0x10, 0x16, 0x18, 0x40, 0x46,
2791 0x48, 0x30, 0x36, 0x38
2792 },
2793 .ctl_freqbin_5G = {
2794 {
2795 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2796 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2797 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2798 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2799 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2800 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2801 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2802 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2803 },
2804 {
2805 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2806 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2807 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2808 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2809 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2810 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2811 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2812 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2813 },
2814
2815 {
2816 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2817 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2818 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2819 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2820 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2821 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2822 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2823 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2824 },
2825
2826 {
2827 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2828 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2829 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2830 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2831 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2832 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2833 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2834 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2835 },
2836
2837 {
2838 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2839 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2840 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2841 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2842 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2843 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2844 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2845 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2846 },
2847
2848 {
2849 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2850 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2851 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2852 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2853 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2854 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2855 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2856 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2857 },
2858
2859 {
2860 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2861 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2862 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2863 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2864 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2865 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2866 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2867 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2868 },
2869
2870 {
2871 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2872 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2873 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2874 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2875 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2876 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2877 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2878 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2879 },
2880
2881 {
2882 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2883 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2884 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2885 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2886 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2887 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2888 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2889 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2890 }
2891 },
2892 .ctlPowerData_5G = {
2893 {
2894 {
2895 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2896 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2897 }
2898 },
2899 {
2900 {
2901 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2902 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2903 }
2904 },
2905 {
2906 {
2907 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2908 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2909 }
2910 },
2911 {
2912 {
2913 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2914 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2915 }
2916 },
2917 {
2918 {
2919 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2920 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2921 }
2922 },
2923 {
2924 {
2925 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2926 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2927 }
2928 },
2929 {
2930 {
2931 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2932 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2933 }
2934 },
2935 {
2936 {
2937 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2938 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2939 }
2940 },
2941 {
2942 {
2943 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2944 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2945 }
2946 },
2947 }
2948};
2949
2950
2951static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2952 &ar9300_default,
2953 &ar9300_x112,
2954 &ar9300_h116,
2955 &ar9300_h112,
2956 &ar9300_x113,
2957};
2958
2959static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2960{
2961#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2962 int it;
2963
2964 for (it = 0; it < N_LOOP; it++)
2965 if (ar9300_eep_templates[it]->templateVersion == id)
2966 return ar9300_eep_templates[it];
2967 return NULL;
2968#undef N_LOOP
2969}
2970
2971
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]2972static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2973{
2974 if (fbin == AR9300_BCHAN_UNUSED)
2975 return fbin;
2976
2977 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2978}
2979
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2980static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2981{
2982 return 0;
2983}
2984
2985static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2986 enum eeprom_param param)
2987{
2988 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2989 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2990
2991 switch (param) {
2992 case EEP_MAC_LSW:
2993 return eep->macAddr[0] << 8 | eep->macAddr[1];
2994 case EEP_MAC_MID:
2995 return eep->macAddr[2] << 8 | eep->macAddr[3];
2996 case EEP_MAC_MSW:
2997 return eep->macAddr[4] << 8 | eep->macAddr[5];
2998 case EEP_REG_0:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]2999 return le16_to_cpu(pBase->regDmn[0]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3000 case EEP_REG_1:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3001 return le16_to_cpu(pBase->regDmn[1]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3002 case EEP_OP_CAP:
3003 return pBase->deviceCap;
3004 case EEP_OP_MODE:
3005 return pBase->opCapFlags.opFlags;
3006 case EEP_RF_SILENT:
3007 return pBase->rfSilent;
3008 case EEP_TX_MASK:
3009 return (pBase->txrxMask >> 4) & 0xf;
3010 case EEP_RX_MASK:
3011 return pBase->txrxMask & 0xf;
3012 case EEP_DRIVE_STRENGTH:
3013#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3014 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3015 case EEP_INTERNAL_REGULATOR:
3016 /* Bit 4 is internal regulator flag */
3017 return (pBase->featureEnable & 0x10) >> 4;
3018 case EEP_SWREG:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3019 return le32_to_cpu(pBase->swreg);
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]3020 case EEP_PAPRD:
3021 return !!(pBase->featureEnable & BIT(5));
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3022 default:
3023 return 0;
3024 }
3025}
3026
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3027static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3028 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3029{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3030 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3031
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3032 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3033 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3034
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3035 *buffer = (val >> (8 * (address % 2))) & 0xff;
3036 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3037}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3038
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3039static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3040 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3041{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3042 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3043
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3044 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3045 return false;
3046
3047 buffer[0] = val >> 8;
3048 buffer[1] = val & 0xff;
3049
3050 return true;
3051}
3052
3053static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3054 int count)
3055{
3056 struct ath_common *common = ath9k_hw_common(ah);
3057 int i;
3058
3059 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3060 ath_print(common, ATH_DBG_EEPROM,
3061 "eeprom address not in range\n");
3062 return false;
3063 }
3064
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3065 /*
3066 * Since we're reading the bytes in reverse order from a little-endian
3067 * word stream, an even address means we only use the lower half of
3068 * the 16-bit word at that address
3069 */
3070 if (address % 2 == 0) {
3071 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3072 goto error;
3073
3074 count--;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3075 }
3076
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3077 for (i = 0; i < count / 2; i++) {
3078 if (!ar9300_eeprom_read_word(common, address, buffer))
3079 goto error;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3080
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3081 address -= 2;
3082 buffer += 2;
3083 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3084
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3085 if (count % 2)
3086 if (!ar9300_eeprom_read_byte(common, address, buffer))
3087 goto error;
3088
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3089 return true;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3090
3091error:
3092 ath_print(common, ATH_DBG_EEPROM,
3093 "unable to read eeprom region at offset %d\n", address);
3094 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3095}
3096
3097static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3098 int *length, int *major, int *minor)
3099{
3100 unsigned long value[4];
3101
3102 value[0] = best[0];
3103 value[1] = best[1];
3104 value[2] = best[2];
3105 value[3] = best[3];
3106 *code = ((value[0] >> 5) & 0x0007);
3107 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3108 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3109 *major = (value[2] & 0x000f);
3110 *minor = (value[3] & 0x00ff);
3111}
3112
3113static u16 ar9300_comp_cksum(u8 *data, int dsize)
3114{
3115 int it, checksum = 0;
3116
3117 for (it = 0; it < dsize; it++) {
3118 checksum += data[it];
3119 checksum &= 0xffff;
3120 }
3121
3122 return checksum;
3123}
3124
3125static bool ar9300_uncompress_block(struct ath_hw *ah,
3126 u8 *mptr,
3127 int mdataSize,
3128 u8 *block,
3129 int size)
3130{
3131 int it;
3132 int spot;
3133 int offset;
3134 int length;
3135 struct ath_common *common = ath9k_hw_common(ah);
3136
3137 spot = 0;
3138
3139 for (it = 0; it < size; it += (length+2)) {
3140 offset = block[it];
3141 offset &= 0xff;
3142 spot += offset;
3143 length = block[it+1];
3144 length &= 0xff;
3145
Luis R. Rodriguez803288e2010-08-30 19:26:32 -0400[diff] [blame]3146 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3147 ath_print(common, ATH_DBG_EEPROM,
3148 "Restore at %d: spot=%d "
3149 "offset=%d length=%d\n",
3150 it, spot, offset, length);
3151 memcpy(&mptr[spot], &block[it+2], length);
3152 spot += length;
3153 } else if (length > 0) {
3154 ath_print(common, ATH_DBG_EEPROM,
3155 "Bad restore at %d: spot=%d "
3156 "offset=%d length=%d\n",
3157 it, spot, offset, length);
3158 return false;
3159 }
3160 }
3161 return true;
3162}
3163
3164static int ar9300_compress_decision(struct ath_hw *ah,
3165 int it,
3166 int code,
3167 int reference,
3168 u8 *mptr,
3169 u8 *word, int length, int mdata_size)
3170{
3171 struct ath_common *common = ath9k_hw_common(ah);
3172 u8 *dptr;
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3173 const struct ar9300_eeprom *eep = NULL;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3174
3175 switch (code) {
3176 case _CompressNone:
3177 if (length != mdata_size) {
3178 ath_print(common, ATH_DBG_EEPROM,
3179 "EEPROM structure size mismatch"
3180 "memory=%d eeprom=%d\n", mdata_size, length);
3181 return -1;
3182 }
3183 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3184 ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
3185 " uncompressed, length %d\n", it, length);
3186 break;
3187 case _CompressBlock:
3188 if (reference == 0) {
3189 dptr = mptr;
3190 } else {
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3191 eep = ar9003_eeprom_struct_find_by_id(reference);
3192 if (eep == NULL) {
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3193 ath_print(common, ATH_DBG_EEPROM,
3194 "cant find reference eeprom"
3195 "struct %d\n", reference);
3196 return -1;
3197 }
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3198 memcpy(mptr, eep, mdata_size);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3199 }
3200 ath_print(common, ATH_DBG_EEPROM,
3201 "restore eeprom %d: block, reference %d,"
3202 " length %d\n", it, reference, length);
3203 ar9300_uncompress_block(ah, mptr, mdata_size,
3204 (u8 *) (word + COMP_HDR_LEN), length);
3205 break;
3206 default:
3207 ath_print(common, ATH_DBG_EEPROM, "unknown compression"
3208 " code %d\n", code);
3209 return -1;
3210 }
3211 return 0;
3212}
3213
3214/*
3215 * Read the configuration data from the eeprom.
3216 * The data can be put in any specified memory buffer.
3217 *
3218 * Returns -1 on error.
3219 * Returns address of next memory location on success.
3220 */
3221static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3222 u8 *mptr, int mdata_size)
3223{
3224#define MDEFAULT 15
3225#define MSTATE 100
3226 int cptr;
3227 u8 *word;
3228 int code;
3229 int reference, length, major, minor;
3230 int osize;
3231 int it;
3232 u16 checksum, mchecksum;
3233 struct ath_common *common = ath9k_hw_common(ah);
3234
3235 word = kzalloc(2048, GFP_KERNEL);
3236 if (!word)
3237 return -1;
3238
3239 memcpy(mptr, &ar9300_default, mdata_size);
3240
3241 cptr = AR9300_BASE_ADDR;
3242 for (it = 0; it < MSTATE; it++) {
3243 if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
3244 goto fail;
3245
3246 if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
3247 word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
3248 && word[2] == 0xff && word[3] == 0xff))
3249 break;
3250
3251 ar9300_comp_hdr_unpack(word, &code, &reference,
3252 &length, &major, &minor);
3253 ath_print(common, ATH_DBG_EEPROM,
3254 "Found block at %x: code=%d ref=%d"
3255 "length=%d major=%d minor=%d\n", cptr, code,
3256 reference, length, major, minor);
3257 if (length >= 1024) {
3258 ath_print(common, ATH_DBG_EEPROM,
3259 "Skipping bad header\n");
3260 cptr -= COMP_HDR_LEN;
3261 continue;
3262 }
3263
3264 osize = length;
3265 ar9300_read_eeprom(ah, cptr, word,
3266 COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3267 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3268 mchecksum = word[COMP_HDR_LEN + osize] |
3269 (word[COMP_HDR_LEN + osize + 1] << 8);
3270 ath_print(common, ATH_DBG_EEPROM,
3271 "checksum %x %x\n", checksum, mchecksum);
3272 if (checksum == mchecksum) {
3273 ar9300_compress_decision(ah, it, code, reference, mptr,
3274 word, length, mdata_size);
3275 } else {
3276 ath_print(common, ATH_DBG_EEPROM,
3277 "skipping block with bad checksum\n");
3278 }
3279 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3280 }
3281
3282 kfree(word);
3283 return cptr;
3284
3285fail:
3286 kfree(word);
3287 return -1;
3288}
3289
3290/*
3291 * Restore the configuration structure by reading the eeprom.
3292 * This function destroys any existing in-memory structure
3293 * content.
3294 */
3295static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3296{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3297 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3298
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3299 if (ar9300_eeprom_restore_internal(ah, mptr,
3300 sizeof(struct ar9300_eeprom)) < 0)
3301 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3302
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3303 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3304}
3305
3306/* XXX: review hardware docs */
3307static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3308{
3309 return ah->eeprom.ar9300_eep.eepromVersion;
3310}
3311
3312/* XXX: could be read from the eepromVersion, not sure yet */
3313static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3314{
3315 return 0;
3316}
3317
3318static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
Rajkumar Manoharanf799a302010-09-16 11:40:06 +0530[diff] [blame]3319 enum ath9k_hal_freq_band freq_band)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3320{
3321 return 1;
3322}
3323
Felix Fietkau601e0cb2010-07-11 12:48:39 +0200[diff] [blame]3324static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3325 struct ath9k_channel *chan)
3326{
3327 return -EINVAL;
3328}
3329
3330static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3331{
3332 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3333
3334 if (is2ghz)
3335 return eep->modalHeader2G.xpaBiasLvl;
3336 else
3337 return eep->modalHeader5G.xpaBiasLvl;
3338}
3339
3340static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3341{
3342 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
Vasanthakumar Thiagarajan52a0e242010-11-10 05:03:11 -0800[diff] [blame]3343 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3344 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
3345 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3346}
3347
3348static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3349{
3350 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3351 __le32 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3352
3353 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3354 val = eep->modalHeader2G.antCtrlCommon;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3355 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3356 val = eep->modalHeader5G.antCtrlCommon;
3357 return le32_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3358}
3359
3360static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3361{
3362 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3363 __le32 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3364
3365 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3366 val = eep->modalHeader2G.antCtrlCommon2;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3367 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3368 val = eep->modalHeader5G.antCtrlCommon2;
3369 return le32_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3370}
3371
3372static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3373 int chain,
3374 bool is2ghz)
3375{
3376 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3377 __le16 val = 0;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3378
3379 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3380 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3381 val = eep->modalHeader2G.antCtrlChain[chain];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3382 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3383 val = eep->modalHeader5G.antCtrlChain[chain];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3384 }
3385
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3386 return le16_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3387}
3388
3389static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3390{
3391 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3392 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3393
3394 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3395 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3396
3397 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
3398 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
3399
3400 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3401 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
3402
3403 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
3404 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
3405}
3406
3407static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3408{
3409 int drive_strength;
3410 unsigned long reg;
3411
3412 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3413
3414 if (!drive_strength)
3415 return;
3416
3417 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3418 reg &= ~0x00ffffc0;
3419 reg |= 0x5 << 21;
3420 reg |= 0x5 << 18;
3421 reg |= 0x5 << 15;
3422 reg |= 0x5 << 12;
3423 reg |= 0x5 << 9;
3424 reg |= 0x5 << 6;
3425 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3426
3427 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3428 reg &= ~0xffffffe0;
3429 reg |= 0x5 << 29;
3430 reg |= 0x5 << 26;
3431 reg |= 0x5 << 23;
3432 reg |= 0x5 << 20;
3433 reg |= 0x5 << 17;
3434 reg |= 0x5 << 14;
3435 reg |= 0x5 << 11;
3436 reg |= 0x5 << 8;
3437 reg |= 0x5 << 5;
3438 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3439
3440 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3441 reg &= ~0xff800000;
3442 reg |= 0x5 << 29;
3443 reg |= 0x5 << 26;
3444 reg |= 0x5 << 23;
3445 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3446}
3447
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3448static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3449 struct ath9k_channel *chan)
3450{
3451 int f[3], t[3];
3452 u16 value;
3453 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3454
3455 if (chain >= 0 && chain < 3) {
3456 if (IS_CHAN_2GHZ(chan))
3457 return eep->modalHeader2G.xatten1DB[chain];
3458 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3459 t[0] = eep->base_ext2.xatten1DBLow[chain];
3460 f[0] = 5180;
3461 t[1] = eep->modalHeader5G.xatten1DB[chain];
3462 f[1] = 5500;
3463 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3464 f[2] = 5785;
3465 value = ar9003_hw_power_interpolate((s32) chan->channel,
3466 f, t, 3);
3467 return value;
3468 } else
3469 return eep->modalHeader5G.xatten1DB[chain];
3470 }
3471
3472 return 0;
3473}
3474
3475
3476static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3477 struct ath9k_channel *chan)
3478{
3479 int f[3], t[3];
3480 u16 value;
3481 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3482
3483 if (chain >= 0 && chain < 3) {
3484 if (IS_CHAN_2GHZ(chan))
3485 return eep->modalHeader2G.xatten1Margin[chain];
3486 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3487 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3488 f[0] = 5180;
3489 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3490 f[1] = 5500;
3491 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3492 f[2] = 5785;
3493 value = ar9003_hw_power_interpolate((s32) chan->channel,
3494 f, t, 3);
3495 return value;
3496 } else
3497 return eep->modalHeader5G.xatten1Margin[chain];
3498 }
3499
3500 return 0;
3501}
3502
3503static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3504{
3505 int i;
3506 u16 value;
3507 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3508 AR_PHY_EXT_ATTEN_CTL_1,
3509 AR_PHY_EXT_ATTEN_CTL_2,
3510 };
3511
3512 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3513 for (i = 0; i < 3; i++) {
3514 value = ar9003_hw_atten_chain_get(ah, i, chan);
3515 REG_RMW_FIELD(ah, ext_atten_reg[i],
3516 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3517
3518 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3519 REG_RMW_FIELD(ah, ext_atten_reg[i],
3520 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
3521 }
3522}
3523
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3524static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3525{
3526 int internal_regulator =
3527 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3528
3529 if (internal_regulator) {
3530 /* Internal regulator is ON. Write swreg register. */
3531 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3532 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3533 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3534 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3535 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3536 /* Set REG_CONTROL1.SWREG_PROGRAM */
3537 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3538 REG_READ(ah,
3539 AR_RTC_REG_CONTROL1) |
3540 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3541 } else {
3542 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3543 (REG_READ(ah,
3544 AR_RTC_SLEEP_CLK) |
3545 AR_RTC_FORCE_SWREG_PRD));
3546 }
3547}
3548
3549static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3550 struct ath9k_channel *chan)
3551{
3552 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3553 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3554 ar9003_hw_drive_strength_apply(ah);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3555 ar9003_hw_atten_apply(ah, chan);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3556 ar9003_hw_internal_regulator_apply(ah);
3557}
3558
3559static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3560 struct ath9k_channel *chan)
3561{
3562}
3563
3564/*
3565 * Returns the interpolated y value corresponding to the specified x value
3566 * from the np ordered pairs of data (px,py).
3567 * The pairs do not have to be in any order.
3568 * If the specified x value is less than any of the px,
3569 * the returned y value is equal to the py for the lowest px.
3570 * If the specified x value is greater than any of the px,
3571 * the returned y value is equal to the py for the highest px.
3572 */
3573static int ar9003_hw_power_interpolate(int32_t x,
3574 int32_t *px, int32_t *py, u_int16_t np)
3575{
3576 int ip = 0;
3577 int lx = 0, ly = 0, lhave = 0;
3578 int hx = 0, hy = 0, hhave = 0;
3579 int dx = 0;
3580 int y = 0;
3581
3582 lhave = 0;
3583 hhave = 0;
3584
3585 /* identify best lower and higher x calibration measurement */
3586 for (ip = 0; ip < np; ip++) {
3587 dx = x - px[ip];
3588
3589 /* this measurement is higher than our desired x */
3590 if (dx <= 0) {
3591 if (!hhave || dx > (x - hx)) {
3592 /* new best higher x measurement */
3593 hx = px[ip];
3594 hy = py[ip];
3595 hhave = 1;
3596 }
3597 }
3598 /* this measurement is lower than our desired x */
3599 if (dx >= 0) {
3600 if (!lhave || dx < (x - lx)) {
3601 /* new best lower x measurement */
3602 lx = px[ip];
3603 ly = py[ip];
3604 lhave = 1;
3605 }
3606 }
3607 }
3608
3609 /* the low x is good */
3610 if (lhave) {
3611 /* so is the high x */
3612 if (hhave) {
3613 /* they're the same, so just pick one */
3614 if (hx == lx)
3615 y = ly;
3616 else /* interpolate */
3617 y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
3618 } else /* only low is good, use it */
3619 y = ly;
3620 } else if (hhave) /* only high is good, use it */
3621 y = hy;
3622 else /* nothing is good,this should never happen unless np=0, ???? */
3623 y = -(1 << 30);
3624 return y;
3625}
3626
3627static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3628 u16 rateIndex, u16 freq, bool is2GHz)
3629{
3630 u16 numPiers, i;
3631 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3632 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3633 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3634 struct cal_tgt_pow_legacy *pEepromTargetPwr;
3635 u8 *pFreqBin;
3636
3637 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]3638 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3639 pEepromTargetPwr = eep->calTargetPower2G;
3640 pFreqBin = eep->calTarget_freqbin_2G;
3641 } else {
3642 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3643 pEepromTargetPwr = eep->calTargetPower5G;
3644 pFreqBin = eep->calTarget_freqbin_5G;
3645 }
3646
3647 /*
3648 * create array of channels and targetpower from
3649 * targetpower piers stored on eeprom
3650 */
3651 for (i = 0; i < numPiers; i++) {
3652 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3653 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3654 }
3655
3656 /* interpolate to get target power for given frequency */
3657 return (u8) ar9003_hw_power_interpolate((s32) freq,
3658 freqArray,
3659 targetPowerArray, numPiers);
3660}
3661
3662static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3663 u16 rateIndex,
3664 u16 freq, bool is2GHz)
3665{
3666 u16 numPiers, i;
3667 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3668 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3669 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3670 struct cal_tgt_pow_ht *pEepromTargetPwr;
3671 u8 *pFreqBin;
3672
3673 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]3674 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3675 pEepromTargetPwr = eep->calTargetPower2GHT20;
3676 pFreqBin = eep->calTarget_freqbin_2GHT20;
3677 } else {
3678 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3679 pEepromTargetPwr = eep->calTargetPower5GHT20;
3680 pFreqBin = eep->calTarget_freqbin_5GHT20;
3681 }
3682
3683 /*
3684 * create array of channels and targetpower
3685 * from targetpower piers stored on eeprom
3686 */
3687 for (i = 0; i < numPiers; i++) {
3688 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3689 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3690 }
3691
3692 /* interpolate to get target power for given frequency */
3693 return (u8) ar9003_hw_power_interpolate((s32) freq,
3694 freqArray,
3695 targetPowerArray, numPiers);
3696}
3697
3698static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3699 u16 rateIndex,
3700 u16 freq, bool is2GHz)
3701{
3702 u16 numPiers, i;
3703 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3704 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3705 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3706 struct cal_tgt_pow_ht *pEepromTargetPwr;
3707 u8 *pFreqBin;
3708
3709 if (is2GHz) {
3710 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3711 pEepromTargetPwr = eep->calTargetPower2GHT40;
3712 pFreqBin = eep->calTarget_freqbin_2GHT40;
3713 } else {
3714 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3715 pEepromTargetPwr = eep->calTargetPower5GHT40;
3716 pFreqBin = eep->calTarget_freqbin_5GHT40;
3717 }
3718
3719 /*
3720 * create array of channels and targetpower from
3721 * targetpower piers stored on eeprom
3722 */
3723 for (i = 0; i < numPiers; i++) {
3724 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3725 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3726 }
3727
3728 /* interpolate to get target power for given frequency */
3729 return (u8) ar9003_hw_power_interpolate((s32) freq,
3730 freqArray,
3731 targetPowerArray, numPiers);
3732}
3733
3734static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3735 u16 rateIndex, u16 freq)
3736{
3737 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3738 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3739 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3740 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3741 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3742 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3743
3744 /*
3745 * create array of channels and targetpower from
3746 * targetpower piers stored on eeprom
3747 */
3748 for (i = 0; i < numPiers; i++) {
3749 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
3750 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3751 }
3752
3753 /* interpolate to get target power for given frequency */
3754 return (u8) ar9003_hw_power_interpolate((s32) freq,
3755 freqArray,
3756 targetPowerArray, numPiers);
3757}
3758
3759/* Set tx power registers to array of values passed in */
3760static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
3761{
3762#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
3763 /* make sure forced gain is not set */
3764 REG_WRITE(ah, 0xa458, 0);
3765
3766 /* Write the OFDM power per rate set */
3767
3768 /* 6 (LSB), 9, 12, 18 (MSB) */
3769 REG_WRITE(ah, 0xa3c0,
3770 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
3771 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
3772 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
3773 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3774
3775 /* 24 (LSB), 36, 48, 54 (MSB) */
3776 REG_WRITE(ah, 0xa3c4,
3777 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
3778 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
3779 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
3780 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3781
3782 /* Write the CCK power per rate set */
3783
3784 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3785 REG_WRITE(ah, 0xa3c8,
3786 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
3787 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
3788 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
3789 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
3790
3791 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3792 REG_WRITE(ah, 0xa3cc,
3793 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
3794 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
3795 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
3796 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
3797 );
3798
3799 /* Write the HT20 power per rate set */
3800
3801 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3802 REG_WRITE(ah, 0xa3d0,
3803 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
3804 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
3805 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
3806 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
3807 );
3808
3809 /* 6 (LSB), 7, 12, 13 (MSB) */
3810 REG_WRITE(ah, 0xa3d4,
3811 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
3812 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
3813 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
3814 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
3815 );
3816
3817 /* 14 (LSB), 15, 20, 21 */
3818 REG_WRITE(ah, 0xa3e4,
3819 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
3820 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
3821 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
3822 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
3823 );
3824
3825 /* Mixed HT20 and HT40 rates */
3826
3827 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3828 REG_WRITE(ah, 0xa3e8,
3829 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
3830 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
3831 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
3832 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
3833 );
3834
3835 /*
3836 * Write the HT40 power per rate set
3837 * correct PAR difference between HT40 and HT20/LEGACY
3838 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
3839 */
3840 REG_WRITE(ah, 0xa3d8,
3841 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
3842 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
3843 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
3844 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
3845 );
3846
3847 /* 6 (LSB), 7, 12, 13 (MSB) */
3848 REG_WRITE(ah, 0xa3dc,
3849 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
3850 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
3851 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
3852 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
3853 );
3854
3855 /* 14 (LSB), 15, 20, 21 */
3856 REG_WRITE(ah, 0xa3ec,
3857 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
3858 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
3859 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
3860 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
3861 );
3862
3863 return 0;
3864#undef POW_SM
3865}
3866
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]3867static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
3868 u8 *targetPowerValT2)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3869{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3870 /* XXX: hard code for now, need to get from eeprom struct */
3871 u8 ht40PowerIncForPdadc = 0;
3872 bool is2GHz = false;
3873 unsigned int i = 0;
3874 struct ath_common *common = ath9k_hw_common(ah);
3875
3876 if (freq < 4000)
3877 is2GHz = true;
3878
3879 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
3880 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
3881 is2GHz);
3882 targetPowerValT2[ALL_TARGET_LEGACY_36] =
3883 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
3884 is2GHz);
3885 targetPowerValT2[ALL_TARGET_LEGACY_48] =
3886 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
3887 is2GHz);
3888 targetPowerValT2[ALL_TARGET_LEGACY_54] =
3889 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
3890 is2GHz);
3891 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
3892 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
3893 freq);
3894 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
3895 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
3896 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
3897 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
3898 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
3899 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
3900 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
3901 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
3902 is2GHz);
3903 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
3904 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
3905 freq, is2GHz);
3906 targetPowerValT2[ALL_TARGET_HT20_4] =
3907 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
3908 is2GHz);
3909 targetPowerValT2[ALL_TARGET_HT20_5] =
3910 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
3911 is2GHz);
3912 targetPowerValT2[ALL_TARGET_HT20_6] =
3913 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
3914 is2GHz);
3915 targetPowerValT2[ALL_TARGET_HT20_7] =
3916 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
3917 is2GHz);
3918 targetPowerValT2[ALL_TARGET_HT20_12] =
3919 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
3920 is2GHz);
3921 targetPowerValT2[ALL_TARGET_HT20_13] =
3922 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
3923 is2GHz);
3924 targetPowerValT2[ALL_TARGET_HT20_14] =
3925 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
3926 is2GHz);
3927 targetPowerValT2[ALL_TARGET_HT20_15] =
3928 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
3929 is2GHz);
3930 targetPowerValT2[ALL_TARGET_HT20_20] =
3931 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
3932 is2GHz);
3933 targetPowerValT2[ALL_TARGET_HT20_21] =
3934 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
3935 is2GHz);
3936 targetPowerValT2[ALL_TARGET_HT20_22] =
3937 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
3938 is2GHz);
3939 targetPowerValT2[ALL_TARGET_HT20_23] =
3940 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
3941 is2GHz);
3942 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
3943 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
3944 is2GHz) + ht40PowerIncForPdadc;
3945 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
3946 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
3947 freq,
3948 is2GHz) + ht40PowerIncForPdadc;
3949 targetPowerValT2[ALL_TARGET_HT40_4] =
3950 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
3951 is2GHz) + ht40PowerIncForPdadc;
3952 targetPowerValT2[ALL_TARGET_HT40_5] =
3953 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
3954 is2GHz) + ht40PowerIncForPdadc;
3955 targetPowerValT2[ALL_TARGET_HT40_6] =
3956 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
3957 is2GHz) + ht40PowerIncForPdadc;
3958 targetPowerValT2[ALL_TARGET_HT40_7] =
3959 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
3960 is2GHz) + ht40PowerIncForPdadc;
3961 targetPowerValT2[ALL_TARGET_HT40_12] =
3962 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
3963 is2GHz) + ht40PowerIncForPdadc;
3964 targetPowerValT2[ALL_TARGET_HT40_13] =
3965 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
3966 is2GHz) + ht40PowerIncForPdadc;
3967 targetPowerValT2[ALL_TARGET_HT40_14] =
3968 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
3969 is2GHz) + ht40PowerIncForPdadc;
3970 targetPowerValT2[ALL_TARGET_HT40_15] =
3971 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
3972 is2GHz) + ht40PowerIncForPdadc;
3973 targetPowerValT2[ALL_TARGET_HT40_20] =
3974 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
3975 is2GHz) + ht40PowerIncForPdadc;
3976 targetPowerValT2[ALL_TARGET_HT40_21] =
3977 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
3978 is2GHz) + ht40PowerIncForPdadc;
3979 targetPowerValT2[ALL_TARGET_HT40_22] =
3980 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
3981 is2GHz) + ht40PowerIncForPdadc;
3982 targetPowerValT2[ALL_TARGET_HT40_23] =
3983 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
3984 is2GHz) + ht40PowerIncForPdadc;
3985
3986 while (i < ar9300RateSize) {
3987 ath_print(common, ATH_DBG_EEPROM,
3988 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
3989 i++;
3990
3991 ath_print(common, ATH_DBG_EEPROM,
3992 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
3993 i++;
3994
3995 ath_print(common, ATH_DBG_EEPROM,
3996 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
3997 i++;
3998
3999 ath_print(common, ATH_DBG_EEPROM,
4000 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4001 i++;
4002 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4003}
4004
4005static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4006 int mode,
4007 int ipier,
4008 int ichain,
4009 int *pfrequency,
4010 int *pcorrection,
4011 int *ptemperature, int *pvoltage)
4012{
4013 u8 *pCalPier;
4014 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4015 int is2GHz;
4016 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4017 struct ath_common *common = ath9k_hw_common(ah);
4018
4019 if (ichain >= AR9300_MAX_CHAINS) {
4020 ath_print(common, ATH_DBG_EEPROM,
4021 "Invalid chain index, must be less than %d\n",
4022 AR9300_MAX_CHAINS);
4023 return -1;
4024 }
4025
4026 if (mode) { /* 5GHz */
4027 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4028 ath_print(common, ATH_DBG_EEPROM,
4029 "Invalid 5GHz cal pier index, must "
4030 "be less than %d\n",
4031 AR9300_NUM_5G_CAL_PIERS);
4032 return -1;
4033 }
4034 pCalPier = &(eep->calFreqPier5G[ipier]);
4035 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4036 is2GHz = 0;
4037 } else {
4038 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4039 ath_print(common, ATH_DBG_EEPROM,
4040 "Invalid 2GHz cal pier index, must "
4041 "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
4042 return -1;
4043 }
4044
4045 pCalPier = &(eep->calFreqPier2G[ipier]);
4046 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4047 is2GHz = 1;
4048 }
4049
4050 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4051 *pcorrection = pCalPierStruct->refPower;
4052 *ptemperature = pCalPierStruct->tempMeas;
4053 *pvoltage = pCalPierStruct->voltMeas;
4054
4055 return 0;
4056}
4057
4058static int ar9003_hw_power_control_override(struct ath_hw *ah,
4059 int frequency,
4060 int *correction,
4061 int *voltage, int *temperature)
4062{
4063 int tempSlope = 0;
4064 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame^]4065 int f[3], t[3];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4066
4067 REG_RMW(ah, AR_PHY_TPC_11_B0,
4068 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4069 AR_PHY_TPC_OLPC_GAIN_DELTA);
4070 REG_RMW(ah, AR_PHY_TPC_11_B1,
4071 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4072 AR_PHY_TPC_OLPC_GAIN_DELTA);
4073 REG_RMW(ah, AR_PHY_TPC_11_B2,
4074 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4075 AR_PHY_TPC_OLPC_GAIN_DELTA);
4076
4077 /* enable open loop power control on chip */
4078 REG_RMW(ah, AR_PHY_TPC_6_B0,
4079 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4080 AR_PHY_TPC_6_ERROR_EST_MODE);
4081 REG_RMW(ah, AR_PHY_TPC_6_B1,
4082 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4083 AR_PHY_TPC_6_ERROR_EST_MODE);
4084 REG_RMW(ah, AR_PHY_TPC_6_B2,
4085 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4086 AR_PHY_TPC_6_ERROR_EST_MODE);
4087
4088 /*
4089 * enable temperature compensation
4090 * Need to use register names
4091 */
4092 if (frequency < 4000)
4093 tempSlope = eep->modalHeader2G.tempSlope;
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame^]4094 else if (eep->base_ext2.tempSlopeLow != 0) {
4095 t[0] = eep->base_ext2.tempSlopeLow;
4096 f[0] = 5180;
4097 t[1] = eep->modalHeader5G.tempSlope;
4098 f[1] = 5500;
4099 t[2] = eep->base_ext2.tempSlopeHigh;
4100 f[2] = 5785;
4101 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4102 f, t, 3);
4103 } else
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4104 tempSlope = eep->modalHeader5G.tempSlope;
4105
4106 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4107 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4108 temperature[0]);
4109
4110 return 0;
4111}
4112
4113/* Apply the recorded correction values. */
4114static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4115{
4116 int ichain, ipier, npier;
4117 int mode;
4118 int lfrequency[AR9300_MAX_CHAINS],
4119 lcorrection[AR9300_MAX_CHAINS],
4120 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4121 int hfrequency[AR9300_MAX_CHAINS],
4122 hcorrection[AR9300_MAX_CHAINS],
4123 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4124 int fdiff;
4125 int correction[AR9300_MAX_CHAINS],
4126 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4127 int pfrequency, pcorrection, ptemperature, pvoltage;
4128 struct ath_common *common = ath9k_hw_common(ah);
4129
4130 mode = (frequency >= 4000);
4131 if (mode)
4132 npier = AR9300_NUM_5G_CAL_PIERS;
4133 else
4134 npier = AR9300_NUM_2G_CAL_PIERS;
4135
4136 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4137 lfrequency[ichain] = 0;
4138 hfrequency[ichain] = 100000;
4139 }
4140 /* identify best lower and higher frequency calibration measurement */
4141 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4142 for (ipier = 0; ipier < npier; ipier++) {
4143 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4144 &pfrequency, &pcorrection,
4145 &ptemperature, &pvoltage)) {
4146 fdiff = frequency - pfrequency;
4147
4148 /*
4149 * this measurement is higher than
4150 * our desired frequency
4151 */
4152 if (fdiff <= 0) {
4153 if (hfrequency[ichain] <= 0 ||
4154 hfrequency[ichain] >= 100000 ||
4155 fdiff >
4156 (frequency - hfrequency[ichain])) {
4157 /*
4158 * new best higher
4159 * frequency measurement
4160 */
4161 hfrequency[ichain] = pfrequency;
4162 hcorrection[ichain] =
4163 pcorrection;
4164 htemperature[ichain] =
4165 ptemperature;
4166 hvoltage[ichain] = pvoltage;
4167 }
4168 }
4169 if (fdiff >= 0) {
4170 if (lfrequency[ichain] <= 0
4171 || fdiff <
4172 (frequency - lfrequency[ichain])) {
4173 /*
4174 * new best lower
4175 * frequency measurement
4176 */
4177 lfrequency[ichain] = pfrequency;
4178 lcorrection[ichain] =
4179 pcorrection;
4180 ltemperature[ichain] =
4181 ptemperature;
4182 lvoltage[ichain] = pvoltage;
4183 }
4184 }
4185 }
4186 }
4187 }
4188
4189 /* interpolate */
4190 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4191 ath_print(common, ATH_DBG_EEPROM,
4192 "ch=%d f=%d low=%d %d h=%d %d\n",
4193 ichain, frequency, lfrequency[ichain],
4194 lcorrection[ichain], hfrequency[ichain],
4195 hcorrection[ichain]);
4196 /* they're the same, so just pick one */
4197 if (hfrequency[ichain] == lfrequency[ichain]) {
4198 correction[ichain] = lcorrection[ichain];
4199 voltage[ichain] = lvoltage[ichain];
4200 temperature[ichain] = ltemperature[ichain];
4201 }
4202 /* the low frequency is good */
4203 else if (frequency - lfrequency[ichain] < 1000) {
4204 /* so is the high frequency, interpolate */
4205 if (hfrequency[ichain] - frequency < 1000) {
4206
4207 correction[ichain] = lcorrection[ichain] +
4208 (((frequency - lfrequency[ichain]) *
4209 (hcorrection[ichain] -
4210 lcorrection[ichain])) /
4211 (hfrequency[ichain] - lfrequency[ichain]));
4212
4213 temperature[ichain] = ltemperature[ichain] +
4214 (((frequency - lfrequency[ichain]) *
4215 (htemperature[ichain] -
4216 ltemperature[ichain])) /
4217 (hfrequency[ichain] - lfrequency[ichain]));
4218
4219 voltage[ichain] =
4220 lvoltage[ichain] +
4221 (((frequency -
4222 lfrequency[ichain]) * (hvoltage[ichain] -
4223 lvoltage[ichain]))
4224 / (hfrequency[ichain] -
4225 lfrequency[ichain]));
4226 }
4227 /* only low is good, use it */
4228 else {
4229 correction[ichain] = lcorrection[ichain];
4230 temperature[ichain] = ltemperature[ichain];
4231 voltage[ichain] = lvoltage[ichain];
4232 }
4233 }
4234 /* only high is good, use it */
4235 else if (hfrequency[ichain] - frequency < 1000) {
4236 correction[ichain] = hcorrection[ichain];
4237 temperature[ichain] = htemperature[ichain];
4238 voltage[ichain] = hvoltage[ichain];
4239 } else { /* nothing is good, presume 0???? */
4240 correction[ichain] = 0;
4241 temperature[ichain] = 0;
4242 voltage[ichain] = 0;
4243 }
4244 }
4245
4246 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4247 temperature);
4248
4249 ath_print(common, ATH_DBG_EEPROM,
4250 "for frequency=%d, calibration correction = %d %d %d\n",
4251 frequency, correction[0], correction[1], correction[2]);
4252
4253 return 0;
4254}
4255
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4256static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4257 int idx,
4258 int edge,
4259 bool is2GHz)
4260{
4261 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4262 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4263
4264 if (is2GHz)
4265 return ctl_2g[idx].ctlEdges[edge].tPower;
4266 else
4267 return ctl_5g[idx].ctlEdges[edge].tPower;
4268}
4269
4270static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4271 int idx,
4272 unsigned int edge,
4273 u16 freq,
4274 bool is2GHz)
4275{
4276 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4277 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4278
4279 u8 *ctl_freqbin = is2GHz ?
4280 &eep->ctl_freqbin_2G[idx][0] :
4281 &eep->ctl_freqbin_5G[idx][0];
4282
4283 if (is2GHz) {
4284 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4285 ctl_2g[idx].ctlEdges[edge - 1].flag)
4286 return ctl_2g[idx].ctlEdges[edge - 1].tPower;
4287 } else {
4288 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4289 ctl_5g[idx].ctlEdges[edge - 1].flag)
4290 return ctl_5g[idx].ctlEdges[edge - 1].tPower;
4291 }
4292
4293 return AR9300_MAX_RATE_POWER;
4294}
4295
4296/*
4297 * Find the maximum conformance test limit for the given channel and CTL info
4298 */
4299static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4300 u16 freq, int idx, bool is2GHz)
4301{
4302 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4303 u8 *ctl_freqbin = is2GHz ?
4304 &eep->ctl_freqbin_2G[idx][0] :
4305 &eep->ctl_freqbin_5G[idx][0];
4306 u16 num_edges = is2GHz ?
4307 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4308 unsigned int edge;
4309
4310 /* Get the edge power */
4311 for (edge = 0;
4312 (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
4313 edge++) {
4314 /*
4315 * If there's an exact channel match or an inband flag set
4316 * on the lower channel use the given rdEdgePower
4317 */
4318 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4319 twiceMaxEdgePower =
4320 ar9003_hw_get_direct_edge_power(eep, idx,
4321 edge, is2GHz);
4322 break;
4323 } else if ((edge > 0) &&
4324 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4325 is2GHz))) {
4326 twiceMaxEdgePower =
4327 ar9003_hw_get_indirect_edge_power(eep, idx,
4328 edge, freq,
4329 is2GHz);
4330 /*
4331 * Leave loop - no more affecting edges possible in
4332 * this monotonic increasing list
4333 */
4334 break;
4335 }
4336 }
4337 return twiceMaxEdgePower;
4338}
4339
4340static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4341 struct ath9k_channel *chan,
4342 u8 *pPwrArray, u16 cfgCtl,
4343 u8 twiceAntennaReduction,
4344 u8 twiceMaxRegulatoryPower,
4345 u16 powerLimit)
4346{
4347 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4348 struct ath_common *common = ath9k_hw_common(ah);
4349 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4350 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4351 static const u16 tpScaleReductionTable[5] = {
4352 0, 3, 6, 9, AR9300_MAX_RATE_POWER
4353 };
4354 int i;
4355 int16_t twiceLargestAntenna;
4356 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4357 u16 ctlModesFor11a[] = {
4358 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4359 };
4360 u16 ctlModesFor11g[] = {
4361 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4362 CTL_11G_EXT, CTL_2GHT40
4363 };
4364 u16 numCtlModes, *pCtlMode, ctlMode, freq;
4365 struct chan_centers centers;
4366 u8 *ctlIndex;
4367 u8 ctlNum;
4368 u16 twiceMinEdgePower;
4369 bool is2ghz = IS_CHAN_2GHZ(chan);
4370
4371 ath9k_hw_get_channel_centers(ah, chan, &centers);
4372
4373 /* Compute TxPower reduction due to Antenna Gain */
4374 if (is2ghz)
4375 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4376 else
4377 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4378
4379 twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4380 twiceLargestAntenna, 0);
4381
4382 /*
4383 * scaledPower is the minimum of the user input power level
4384 * and the regulatory allowed power level
4385 */
4386 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4387
4388 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4389 maxRegAllowedPower -=
4390 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4391 }
4392
4393 scaledPower = min(powerLimit, maxRegAllowedPower);
4394
4395 /*
4396 * Reduce scaled Power by number of chains active to get
4397 * to per chain tx power level
4398 */
4399 switch (ar5416_get_ntxchains(ah->txchainmask)) {
4400 case 1:
4401 break;
4402 case 2:
4403 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4404 break;
4405 case 3:
4406 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4407 break;
4408 }
4409
4410 scaledPower = max((u16)0, scaledPower);
4411
4412 /*
4413 * Get target powers from EEPROM - our baseline for TX Power
4414 */
4415 if (is2ghz) {
4416 /* Setup for CTL modes */
4417 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4418 numCtlModes =
4419 ARRAY_SIZE(ctlModesFor11g) -
4420 SUB_NUM_CTL_MODES_AT_2G_40;
4421 pCtlMode = ctlModesFor11g;
4422 if (IS_CHAN_HT40(chan))
4423 /* All 2G CTL's */
4424 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4425 } else {
4426 /* Setup for CTL modes */
4427 /* CTL_11A, CTL_5GHT20 */
4428 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4429 SUB_NUM_CTL_MODES_AT_5G_40;
4430 pCtlMode = ctlModesFor11a;
4431 if (IS_CHAN_HT40(chan))
4432 /* All 5G CTL's */
4433 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4434 }
4435
4436 /*
4437 * For MIMO, need to apply regulatory caps individually across
4438 * dynamically running modes: CCK, OFDM, HT20, HT40
4439 *
4440 * The outer loop walks through each possible applicable runtime mode.
4441 * The inner loop walks through each ctlIndex entry in EEPROM.
4442 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4443 */
4444 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4445 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4446 (pCtlMode[ctlMode] == CTL_2GHT40);
4447 if (isHt40CtlMode)
4448 freq = centers.synth_center;
4449 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4450 freq = centers.ext_center;
4451 else
4452 freq = centers.ctl_center;
4453
4454 ath_print(common, ATH_DBG_REGULATORY,
4455 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4456 "EXT_ADDITIVE %d\n",
4457 ctlMode, numCtlModes, isHt40CtlMode,
4458 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4459
4460 /* walk through each CTL index stored in EEPROM */
4461 if (is2ghz) {
4462 ctlIndex = pEepData->ctlIndex_2G;
4463 ctlNum = AR9300_NUM_CTLS_2G;
4464 } else {
4465 ctlIndex = pEepData->ctlIndex_5G;
4466 ctlNum = AR9300_NUM_CTLS_5G;
4467 }
4468
4469 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4470 ath_print(common, ATH_DBG_REGULATORY,
4471 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4472 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4473 "chan %dn",
4474 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4475 chan->channel);
4476
4477 /*
4478 * compare test group from regulatory
4479 * channel list with test mode from pCtlMode
4480 * list
4481 */
4482 if ((((cfgCtl & ~CTL_MODE_M) |
4483 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4484 ctlIndex[i]) ||
4485 (((cfgCtl & ~CTL_MODE_M) |
4486 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4487 ((ctlIndex[i] & CTL_MODE_M) |
4488 SD_NO_CTL))) {
4489 twiceMinEdgePower =
4490 ar9003_hw_get_max_edge_power(pEepData,
4491 freq, i,
4492 is2ghz);
4493
4494 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4495 /*
4496 * Find the minimum of all CTL
4497 * edge powers that apply to
4498 * this channel
4499 */
4500 twiceMaxEdgePower =
4501 min(twiceMaxEdgePower,
4502 twiceMinEdgePower);
4503 else {
4504 /* specific */
4505 twiceMaxEdgePower =
4506 twiceMinEdgePower;
4507 break;
4508 }
4509 }
4510 }
4511
4512 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4513
4514 ath_print(common, ATH_DBG_REGULATORY,
4515 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d "
4516 "sP %d minCtlPwr %d\n",
4517 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4518 scaledPower, minCtlPower);
4519
4520 /* Apply ctl mode to correct target power set */
4521 switch (pCtlMode[ctlMode]) {
4522 case CTL_11B:
4523 for (i = ALL_TARGET_LEGACY_1L_5L;
4524 i <= ALL_TARGET_LEGACY_11S; i++)
4525 pPwrArray[i] =
4526 (u8)min((u16)pPwrArray[i],
4527 minCtlPower);
4528 break;
4529 case CTL_11A:
4530 case CTL_11G:
4531 for (i = ALL_TARGET_LEGACY_6_24;
4532 i <= ALL_TARGET_LEGACY_54; i++)
4533 pPwrArray[i] =
4534 (u8)min((u16)pPwrArray[i],
4535 minCtlPower);
4536 break;
4537 case CTL_5GHT20:
4538 case CTL_2GHT20:
4539 for (i = ALL_TARGET_HT20_0_8_16;
4540 i <= ALL_TARGET_HT20_21; i++)
4541 pPwrArray[i] =
4542 (u8)min((u16)pPwrArray[i],
4543 minCtlPower);
4544 pPwrArray[ALL_TARGET_HT20_22] =
4545 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4546 minCtlPower);
4547 pPwrArray[ALL_TARGET_HT20_23] =
4548 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4549 minCtlPower);
4550 break;
4551 case CTL_5GHT40:
4552 case CTL_2GHT40:
4553 for (i = ALL_TARGET_HT40_0_8_16;
4554 i <= ALL_TARGET_HT40_23; i++)
4555 pPwrArray[i] =
4556 (u8)min((u16)pPwrArray[i],
4557 minCtlPower);
4558 break;
4559 default:
4560 break;
4561 }
4562 } /* end ctl mode checking */
4563}
4564
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4565static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4566 struct ath9k_channel *chan, u16 cfgCtl,
4567 u8 twiceAntennaReduction,
4568 u8 twiceMaxRegulatoryPower,
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4569 u8 powerLimit, bool test)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4570{
Felix Fietkau6b7b6cf2010-10-20 02:09:44 +0200[diff] [blame]4571 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4572 struct ath_common *common = ath9k_hw_common(ah);
4573 u8 targetPowerValT2[ar9300RateSize];
4574 unsigned int i = 0;
4575
4576 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4577 ar9003_hw_set_power_per_rate_table(ah, chan,
4578 targetPowerValT2, cfgCtl,
4579 twiceAntennaReduction,
4580 twiceMaxRegulatoryPower,
4581 powerLimit);
4582
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4583 regulatory->max_power_level = 0;
4584 for (i = 0; i < ar9300RateSize; i++) {
4585 if (targetPowerValT2[i] > regulatory->max_power_level)
4586 regulatory->max_power_level = targetPowerValT2[i];
4587 }
4588
4589 if (test)
4590 return;
4591
4592 for (i = 0; i < ar9300RateSize; i++) {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4593 ath_print(common, ATH_DBG_EEPROM,
4594 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4595 i++;
4596 ath_print(common, ATH_DBG_EEPROM,
4597 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4598 i++;
4599 ath_print(common, ATH_DBG_EEPROM,
4600 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4601 i++;
4602 ath_print(common, ATH_DBG_EEPROM,
4603 "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]);
4604 i++;
4605 }
4606
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4607 /*
4608 * This is the TX power we send back to driver core,
4609 * and it can use to pass to userspace to display our
4610 * currently configured TX power setting.
4611 *
4612 * Since power is rate dependent, use one of the indices
4613 * from the AR9300_Rates enum to select an entry from
4614 * targetPowerValT2[] to report. Currently returns the
4615 * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4616 * as CCK power is less interesting (?).
4617 */
4618 i = ALL_TARGET_LEGACY_6_24; /* legacy */
4619 if (IS_CHAN_HT40(chan))
4620 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4621 else if (IS_CHAN_HT20(chan))
4622 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4623
4624 ah->txpower_limit = targetPowerValT2[i];
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4625 regulatory->max_power_level = targetPowerValT2[i];
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4626
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4627 /* Write target power array to registers */
4628 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4629 ar9003_hw_calibration_apply(ah, chan->channel);
4630}
4631
4632static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
4633 u16 i, bool is2GHz)
4634{
4635 return AR_NO_SPUR;
4636}
4637
Luis R. Rodriguezc14a85d2010-04-15 17:39:21 -0400[diff] [blame]4638s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4639{
4640 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4641
4642 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4643}
4644
4645s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4646{
4647 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4648
4649 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4650}
4651
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4652const struct eeprom_ops eep_ar9300_ops = {
4653 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4654 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
4655 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
4656 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
4657 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
4658 .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
4659 .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
4660 .set_board_values = ath9k_hw_ar9300_set_board_values,
4661 .set_addac = ath9k_hw_ar9300_set_addac,
4662 .set_txpower = ath9k_hw_ar9300_set_txpower,
4663 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
4664};