Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. |
| 3 | * http://www.samsung.com |
| 4 | * |
| 5 | * Common Codes for S5P64X0 machines |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/types.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/list.h> |
| 16 | #include <linux/timer.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/clk.h> |
| 19 | #include <linux/io.h> |
Linus Torvalds | 7affca3 | 2012-01-07 12:03:30 -0800 | [diff] [blame] | 20 | #include <linux/device.h> |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 21 | #include <linux/serial_core.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/sched.h> |
| 24 | #include <linux/dma-mapping.h> |
| 25 | #include <linux/gpio.h> |
| 26 | #include <linux/irq.h> |
| 27 | |
| 28 | #include <asm/irq.h> |
| 29 | #include <asm/proc-fns.h> |
| 30 | #include <asm/mach/arch.h> |
| 31 | #include <asm/mach/map.h> |
| 32 | #include <asm/mach/irq.h> |
| 33 | |
| 34 | #include <mach/map.h> |
| 35 | #include <mach/hardware.h> |
| 36 | #include <mach/regs-clock.h> |
| 37 | #include <mach/regs-gpio.h> |
| 38 | |
| 39 | #include <plat/cpu.h> |
| 40 | #include <plat/clock.h> |
| 41 | #include <plat/devs.h> |
| 42 | #include <plat/pm.h> |
Arnd Bergmann | 142f210 | 2012-01-09 16:14:07 +0000 | [diff] [blame] | 43 | #include <plat/sdhci.h> |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 44 | #include <plat/adc-core.h> |
| 45 | #include <plat/fb-core.h> |
| 46 | #include <plat/gpio-cfg.h> |
| 47 | #include <plat/regs-irqtype.h> |
| 48 | #include <plat/regs-serial.h> |
Kukjin Kim | 73aed8b | 2011-12-22 23:34:25 +0100 | [diff] [blame] | 49 | #include <plat/watchdog-reset.h> |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 50 | |
| 51 | #include "common.h" |
| 52 | |
| 53 | static const char name_s5p6440[] = "S5P6440"; |
| 54 | static const char name_s5p6450[] = "S5P6450"; |
| 55 | |
| 56 | static struct cpu_table cpu_ids[] __initdata = { |
| 57 | { |
| 58 | .idcode = S5P6440_CPU_ID, |
| 59 | .idmask = S5P64XX_CPU_MASK, |
| 60 | .map_io = s5p6440_map_io, |
| 61 | .init_clocks = s5p6440_init_clocks, |
| 62 | .init_uarts = s5p6440_init_uarts, |
| 63 | .init = s5p64x0_init, |
| 64 | .name = name_s5p6440, |
| 65 | }, { |
| 66 | .idcode = S5P6450_CPU_ID, |
| 67 | .idmask = S5P64XX_CPU_MASK, |
| 68 | .map_io = s5p6450_map_io, |
| 69 | .init_clocks = s5p6450_init_clocks, |
| 70 | .init_uarts = s5p6450_init_uarts, |
| 71 | .init = s5p64x0_init, |
| 72 | .name = name_s5p6450, |
| 73 | }, |
| 74 | }; |
| 75 | |
| 76 | /* Initial IO mappings */ |
| 77 | |
| 78 | static struct map_desc s5p64x0_iodesc[] __initdata = { |
| 79 | { |
| 80 | .virtual = (unsigned long)S5P_VA_CHIPID, |
| 81 | .pfn = __phys_to_pfn(S5P64X0_PA_CHIPID), |
| 82 | .length = SZ_4K, |
| 83 | .type = MT_DEVICE, |
| 84 | }, { |
| 85 | .virtual = (unsigned long)S3C_VA_SYS, |
| 86 | .pfn = __phys_to_pfn(S5P64X0_PA_SYSCON), |
| 87 | .length = SZ_64K, |
| 88 | .type = MT_DEVICE, |
| 89 | }, { |
| 90 | .virtual = (unsigned long)S3C_VA_TIMER, |
| 91 | .pfn = __phys_to_pfn(S5P64X0_PA_TIMER), |
| 92 | .length = SZ_16K, |
| 93 | .type = MT_DEVICE, |
| 94 | }, { |
| 95 | .virtual = (unsigned long)S3C_VA_WATCHDOG, |
| 96 | .pfn = __phys_to_pfn(S5P64X0_PA_WDT), |
| 97 | .length = SZ_4K, |
| 98 | .type = MT_DEVICE, |
| 99 | }, { |
| 100 | .virtual = (unsigned long)S5P_VA_SROMC, |
| 101 | .pfn = __phys_to_pfn(S5P64X0_PA_SROMC), |
| 102 | .length = SZ_4K, |
| 103 | .type = MT_DEVICE, |
| 104 | }, { |
| 105 | .virtual = (unsigned long)S5P_VA_GPIO, |
| 106 | .pfn = __phys_to_pfn(S5P64X0_PA_GPIO), |
| 107 | .length = SZ_4K, |
| 108 | .type = MT_DEVICE, |
| 109 | }, { |
| 110 | .virtual = (unsigned long)VA_VIC0, |
| 111 | .pfn = __phys_to_pfn(S5P64X0_PA_VIC0), |
| 112 | .length = SZ_16K, |
| 113 | .type = MT_DEVICE, |
| 114 | }, { |
| 115 | .virtual = (unsigned long)VA_VIC1, |
| 116 | .pfn = __phys_to_pfn(S5P64X0_PA_VIC1), |
| 117 | .length = SZ_16K, |
| 118 | .type = MT_DEVICE, |
| 119 | }, |
| 120 | }; |
| 121 | |
| 122 | static struct map_desc s5p6440_iodesc[] __initdata = { |
| 123 | { |
| 124 | .virtual = (unsigned long)S3C_VA_UART, |
| 125 | .pfn = __phys_to_pfn(S5P6440_PA_UART(0)), |
| 126 | .length = SZ_4K, |
| 127 | .type = MT_DEVICE, |
| 128 | }, |
| 129 | }; |
| 130 | |
| 131 | static struct map_desc s5p6450_iodesc[] __initdata = { |
| 132 | { |
| 133 | .virtual = (unsigned long)S3C_VA_UART, |
| 134 | .pfn = __phys_to_pfn(S5P6450_PA_UART(0)), |
| 135 | .length = SZ_512K, |
| 136 | .type = MT_DEVICE, |
| 137 | }, { |
| 138 | .virtual = (unsigned long)S3C_VA_UART + SZ_512K, |
| 139 | .pfn = __phys_to_pfn(S5P6450_PA_UART(5)), |
| 140 | .length = SZ_4K, |
| 141 | .type = MT_DEVICE, |
| 142 | }, |
| 143 | }; |
| 144 | |
| 145 | static void s5p64x0_idle(void) |
| 146 | { |
| 147 | unsigned long val; |
| 148 | |
| 149 | if (!need_resched()) { |
| 150 | val = __raw_readl(S5P64X0_PWR_CFG); |
| 151 | val &= ~(0x3 << 5); |
| 152 | val |= (0x1 << 5); |
| 153 | __raw_writel(val, S5P64X0_PWR_CFG); |
| 154 | |
| 155 | cpu_do_idle(); |
| 156 | } |
| 157 | local_irq_enable(); |
| 158 | } |
| 159 | |
| 160 | /* |
| 161 | * s5p64x0_map_io |
| 162 | * |
| 163 | * register the standard CPU IO areas |
| 164 | */ |
| 165 | |
| 166 | void __init s5p64x0_init_io(struct map_desc *mach_desc, int size) |
| 167 | { |
| 168 | /* initialize the io descriptors we need for initialization */ |
| 169 | iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); |
| 170 | if (mach_desc) |
| 171 | iotable_init(mach_desc, size); |
| 172 | |
| 173 | /* detect cpu id and rev. */ |
| 174 | s5p_init_cpu(S5P64X0_SYS_ID); |
| 175 | |
| 176 | s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); |
| 177 | } |
| 178 | |
| 179 | void __init s5p6440_map_io(void) |
| 180 | { |
| 181 | /* initialize any device information early */ |
| 182 | s3c_adc_setname("s3c64xx-adc"); |
| 183 | s3c_fb_setname("s5p64x0-fb"); |
| 184 | |
Arnd Bergmann | 142f210 | 2012-01-09 16:14:07 +0000 | [diff] [blame] | 185 | s5p64x0_default_sdhci0(); |
| 186 | s5p64x0_default_sdhci1(); |
| 187 | s5p6440_default_sdhci2(); |
| 188 | |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 189 | iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc)); |
| 190 | init_consistent_dma_size(SZ_8M); |
| 191 | } |
| 192 | |
| 193 | void __init s5p6450_map_io(void) |
| 194 | { |
| 195 | /* initialize any device information early */ |
| 196 | s3c_adc_setname("s3c64xx-adc"); |
| 197 | s3c_fb_setname("s5p64x0-fb"); |
| 198 | |
Arnd Bergmann | 142f210 | 2012-01-09 16:14:07 +0000 | [diff] [blame] | 199 | s5p64x0_default_sdhci0(); |
| 200 | s5p64x0_default_sdhci1(); |
| 201 | s5p6450_default_sdhci2(); |
| 202 | |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 203 | iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); |
| 204 | init_consistent_dma_size(SZ_8M); |
| 205 | } |
| 206 | |
| 207 | /* |
| 208 | * s5p64x0_init_clocks |
| 209 | * |
| 210 | * register and setup the CPU clocks |
| 211 | */ |
| 212 | |
| 213 | void __init s5p6440_init_clocks(int xtal) |
| 214 | { |
| 215 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); |
| 216 | |
| 217 | s3c24xx_register_baseclocks(xtal); |
| 218 | s5p_register_clocks(xtal); |
| 219 | s5p6440_register_clocks(); |
| 220 | s5p6440_setup_clocks(); |
| 221 | } |
| 222 | |
| 223 | void __init s5p6450_init_clocks(int xtal) |
| 224 | { |
| 225 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); |
| 226 | |
| 227 | s3c24xx_register_baseclocks(xtal); |
| 228 | s5p_register_clocks(xtal); |
| 229 | s5p6450_register_clocks(); |
| 230 | s5p6450_setup_clocks(); |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * s5p64x0_init_irq |
| 235 | * |
| 236 | * register the CPU interrupts |
| 237 | */ |
| 238 | |
| 239 | void __init s5p6440_init_irq(void) |
| 240 | { |
| 241 | /* S5P6440 supports 2 VIC */ |
| 242 | u32 vic[2]; |
| 243 | |
| 244 | /* |
| 245 | * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)] |
| 246 | * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22] |
| 247 | */ |
| 248 | vic[0] = 0xff800ae7; |
| 249 | vic[1] = 0xffbf23e5; |
| 250 | |
| 251 | s5p_init_irq(vic, ARRAY_SIZE(vic)); |
| 252 | } |
| 253 | |
| 254 | void __init s5p6450_init_irq(void) |
| 255 | { |
| 256 | /* S5P6450 supports only 2 VIC */ |
| 257 | u32 vic[2]; |
| 258 | |
| 259 | /* |
| 260 | * VIC0 is missing IRQ_VIC0[(13-15), (21-22)] |
| 261 | * VIC1 is missing IRQ VIC1[12, 14, 23] |
| 262 | */ |
| 263 | vic[0] = 0xff9f1fff; |
| 264 | vic[1] = 0xff7fafff; |
| 265 | |
| 266 | s5p_init_irq(vic, ARRAY_SIZE(vic)); |
| 267 | } |
| 268 | |
Linus Torvalds | 7affca3 | 2012-01-07 12:03:30 -0800 | [diff] [blame] | 269 | struct bus_type s5p64x0_subsys = { |
| 270 | .name = "s5p64x0-core", |
| 271 | .dev_name = "s5p64x0-core", |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 272 | }; |
| 273 | |
Linus Torvalds | 7affca3 | 2012-01-07 12:03:30 -0800 | [diff] [blame] | 274 | static struct device s5p64x0_dev = { |
| 275 | .bus = &s5p64x0_subsys, |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 276 | }; |
| 277 | |
| 278 | static int __init s5p64x0_core_init(void) |
| 279 | { |
Linus Torvalds | 7affca3 | 2012-01-07 12:03:30 -0800 | [diff] [blame] | 280 | return subsys_system_register(&s5p64x0_subsys, NULL); |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 281 | } |
| 282 | core_initcall(s5p64x0_core_init); |
| 283 | |
| 284 | int __init s5p64x0_init(void) |
| 285 | { |
| 286 | printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n"); |
| 287 | |
| 288 | /* set idle function */ |
| 289 | pm_idle = s5p64x0_idle; |
| 290 | |
Linus Torvalds | 7affca3 | 2012-01-07 12:03:30 -0800 | [diff] [blame] | 291 | return device_register(&s5p64x0_dev); |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 292 | } |
| 293 | |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 294 | /* uart registration process */ |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 295 | void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
| 296 | { |
| 297 | int uart; |
| 298 | |
| 299 | for (uart = 0; uart < no; uart++) { |
| 300 | s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart); |
| 301 | s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART; |
| 302 | } |
| 303 | |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 304 | s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); |
| 305 | } |
| 306 | |
| 307 | void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
| 308 | { |
Kukjin Kim | 95af214 | 2011-12-22 23:28:28 +0100 | [diff] [blame] | 309 | s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); |
| 310 | } |
| 311 | |
| 312 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) |
| 313 | |
| 314 | static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type) |
| 315 | { |
| 316 | int offs = eint_offset(data->irq); |
| 317 | int shift; |
| 318 | u32 ctrl, mask; |
| 319 | u32 newvalue = 0; |
| 320 | |
| 321 | if (offs > 15) |
| 322 | return -EINVAL; |
| 323 | |
| 324 | switch (type) { |
| 325 | case IRQ_TYPE_NONE: |
| 326 | printk(KERN_WARNING "No edge setting!\n"); |
| 327 | break; |
| 328 | case IRQ_TYPE_EDGE_RISING: |
| 329 | newvalue = S3C2410_EXTINT_RISEEDGE; |
| 330 | break; |
| 331 | case IRQ_TYPE_EDGE_FALLING: |
| 332 | newvalue = S3C2410_EXTINT_FALLEDGE; |
| 333 | break; |
| 334 | case IRQ_TYPE_EDGE_BOTH: |
| 335 | newvalue = S3C2410_EXTINT_BOTHEDGE; |
| 336 | break; |
| 337 | case IRQ_TYPE_LEVEL_LOW: |
| 338 | newvalue = S3C2410_EXTINT_LOWLEV; |
| 339 | break; |
| 340 | case IRQ_TYPE_LEVEL_HIGH: |
| 341 | newvalue = S3C2410_EXTINT_HILEV; |
| 342 | break; |
| 343 | default: |
| 344 | printk(KERN_ERR "No such irq type %d", type); |
| 345 | return -EINVAL; |
| 346 | } |
| 347 | |
| 348 | shift = (offs / 2) * 4; |
| 349 | mask = 0x7 << shift; |
| 350 | |
| 351 | ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask; |
| 352 | ctrl |= newvalue << shift; |
| 353 | __raw_writel(ctrl, S5P64X0_EINT0CON0); |
| 354 | |
| 355 | /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */ |
| 356 | if (soc_is_s5p6450()) |
| 357 | s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2)); |
| 358 | else |
| 359 | s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2)); |
| 360 | |
| 361 | return 0; |
| 362 | } |
| 363 | |
| 364 | /* |
| 365 | * s5p64x0_irq_demux_eint |
| 366 | * |
| 367 | * This function demuxes the IRQ from the group0 external interrupts, |
| 368 | * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into |
| 369 | * the specific handlers s5p64x0_irq_demux_eintX_Y. |
| 370 | */ |
| 371 | static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end) |
| 372 | { |
| 373 | u32 status = __raw_readl(S5P64X0_EINT0PEND); |
| 374 | u32 mask = __raw_readl(S5P64X0_EINT0MASK); |
| 375 | unsigned int irq; |
| 376 | |
| 377 | status &= ~mask; |
| 378 | status >>= start; |
| 379 | status &= (1 << (end - start + 1)) - 1; |
| 380 | |
| 381 | for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { |
| 382 | if (status & 1) |
| 383 | generic_handle_irq(irq); |
| 384 | status >>= 1; |
| 385 | } |
| 386 | } |
| 387 | |
| 388 | static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) |
| 389 | { |
| 390 | s5p64x0_irq_demux_eint(0, 3); |
| 391 | } |
| 392 | |
| 393 | static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) |
| 394 | { |
| 395 | s5p64x0_irq_demux_eint(4, 11); |
| 396 | } |
| 397 | |
| 398 | static void s5p64x0_irq_demux_eint12_15(unsigned int irq, |
| 399 | struct irq_desc *desc) |
| 400 | { |
| 401 | s5p64x0_irq_demux_eint(12, 15); |
| 402 | } |
| 403 | |
| 404 | static int s5p64x0_alloc_gc(void) |
| 405 | { |
| 406 | struct irq_chip_generic *gc; |
| 407 | struct irq_chip_type *ct; |
| 408 | |
| 409 | gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE, |
| 410 | S5P_VA_GPIO, handle_level_irq); |
| 411 | if (!gc) { |
| 412 | printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0" |
| 413 | "external interrupts failed\n", __func__); |
| 414 | return -EINVAL; |
| 415 | } |
| 416 | |
| 417 | ct = gc->chip_types; |
| 418 | ct->chip.irq_ack = irq_gc_ack_set_bit; |
| 419 | ct->chip.irq_mask = irq_gc_mask_set_bit; |
| 420 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; |
| 421 | ct->chip.irq_set_type = s5p64x0_irq_eint_set_type; |
| 422 | ct->chip.irq_set_wake = s3c_irqext_wake; |
| 423 | ct->regs.ack = EINT0PEND_OFFSET; |
| 424 | ct->regs.mask = EINT0MASK_OFFSET; |
| 425 | irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE, |
| 426 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); |
| 427 | return 0; |
| 428 | } |
| 429 | |
| 430 | static int __init s5p64x0_init_irq_eint(void) |
| 431 | { |
| 432 | int ret = s5p64x0_alloc_gc(); |
| 433 | irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3); |
| 434 | irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11); |
| 435 | irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15); |
| 436 | |
| 437 | return ret; |
| 438 | } |
| 439 | arch_initcall(s5p64x0_init_irq_eint); |
Kukjin Kim | 73aed8b | 2011-12-22 23:34:25 +0100 | [diff] [blame] | 440 | |
| 441 | void s5p64x0_restart(char mode, const char *cmd) |
| 442 | { |
| 443 | if (mode != 's') |
| 444 | arch_wdt_reset(); |
| 445 | |
| 446 | soft_restart(0); |
| 447 | } |