Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010 Atheros Communications Inc. |
| 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #ifndef AR9003_MAC_H |
| 18 | #define AR9003_MAC_H |
| 19 | |
Vasanthakumar Thiagarajan | ad7b806 | 2010-04-15 17:38:28 -0400 | [diff] [blame] | 20 | #define AR_DescId 0xffff0000 |
| 21 | #define AR_DescId_S 16 |
| 22 | #define AR_CtrlStat 0x00004000 |
| 23 | #define AR_TxRxDesc 0x00008000 |
| 24 | |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 25 | struct ar9003_rxs { |
| 26 | u32 ds_info; |
| 27 | u32 status1; |
| 28 | u32 status2; |
| 29 | u32 status3; |
| 30 | u32 status4; |
| 31 | u32 status5; |
| 32 | u32 status6; |
| 33 | u32 status7; |
| 34 | u32 status8; |
| 35 | u32 status9; |
| 36 | u32 status10; |
| 37 | u32 status11; |
| 38 | } __packed; |
| 39 | |
Vasanthakumar Thiagarajan | 162c3be | 2010-04-15 17:38:41 -0400 | [diff] [blame^] | 40 | /* Transmit Control Descriptor */ |
| 41 | struct ar9003_txc { |
| 42 | u32 info; /* descriptor information */ |
| 43 | u32 link; /* link pointer */ |
| 44 | u32 data0; /* data pointer to 1st buffer */ |
| 45 | u32 ctl3; /* DMA control 3 */ |
| 46 | u32 data1; /* data pointer to 2nd buffer */ |
| 47 | u32 ctl5; /* DMA control 5 */ |
| 48 | u32 data2; /* data pointer to 3rd buffer */ |
| 49 | u32 ctl7; /* DMA control 7 */ |
| 50 | u32 data3; /* data pointer to 4th buffer */ |
| 51 | u32 ctl9; /* DMA control 9 */ |
| 52 | u32 ctl10; /* DMA control 10 */ |
| 53 | u32 ctl11; /* DMA control 11 */ |
| 54 | u32 ctl12; /* DMA control 12 */ |
| 55 | u32 ctl13; /* DMA control 13 */ |
| 56 | u32 ctl14; /* DMA control 14 */ |
| 57 | u32 ctl15; /* DMA control 15 */ |
| 58 | u32 ctl16; /* DMA control 16 */ |
| 59 | u32 ctl17; /* DMA control 17 */ |
| 60 | u32 ctl18; /* DMA control 18 */ |
| 61 | u32 ctl19; /* DMA control 19 */ |
| 62 | u32 ctl20; /* DMA control 20 */ |
| 63 | u32 ctl21; /* DMA control 21 */ |
| 64 | u32 ctl22; /* DMA control 22 */ |
| 65 | u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */ |
| 66 | } __packed; |
| 67 | |
Vasanthakumar Thiagarajan | ae3bb6d | 2010-04-15 17:38:27 -0400 | [diff] [blame] | 68 | void ar9003_hw_attach_mac_ops(struct ath_hw *hw); |
Vasanthakumar Thiagarajan | ad7b806 | 2010-04-15 17:38:28 -0400 | [diff] [blame] | 69 | void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size); |
| 70 | void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, |
| 71 | enum ath9k_rx_qtype qtype); |
| 72 | |
| 73 | int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, |
| 74 | struct ath_rx_status *rxs, |
| 75 | void *buf_addr); |
Vasanthakumar Thiagarajan | ae3bb6d | 2010-04-15 17:38:27 -0400 | [diff] [blame] | 76 | |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 77 | #endif |