Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Driver for DBRI sound chip found on Sparcs. |
| 3 | * Copyright (C) 2004 Martin Habets (mhabets@users.sourceforge.net) |
| 4 | * |
| 5 | * Based entirely upon drivers/sbus/audio/dbri.c which is: |
| 6 | * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) |
| 7 | * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org) |
| 8 | * |
| 9 | * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO |
| 10 | * on Sun SPARCstation 10, 20, LX and Voyager models. |
| 11 | * |
| 12 | * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel |
| 13 | * data time multiplexer with ISDN support (aka T7259) |
| 14 | * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel. |
| 15 | * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?). |
| 16 | * Documentation: |
| 17 | * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from |
| 18 | * Sparc Technology Business (courtesy of Sun Support) |
| 19 | * - Data sheet of the T7903, a newer but very similar ISA bus equivalent |
| 20 | * available from the Lucent (formarly AT&T microelectronics) home |
| 21 | * page. |
| 22 | * - http://www.freesoft.org/Linux/DBRI/ |
| 23 | * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec |
| 24 | * Interfaces: CHI, Audio In & Out, 2 bits parallel |
| 25 | * Documentation: from the Crystal Semiconductor home page. |
| 26 | * |
| 27 | * The DBRI is a 32 pipe machine, each pipe can transfer some bits between |
| 28 | * memory and a serial device (long pipes, nr 0-15) or between two serial |
| 29 | * devices (short pipes, nr 16-31), or simply send a fixed data to a serial |
| 30 | * device (short pipes). |
| 31 | * A timeslot defines the bit-offset and nr of bits read from a serial device. |
| 32 | * The timeslots are linked to 6 circular lists, one for each direction for |
| 33 | * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes |
| 34 | * (the second one is a monitor/tee pipe, valid only for serial input). |
| 35 | * |
| 36 | * The mmcodec is connected via the CHI bus and needs the data & some |
| 37 | * parameters (volume, balance, output selection) timemultiplexed in 8 byte |
| 38 | * chunks. It also has a control mode, which serves for audio format setting. |
| 39 | * |
| 40 | * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on |
| 41 | * the same CHI bus, so I thought perhaps it is possible to use the onboard |
| 42 | * & the speakerbox codec simultanously, giving 2 (not very independent :-) |
| 43 | * audio devices. But the SUN HW group decided against it, at least on my |
| 44 | * LX the speakerbox connector has at least 1 pin missing and 1 wrongly |
| 45 | * connected. |
| 46 | */ |
| 47 | |
| 48 | #include <sound/driver.h> |
| 49 | #include <linux/interrupt.h> |
| 50 | #include <linux/delay.h> |
| 51 | |
| 52 | #include <sound/core.h> |
| 53 | #include <sound/pcm.h> |
| 54 | #include <sound/pcm_params.h> |
| 55 | #include <sound/info.h> |
| 56 | #include <sound/control.h> |
| 57 | #include <sound/initval.h> |
| 58 | |
| 59 | #include <asm/irq.h> |
| 60 | #include <asm/io.h> |
| 61 | #include <asm/sbus.h> |
| 62 | #include <asm/atomic.h> |
| 63 | |
| 64 | MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets"); |
| 65 | MODULE_DESCRIPTION("Sun DBRI"); |
| 66 | MODULE_LICENSE("GPL"); |
| 67 | MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}"); |
| 68 | |
| 69 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
| 70 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ |
| 71 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ |
| 72 | |
| 73 | module_param_array(index, int, NULL, 0444); |
| 74 | MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard."); |
| 75 | module_param_array(id, charp, NULL, 0444); |
| 76 | MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard."); |
| 77 | module_param_array(enable, bool, NULL, 0444); |
| 78 | MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard."); |
| 79 | |
| 80 | #define DBRI_DEBUG |
| 81 | |
| 82 | #define D_INT (1<<0) |
| 83 | #define D_GEN (1<<1) |
| 84 | #define D_CMD (1<<2) |
| 85 | #define D_MM (1<<3) |
| 86 | #define D_USR (1<<4) |
| 87 | #define D_DESC (1<<5) |
| 88 | |
| 89 | static int dbri_debug = 0; |
| 90 | module_param(dbri_debug, int, 0444); |
| 91 | MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard."); |
| 92 | |
| 93 | #ifdef DBRI_DEBUG |
| 94 | static char *cmds[] = { |
| 95 | "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS", |
| 96 | "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV" |
| 97 | }; |
| 98 | |
| 99 | #define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x) |
| 100 | |
| 101 | #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \ |
| 102 | (1 << 27) | \ |
| 103 | value) |
| 104 | #else |
| 105 | #define dprintk(a, x...) |
| 106 | |
| 107 | #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \ |
| 108 | (intr << 27) | \ |
| 109 | value) |
| 110 | #endif /* DBRI_DEBUG */ |
| 111 | |
| 112 | /*************************************************************************** |
| 113 | CS4215 specific definitions and structures |
| 114 | ****************************************************************************/ |
| 115 | |
| 116 | struct cs4215 { |
| 117 | __u8 data[4]; /* Data mode: Time slots 5-8 */ |
| 118 | __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */ |
| 119 | __u8 onboard; |
| 120 | __u8 offset; /* Bit offset from frame sync to time slot 1 */ |
| 121 | volatile __u32 status; |
| 122 | volatile __u32 version; |
| 123 | __u8 precision; /* In bits, either 8 or 16 */ |
| 124 | __u8 channels; /* 1 or 2 */ |
| 125 | }; |
| 126 | |
| 127 | /* |
| 128 | * Control mode first |
| 129 | */ |
| 130 | |
| 131 | /* Time Slot 1, Status register */ |
| 132 | #define CS4215_CLB (1<<2) /* Control Latch Bit */ |
| 133 | #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */ |
| 134 | /* 0: line: 2.8V, speaker 8V */ |
| 135 | #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */ |
| 136 | #define CS4215_RSRVD_1 (1<<5) |
| 137 | |
| 138 | /* Time Slot 2, Data Format Register */ |
| 139 | #define CS4215_DFR_LINEAR16 0 |
| 140 | #define CS4215_DFR_ULAW 1 |
| 141 | #define CS4215_DFR_ALAW 2 |
| 142 | #define CS4215_DFR_LINEAR8 3 |
| 143 | #define CS4215_DFR_STEREO (1<<2) |
| 144 | static struct { |
| 145 | unsigned short freq; |
| 146 | unsigned char xtal; |
| 147 | unsigned char csval; |
| 148 | } CS4215_FREQ[] = { |
| 149 | { 8000, (1 << 4), (0 << 3) }, |
| 150 | { 16000, (1 << 4), (1 << 3) }, |
| 151 | { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */ |
| 152 | { 32000, (1 << 4), (3 << 3) }, |
| 153 | /* { NA, (1 << 4), (4 << 3) }, */ |
| 154 | /* { NA, (1 << 4), (5 << 3) }, */ |
| 155 | { 48000, (1 << 4), (6 << 3) }, |
| 156 | { 9600, (1 << 4), (7 << 3) }, |
| 157 | { 5513, (2 << 4), (0 << 3) }, /* Actually 5512.5 */ |
| 158 | { 11025, (2 << 4), (1 << 3) }, |
| 159 | { 18900, (2 << 4), (2 << 3) }, |
| 160 | { 22050, (2 << 4), (3 << 3) }, |
| 161 | { 37800, (2 << 4), (4 << 3) }, |
| 162 | { 44100, (2 << 4), (5 << 3) }, |
| 163 | { 33075, (2 << 4), (6 << 3) }, |
| 164 | { 6615, (2 << 4), (7 << 3) }, |
| 165 | { 0, 0, 0} |
| 166 | }; |
| 167 | |
| 168 | #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */ |
| 169 | |
| 170 | #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */ |
| 171 | |
| 172 | /* Time Slot 3, Serial Port Control register */ |
| 173 | #define CS4215_XEN (1<<0) /* 0: Enable serial output */ |
| 174 | #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */ |
| 175 | #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */ |
| 176 | #define CS4215_BSEL_128 (1<<2) |
| 177 | #define CS4215_BSEL_256 (2<<2) |
| 178 | #define CS4215_MCK_MAST (0<<4) /* Master clock */ |
| 179 | #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */ |
| 180 | #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */ |
| 181 | #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */ |
| 182 | #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */ |
| 183 | |
| 184 | /* Time Slot 4, Test Register */ |
| 185 | #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */ |
| 186 | #define CS4215_ENL (1<<1) /* Enable Loopback Testing */ |
| 187 | |
| 188 | /* Time Slot 5, Parallel Port Register */ |
| 189 | /* Read only here and the same as the in data mode */ |
| 190 | |
| 191 | /* Time Slot 6, Reserved */ |
| 192 | |
| 193 | /* Time Slot 7, Version Register */ |
| 194 | #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */ |
| 195 | |
| 196 | /* Time Slot 8, Reserved */ |
| 197 | |
| 198 | /* |
| 199 | * Data mode |
| 200 | */ |
| 201 | /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */ |
| 202 | |
| 203 | /* Time Slot 5, Output Setting */ |
| 204 | #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */ |
| 205 | #define CS4215_LE (1<<6) /* Line Out Enable */ |
| 206 | #define CS4215_HE (1<<7) /* Headphone Enable */ |
| 207 | |
| 208 | /* Time Slot 6, Output Setting */ |
| 209 | #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */ |
| 210 | #define CS4215_SE (1<<6) /* Speaker Enable */ |
| 211 | #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */ |
| 212 | |
| 213 | /* Time Slot 7, Input Setting */ |
| 214 | #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */ |
| 215 | #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */ |
| 216 | #define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */ |
| 217 | #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */ |
| 218 | #define CS4215_PIO1 (1<<7) |
| 219 | |
| 220 | /* Time Slot 8, Input Setting */ |
| 221 | #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */ |
| 222 | #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */ |
| 223 | |
| 224 | /*************************************************************************** |
| 225 | DBRI specific definitions and structures |
| 226 | ****************************************************************************/ |
| 227 | |
| 228 | /* DBRI main registers */ |
| 229 | #define REG0 0x00UL /* Status and Control */ |
| 230 | #define REG1 0x04UL /* Mode and Interrupt */ |
| 231 | #define REG2 0x08UL /* Parallel IO */ |
| 232 | #define REG3 0x0cUL /* Test */ |
| 233 | #define REG8 0x20UL /* Command Queue Pointer */ |
| 234 | #define REG9 0x24UL /* Interrupt Queue Pointer */ |
| 235 | |
| 236 | #define DBRI_NO_CMDS 64 |
| 237 | #define DBRI_NO_INTS 1 /* Note: the value of this define was |
| 238 | * originally 2. The ringbuffer to store |
| 239 | * interrupts in dma is currently broken. |
| 240 | * This is a temporary fix until the ringbuffer |
| 241 | * is fixed. |
| 242 | */ |
| 243 | #define DBRI_INT_BLK 64 |
| 244 | #define DBRI_NO_DESCS 64 |
| 245 | #define DBRI_NO_PIPES 32 |
| 246 | |
| 247 | #define DBRI_MM_ONB 1 |
| 248 | #define DBRI_MM_SB 2 |
| 249 | |
| 250 | #define DBRI_REC 0 |
| 251 | #define DBRI_PLAY 1 |
| 252 | #define DBRI_NO_STREAMS 2 |
| 253 | |
| 254 | /* One transmit/receive descriptor */ |
| 255 | struct dbri_mem { |
| 256 | volatile __u32 word1; |
| 257 | volatile __u32 ba; /* Transmit/Receive Buffer Address */ |
| 258 | volatile __u32 nda; /* Next Descriptor Address */ |
| 259 | volatile __u32 word4; |
| 260 | }; |
| 261 | |
| 262 | /* This structure is in a DMA region where it can accessed by both |
| 263 | * the CPU and the DBRI |
| 264 | */ |
| 265 | struct dbri_dma { |
| 266 | volatile s32 cmd[DBRI_NO_CMDS]; /* Place for commands */ |
| 267 | volatile s32 intr[DBRI_NO_INTS * DBRI_INT_BLK]; /* Interrupt field */ |
| 268 | struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */ |
| 269 | }; |
| 270 | |
| 271 | #define dbri_dma_off(member, elem) \ |
| 272 | ((u32)(unsigned long) \ |
| 273 | (&(((struct dbri_dma *)0)->member[elem]))) |
| 274 | |
| 275 | enum in_or_out { PIPEinput, PIPEoutput }; |
| 276 | |
| 277 | struct dbri_pipe { |
| 278 | u32 sdp; /* SDP command word */ |
| 279 | enum in_or_out direction; |
| 280 | int nextpipe; /* Next pipe in linked list */ |
| 281 | int prevpipe; |
| 282 | int cycle; /* Offset of timeslot (bits) */ |
| 283 | int length; /* Length of timeslot (bits) */ |
| 284 | int first_desc; /* Index of first descriptor */ |
| 285 | int desc; /* Index of active descriptor */ |
| 286 | volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */ |
| 287 | }; |
| 288 | |
| 289 | struct dbri_desc { |
| 290 | int inuse; /* Boolean flag */ |
| 291 | int next; /* Index of next desc, or -1 */ |
| 292 | unsigned int len; |
| 293 | }; |
| 294 | |
| 295 | /* Per stream (playback or record) information */ |
| 296 | typedef struct dbri_streaminfo { |
| 297 | snd_pcm_substream_t *substream; |
| 298 | u32 dvma_buffer; /* Device view of Alsa DMA buffer */ |
| 299 | int left; /* # of bytes left in DMA buffer */ |
| 300 | int size; /* Size of DMA buffer */ |
| 301 | size_t offset; /* offset in user buffer */ |
| 302 | int pipe; /* Data pipe used */ |
| 303 | int left_gain; /* mixer elements */ |
| 304 | int right_gain; |
| 305 | int balance; |
| 306 | } dbri_streaminfo_t; |
| 307 | |
| 308 | /* This structure holds the information for both chips (DBRI & CS4215) */ |
| 309 | typedef struct snd_dbri { |
| 310 | snd_card_t *card; /* ALSA card */ |
| 311 | snd_pcm_t *pcm; |
| 312 | |
| 313 | int regs_size, irq; /* Needed for unload */ |
| 314 | struct sbus_dev *sdev; /* SBUS device info */ |
| 315 | spinlock_t lock; |
| 316 | |
| 317 | volatile struct dbri_dma *dma; /* Pointer to our DMA block */ |
| 318 | u32 dma_dvma; /* DBRI visible DMA address */ |
| 319 | |
| 320 | void __iomem *regs; /* dbri HW regs */ |
| 321 | int dbri_version; /* 'e' and up is OK */ |
| 322 | int dbri_irqp; /* intr queue pointer */ |
| 323 | int wait_seen; |
| 324 | |
| 325 | struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ |
| 326 | struct dbri_desc descs[DBRI_NO_DESCS]; |
| 327 | |
| 328 | int chi_in_pipe; |
| 329 | int chi_out_pipe; |
| 330 | int chi_bpf; |
| 331 | |
| 332 | struct cs4215 mm; /* mmcodec special info */ |
| 333 | /* per stream (playback/record) info */ |
| 334 | struct dbri_streaminfo stream_info[DBRI_NO_STREAMS]; |
| 335 | |
| 336 | struct snd_dbri *next; |
| 337 | } snd_dbri_t; |
| 338 | |
| 339 | /* Needed for the ALSA macros to work */ |
| 340 | #define chip_t snd_dbri_t |
| 341 | |
| 342 | #define DBRI_MAX_VOLUME 63 /* Output volume */ |
| 343 | #define DBRI_MAX_GAIN 15 /* Input gain */ |
| 344 | #define DBRI_RIGHT_BALANCE 255 |
| 345 | #define DBRI_MID_BALANCE (DBRI_RIGHT_BALANCE >> 1) |
| 346 | |
| 347 | /* DBRI Reg0 - Status Control Register - defines. (Page 17) */ |
| 348 | #define D_P (1<<15) /* Program command & queue pointer valid */ |
| 349 | #define D_G (1<<14) /* Allow 4-Word SBus Burst */ |
| 350 | #define D_S (1<<13) /* Allow 16-Word SBus Burst */ |
| 351 | #define D_E (1<<12) /* Allow 8-Word SBus Burst */ |
| 352 | #define D_X (1<<7) /* Sanity Timer Disable */ |
| 353 | #define D_T (1<<6) /* Permit activation of the TE interface */ |
| 354 | #define D_N (1<<5) /* Permit activation of the NT interface */ |
| 355 | #define D_C (1<<4) /* Permit activation of the CHI interface */ |
| 356 | #define D_F (1<<3) /* Force Sanity Timer Time-Out */ |
| 357 | #define D_D (1<<2) /* Disable Master Mode */ |
| 358 | #define D_H (1<<1) /* Halt for Analysis */ |
| 359 | #define D_R (1<<0) /* Soft Reset */ |
| 360 | |
| 361 | /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */ |
| 362 | #define D_LITTLE_END (1<<8) /* Byte Order */ |
| 363 | #define D_BIG_END (0<<8) /* Byte Order */ |
| 364 | #define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */ |
| 365 | #define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */ |
| 366 | #define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */ |
| 367 | #define D_MBE (1<<1) /* Burst Error on SBus (readonly) */ |
| 368 | #define D_IR (1<<0) /* Interrupt Indicator (readonly) */ |
| 369 | |
| 370 | /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */ |
| 371 | #define D_ENPIO3 (1<<7) /* Enable Pin 3 */ |
| 372 | #define D_ENPIO2 (1<<6) /* Enable Pin 2 */ |
| 373 | #define D_ENPIO1 (1<<5) /* Enable Pin 1 */ |
| 374 | #define D_ENPIO0 (1<<4) /* Enable Pin 0 */ |
| 375 | #define D_ENPIO (0xf0) /* Enable all the pins */ |
| 376 | #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */ |
| 377 | #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */ |
| 378 | #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */ |
| 379 | #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */ |
| 380 | |
| 381 | /* DBRI Commands (Page 20) */ |
| 382 | #define D_WAIT 0x0 /* Stop execution */ |
| 383 | #define D_PAUSE 0x1 /* Flush long pipes */ |
| 384 | #define D_JUMP 0x2 /* New command queue */ |
| 385 | #define D_IIQ 0x3 /* Initialize Interrupt Queue */ |
| 386 | #define D_REX 0x4 /* Report command execution via interrupt */ |
| 387 | #define D_SDP 0x5 /* Setup Data Pipe */ |
| 388 | #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */ |
| 389 | #define D_DTS 0x7 /* Define Time Slot */ |
| 390 | #define D_SSP 0x8 /* Set short Data Pipe */ |
| 391 | #define D_CHI 0x9 /* Set CHI Global Mode */ |
| 392 | #define D_NT 0xa /* NT Command */ |
| 393 | #define D_TE 0xb /* TE Command */ |
| 394 | #define D_CDEC 0xc /* Codec setup */ |
| 395 | #define D_TEST 0xd /* No comment */ |
| 396 | #define D_CDM 0xe /* CHI Data mode command */ |
| 397 | |
| 398 | /* Special bits for some commands */ |
| 399 | #define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */ |
| 400 | |
| 401 | /* Setup Data Pipe */ |
| 402 | /* IRM */ |
| 403 | #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */ |
| 404 | #define D_SDP_CHANGE (2<<18) /* Report any changes */ |
| 405 | #define D_SDP_EVERY (3<<18) /* Report any changes */ |
| 406 | #define D_SDP_EOL (1<<17) /* EOL interrupt enable */ |
| 407 | #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */ |
| 408 | |
| 409 | /* Pipe data MODE */ |
| 410 | #define D_SDP_MEM (0<<13) /* To/from memory */ |
| 411 | #define D_SDP_HDLC (2<<13) |
| 412 | #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */ |
| 413 | #define D_SDP_SER (4<<13) /* Serial to serial */ |
| 414 | #define D_SDP_FIXED (6<<13) /* Short only */ |
| 415 | #define D_SDP_MODE(v) ((v)&(7<<13)) |
| 416 | |
| 417 | #define D_SDP_TO_SER (1<<12) /* Direction */ |
| 418 | #define D_SDP_FROM_SER (0<<12) /* Direction */ |
| 419 | #define D_SDP_MSB (1<<11) /* Bit order within Byte */ |
| 420 | #define D_SDP_LSB (0<<11) /* Bit order within Byte */ |
| 421 | #define D_SDP_P (1<<10) /* Pointer Valid */ |
| 422 | #define D_SDP_A (1<<8) /* Abort */ |
| 423 | #define D_SDP_C (1<<7) /* Clear */ |
| 424 | |
| 425 | /* Define Time Slot */ |
| 426 | #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */ |
| 427 | #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */ |
| 428 | #define D_DTS_INS (1<<15) /* Insert Time Slot */ |
| 429 | #define D_DTS_DEL (0<<15) /* Delete Time Slot */ |
| 430 | #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */ |
| 431 | #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */ |
| 432 | |
| 433 | /* Time Slot defines */ |
| 434 | #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */ |
| 435 | #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */ |
| 436 | #define D_TS_DI (1<<13) /* Data Invert */ |
| 437 | #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */ |
| 438 | #define D_TS_MONITOR (2<<10) /* Monitor pipe */ |
| 439 | #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */ |
| 440 | #define D_TS_ANCHOR (7<<10) /* Starting short pipes */ |
| 441 | #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */ |
| 442 | #define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */ |
| 443 | |
| 444 | /* Concentration Highway Interface Modes */ |
| 445 | #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */ |
| 446 | #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */ |
| 447 | #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */ |
| 448 | #define D_CHI_OD (1<<13) /* Open Drain Enable */ |
| 449 | #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */ |
| 450 | #define D_CHI_FD (1<<11) /* Frame Drive */ |
| 451 | #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */ |
| 452 | |
| 453 | /* NT: These are here for completeness */ |
| 454 | #define D_NT_FBIT (1<<17) /* Frame Bit */ |
| 455 | #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */ |
| 456 | #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */ |
| 457 | #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */ |
| 458 | #define D_NT_ISNT (1<<13) /* Configfure interface as NT */ |
| 459 | #define D_NT_FT (1<<12) /* Fixed Timing */ |
| 460 | #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */ |
| 461 | #define D_NT_IFA (1<<10) /* Inhibit Final Activation */ |
| 462 | #define D_NT_ACT (1<<9) /* Activate Interface */ |
| 463 | #define D_NT_MFE (1<<8) /* Multiframe Enable */ |
| 464 | #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */ |
| 465 | #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */ |
| 466 | #define D_NT_FACT (1<<1) /* Force Activation */ |
| 467 | #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */ |
| 468 | |
| 469 | /* Codec Setup */ |
| 470 | #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */ |
| 471 | #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */ |
| 472 | #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */ |
| 473 | |
| 474 | /* Test */ |
| 475 | #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */ |
| 476 | #define D_TEST_SIZE(v) ((v)<<11) /* */ |
| 477 | #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */ |
| 478 | #define D_TEST_PROC 0x6 /* MicroProcessor test */ |
| 479 | #define D_TEST_SER 0x7 /* Serial-Controller test */ |
| 480 | #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */ |
| 481 | #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */ |
| 482 | #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */ |
| 483 | #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */ |
| 484 | #define D_TEST_DUMP 0xe /* ROM Dump */ |
| 485 | |
| 486 | /* CHI Data Mode */ |
| 487 | #define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */ |
| 488 | #define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */ |
| 489 | #define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */ |
| 490 | #define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */ |
| 491 | #define D_CDM_XEN (1<<1) /* Transmit Highway Enable */ |
| 492 | #define D_CDM_REN (1<<0) /* Receive Highway Enable */ |
| 493 | |
| 494 | /* The Interrupts */ |
| 495 | #define D_INTR_BRDY 1 /* Buffer Ready for processing */ |
| 496 | #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */ |
| 497 | #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */ |
| 498 | #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */ |
| 499 | #define D_INTR_EOL 5 /* End of List */ |
| 500 | #define D_INTR_CMDI 6 /* Command has bean read */ |
| 501 | #define D_INTR_XCMP 8 /* Transmission of frame complete */ |
| 502 | #define D_INTR_SBRI 9 /* BRI status change info */ |
| 503 | #define D_INTR_FXDT 10 /* Fixed data change */ |
| 504 | #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */ |
| 505 | #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */ |
| 506 | #define D_INTR_DBYT 12 /* Dropped by frame slip */ |
| 507 | #define D_INTR_RBYT 13 /* Repeated by frame slip */ |
| 508 | #define D_INTR_LINT 14 /* Lost Interrupt */ |
| 509 | #define D_INTR_UNDR 15 /* DMA underrun */ |
| 510 | |
| 511 | #define D_INTR_TE 32 |
| 512 | #define D_INTR_NT 34 |
| 513 | #define D_INTR_CHI 36 |
| 514 | #define D_INTR_CMD 38 |
| 515 | |
| 516 | #define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f) |
| 517 | #define D_INTR_GETCODE(v) (((v)>>20) & 0xf) |
| 518 | #define D_INTR_GETCMD(v) (((v)>>16) & 0xf) |
| 519 | #define D_INTR_GETVAL(v) ((v) & 0xffff) |
| 520 | #define D_INTR_GETRVAL(v) ((v) & 0xfffff) |
| 521 | |
| 522 | #define D_P_0 0 /* TE receive anchor */ |
| 523 | #define D_P_1 1 /* TE transmit anchor */ |
| 524 | #define D_P_2 2 /* NT transmit anchor */ |
| 525 | #define D_P_3 3 /* NT receive anchor */ |
| 526 | #define D_P_4 4 /* CHI send data */ |
| 527 | #define D_P_5 5 /* CHI receive data */ |
| 528 | #define D_P_6 6 /* */ |
| 529 | #define D_P_7 7 /* */ |
| 530 | #define D_P_8 8 /* */ |
| 531 | #define D_P_9 9 /* */ |
| 532 | #define D_P_10 10 /* */ |
| 533 | #define D_P_11 11 /* */ |
| 534 | #define D_P_12 12 /* */ |
| 535 | #define D_P_13 13 /* */ |
| 536 | #define D_P_14 14 /* */ |
| 537 | #define D_P_15 15 /* */ |
| 538 | #define D_P_16 16 /* CHI anchor pipe */ |
| 539 | #define D_P_17 17 /* CHI send */ |
| 540 | #define D_P_18 18 /* CHI receive */ |
| 541 | #define D_P_19 19 /* CHI receive */ |
| 542 | #define D_P_20 20 /* CHI receive */ |
| 543 | #define D_P_21 21 /* */ |
| 544 | #define D_P_22 22 /* */ |
| 545 | #define D_P_23 23 /* */ |
| 546 | #define D_P_24 24 /* */ |
| 547 | #define D_P_25 25 /* */ |
| 548 | #define D_P_26 26 /* */ |
| 549 | #define D_P_27 27 /* */ |
| 550 | #define D_P_28 28 /* */ |
| 551 | #define D_P_29 29 /* */ |
| 552 | #define D_P_30 30 /* */ |
| 553 | #define D_P_31 31 /* */ |
| 554 | |
| 555 | /* Transmit descriptor defines */ |
| 556 | #define DBRI_TD_F (1<<31) /* End of Frame */ |
| 557 | #define DBRI_TD_D (1<<30) /* Do not append CRC */ |
| 558 | #define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */ |
| 559 | #define DBRI_TD_B (1<<15) /* Final interrupt */ |
| 560 | #define DBRI_TD_M (1<<14) /* Marker interrupt */ |
| 561 | #define DBRI_TD_I (1<<13) /* Transmit Idle Characters */ |
| 562 | #define DBRI_TD_FCNT(v) (v) /* Flag Count */ |
| 563 | #define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */ |
| 564 | #define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */ |
| 565 | #define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */ |
| 566 | #define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */ |
| 567 | /* Maximum buffer size per TD: almost 8Kb */ |
| 568 | #define DBRI_TD_MAXCNT ((1 << 13) - 1) |
| 569 | |
| 570 | /* Receive descriptor defines */ |
| 571 | #define DBRI_RD_F (1<<31) /* End of Frame */ |
| 572 | #define DBRI_RD_C (1<<30) /* Completed buffer */ |
| 573 | #define DBRI_RD_B (1<<15) /* Final interrupt */ |
| 574 | #define DBRI_RD_M (1<<14) /* Marker interrupt */ |
| 575 | #define DBRI_RD_BCNT(v) (v) /* Buffer size */ |
| 576 | #define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */ |
| 577 | #define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */ |
| 578 | #define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */ |
| 579 | #define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */ |
| 580 | #define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */ |
| 581 | #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */ |
| 582 | |
| 583 | /* stream_info[] access */ |
| 584 | /* Translate the ALSA direction into the array index */ |
| 585 | #define DBRI_STREAMNO(substream) \ |
| 586 | (substream->stream == \ |
| 587 | SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC) |
| 588 | |
| 589 | /* Return a pointer to dbri_streaminfo */ |
| 590 | #define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)] |
| 591 | |
| 592 | static snd_dbri_t *dbri_list = NULL; /* All DBRI devices */ |
| 593 | |
| 594 | /* |
| 595 | * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr. |
| 596 | * So we have to reverse the bits. Note: not all bit lengths are supported |
| 597 | */ |
| 598 | static __u32 reverse_bytes(__u32 b, int len) |
| 599 | { |
| 600 | switch (len) { |
| 601 | case 32: |
| 602 | b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); |
| 603 | case 16: |
| 604 | b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); |
| 605 | case 8: |
| 606 | b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); |
| 607 | case 4: |
| 608 | b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); |
| 609 | case 2: |
| 610 | b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); |
| 611 | case 1: |
| 612 | case 0: |
| 613 | break; |
| 614 | default: |
| 615 | printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n"); |
| 616 | }; |
| 617 | |
| 618 | return b; |
| 619 | } |
| 620 | |
| 621 | /* |
| 622 | **************************************************************************** |
| 623 | ************** DBRI initialization and command synchronization ************* |
| 624 | **************************************************************************** |
| 625 | |
| 626 | Commands are sent to the DBRI by building a list of them in memory, |
| 627 | then writing the address of the first list item to DBRI register 8. |
| 628 | The list is terminated with a WAIT command, which can generate a |
| 629 | CPU interrupt if required. |
| 630 | |
| 631 | Since the DBRI can run in parallel with the CPU, several means of |
| 632 | synchronization present themselves. The original scheme (Rudolf's) |
| 633 | was to set a flag when we "cmdlock"ed the DBRI, clear the flag when |
| 634 | an interrupt signaled completion, and wait on a wait_queue if a routine |
| 635 | attempted to cmdlock while the flag was set. The problems arose when |
| 636 | we tried to cmdlock from inside an interrupt handler, which might |
| 637 | cause scheduling in an interrupt (if we waited), etc, etc |
| 638 | |
| 639 | A more sophisticated scheme might involve a circular command buffer |
| 640 | or an array of command buffers. A routine could fill one with |
| 641 | commands and link it onto a list. When a interrupt signaled |
| 642 | completion of the current command buffer, look on the list for |
| 643 | the next one. |
| 644 | |
| 645 | I've decided to implement something much simpler - after each command, |
| 646 | the CPU waits for the DBRI to finish the command by polling the P bit |
| 647 | in DBRI register 0. I've tried to implement this in such a way |
| 648 | that might make implementing a more sophisticated scheme easier. |
| 649 | |
| 650 | Every time a routine wants to write commands to the DBRI, it must |
| 651 | first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd |
| 652 | in return. After the commands have been writen, dbri_cmdsend() is |
| 653 | called with the final pointer value. |
| 654 | |
| 655 | */ |
| 656 | |
| 657 | enum dbri_lock_t { NoGetLock, GetLock }; |
| 658 | |
| 659 | static volatile s32 *dbri_cmdlock(snd_dbri_t * dbri, enum dbri_lock_t get) |
| 660 | { |
| 661 | #ifndef SMP |
| 662 | if ((get == GetLock) && spin_is_locked(&dbri->lock)) { |
| 663 | printk(KERN_ERR "DBRI: cmdlock called while in spinlock."); |
| 664 | } |
| 665 | #endif |
| 666 | |
| 667 | /*if (get == GetLock) spin_lock(&dbri->lock); */ |
| 668 | return &dbri->dma->cmd[0]; |
| 669 | } |
| 670 | |
| 671 | static void dbri_process_interrupt_buffer(snd_dbri_t *); |
| 672 | |
| 673 | static void dbri_cmdsend(snd_dbri_t * dbri, volatile s32 * cmd) |
| 674 | { |
| 675 | int MAXLOOPS = 1000000; |
| 676 | int maxloops = MAXLOOPS; |
| 677 | volatile s32 *ptr; |
| 678 | |
| 679 | for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) { |
| 680 | dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); |
| 681 | } |
| 682 | |
| 683 | if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS - 1) { |
| 684 | printk("DBRI: Command buffer overflow! (bug in driver)\n"); |
| 685 | /* Ignore the last part. */ |
| 686 | cmd = &dbri->dma->cmd[DBRI_NO_CMDS - 3]; |
| 687 | } |
| 688 | |
| 689 | *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
| 690 | *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); |
| 691 | dbri->wait_seen = 0; |
| 692 | sbus_writel(dbri->dma_dvma, dbri->regs + REG8); |
| 693 | while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) |
| 694 | barrier(); |
| 695 | if (maxloops == 0) { |
| 696 | printk(KERN_ERR "DBRI: Chip never completed command buffer\n"); |
| 697 | dprintk(D_CMD, "DBRI: Chip never completed command buffer\n"); |
| 698 | } else { |
| 699 | while ((--maxloops) > 0 && (!dbri->wait_seen)) |
| 700 | dbri_process_interrupt_buffer(dbri); |
| 701 | if (maxloops == 0) { |
| 702 | printk(KERN_ERR "DBRI: Chip never acked WAIT\n"); |
| 703 | dprintk(D_CMD, "DBRI: Chip never acked WAIT\n"); |
| 704 | } else { |
| 705 | dprintk(D_CMD, "Chip completed command " |
| 706 | "buffer (%d)\n", MAXLOOPS - maxloops); |
| 707 | } |
| 708 | } |
| 709 | |
| 710 | /*spin_unlock(&dbri->lock); */ |
| 711 | } |
| 712 | |
| 713 | /* Lock must be held when calling this */ |
| 714 | static void dbri_reset(snd_dbri_t * dbri) |
| 715 | { |
| 716 | int i; |
| 717 | |
| 718 | dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n", |
| 719 | sbus_readl(dbri->regs + REG0), |
| 720 | sbus_readl(dbri->regs + REG2), |
| 721 | sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9)); |
| 722 | |
| 723 | sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */ |
| 724 | for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++) |
| 725 | udelay(10); |
| 726 | } |
| 727 | |
| 728 | /* Lock must not be held before calling this */ |
| 729 | static void dbri_initialize(snd_dbri_t * dbri) |
| 730 | { |
| 731 | volatile s32 *cmd; |
| 732 | u32 dma_addr, tmp; |
| 733 | unsigned long flags; |
| 734 | int n; |
| 735 | |
| 736 | spin_lock_irqsave(&dbri->lock, flags); |
| 737 | |
| 738 | dbri_reset(dbri); |
| 739 | |
| 740 | cmd = dbri_cmdlock(dbri, NoGetLock); |
| 741 | dprintk(D_GEN, "init: cmd: %p, int: %p\n", |
| 742 | &dbri->dma->cmd[0], &dbri->dma->intr[0]); |
| 743 | |
| 744 | /* |
| 745 | * Initialize the interrupt ringbuffer. |
| 746 | */ |
| 747 | for (n = 0; n < DBRI_NO_INTS - 1; n++) { |
| 748 | dma_addr = dbri->dma_dvma; |
| 749 | dma_addr += dbri_dma_off(intr, ((n + 1) & DBRI_INT_BLK)); |
| 750 | dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr; |
| 751 | } |
| 752 | dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0); |
| 753 | dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr; |
| 754 | dbri->dbri_irqp = 1; |
| 755 | |
| 756 | /* Initialize pipes */ |
| 757 | for (n = 0; n < DBRI_NO_PIPES; n++) |
| 758 | dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; |
| 759 | |
| 760 | /* We should query the openprom to see what burst sizes this |
| 761 | * SBus supports. For now, just disable all SBus bursts */ |
| 762 | tmp = sbus_readl(dbri->regs + REG0); |
| 763 | tmp &= ~(D_G | D_S | D_E); |
| 764 | sbus_writel(tmp, dbri->regs + REG0); |
| 765 | |
| 766 | /* |
| 767 | * Set up the interrupt queue |
| 768 | */ |
| 769 | dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0); |
| 770 | *(cmd++) = DBRI_CMD(D_IIQ, 0, 0); |
| 771 | *(cmd++) = dma_addr; |
| 772 | |
| 773 | dbri_cmdsend(dbri, cmd); |
| 774 | spin_unlock_irqrestore(&dbri->lock, flags); |
| 775 | } |
| 776 | |
| 777 | /* |
| 778 | **************************************************************************** |
| 779 | ************************** DBRI data pipe management *********************** |
| 780 | **************************************************************************** |
| 781 | |
| 782 | While DBRI control functions use the command and interrupt buffers, the |
| 783 | main data path takes the form of data pipes, which can be short (command |
| 784 | and interrupt driven), or long (attached to DMA buffers). These functions |
| 785 | provide a rudimentary means of setting up and managing the DBRI's pipes, |
| 786 | but the calling functions have to make sure they respect the pipes' linked |
| 787 | list ordering, among other things. The transmit and receive functions |
| 788 | here interface closely with the transmit and receive interrupt code. |
| 789 | |
| 790 | */ |
| 791 | static int pipe_active(snd_dbri_t * dbri, int pipe) |
| 792 | { |
| 793 | return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1)); |
| 794 | } |
| 795 | |
| 796 | /* reset_pipe(dbri, pipe) |
| 797 | * |
| 798 | * Called on an in-use pipe to clear anything being transmitted or received |
| 799 | * Lock must be held before calling this. |
| 800 | */ |
| 801 | static void reset_pipe(snd_dbri_t * dbri, int pipe) |
| 802 | { |
| 803 | int sdp; |
| 804 | int desc; |
| 805 | volatile int *cmd; |
| 806 | |
| 807 | if (pipe < 0 || pipe > 31) { |
| 808 | printk("DBRI: reset_pipe called with illegal pipe number\n"); |
| 809 | return; |
| 810 | } |
| 811 | |
| 812 | sdp = dbri->pipes[pipe].sdp; |
| 813 | if (sdp == 0) { |
| 814 | printk("DBRI: reset_pipe called on uninitialized pipe\n"); |
| 815 | return; |
| 816 | } |
| 817 | |
| 818 | cmd = dbri_cmdlock(dbri, NoGetLock); |
| 819 | *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P); |
| 820 | *(cmd++) = 0; |
| 821 | dbri_cmdsend(dbri, cmd); |
| 822 | |
| 823 | desc = dbri->pipes[pipe].first_desc; |
| 824 | while (desc != -1) { |
| 825 | dbri->descs[desc].inuse = 0; |
| 826 | desc = dbri->descs[desc].next; |
| 827 | } |
| 828 | |
| 829 | dbri->pipes[pipe].desc = -1; |
| 830 | dbri->pipes[pipe].first_desc = -1; |
| 831 | } |
| 832 | |
| 833 | /* FIXME: direction as an argument? */ |
| 834 | static void setup_pipe(snd_dbri_t * dbri, int pipe, int sdp) |
| 835 | { |
| 836 | if (pipe < 0 || pipe > 31) { |
| 837 | printk("DBRI: setup_pipe called with illegal pipe number\n"); |
| 838 | return; |
| 839 | } |
| 840 | |
| 841 | if ((sdp & 0xf800) != sdp) { |
| 842 | printk("DBRI: setup_pipe called with strange SDP value\n"); |
| 843 | /* sdp &= 0xf800; */ |
| 844 | } |
| 845 | |
| 846 | /* If this is a fixed receive pipe, arrange for an interrupt |
| 847 | * every time its data changes |
| 848 | */ |
| 849 | if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER)) |
| 850 | sdp |= D_SDP_CHANGE; |
| 851 | |
| 852 | sdp |= D_PIPE(pipe); |
| 853 | dbri->pipes[pipe].sdp = sdp; |
| 854 | dbri->pipes[pipe].desc = -1; |
| 855 | dbri->pipes[pipe].first_desc = -1; |
| 856 | if (sdp & D_SDP_TO_SER) |
| 857 | dbri->pipes[pipe].direction = PIPEoutput; |
| 858 | else |
| 859 | dbri->pipes[pipe].direction = PIPEinput; |
| 860 | |
| 861 | reset_pipe(dbri, pipe); |
| 862 | } |
| 863 | |
| 864 | /* FIXME: direction not needed */ |
| 865 | static void link_time_slot(snd_dbri_t * dbri, int pipe, |
| 866 | enum in_or_out direction, int basepipe, |
| 867 | int length, int cycle) |
| 868 | { |
| 869 | volatile s32 *cmd; |
| 870 | int val; |
| 871 | int prevpipe; |
| 872 | int nextpipe; |
| 873 | |
| 874 | if (pipe < 0 || pipe > 31 || basepipe < 0 || basepipe > 31) { |
| 875 | printk |
| 876 | ("DBRI: link_time_slot called with illegal pipe number\n"); |
| 877 | return; |
| 878 | } |
| 879 | |
| 880 | if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) { |
| 881 | printk("DBRI: link_time_slot called on uninitialized pipe\n"); |
| 882 | return; |
| 883 | } |
| 884 | |
| 885 | /* Deal with CHI special case: |
| 886 | * "If transmission on edges 0 or 1 is desired, then cycle n |
| 887 | * (where n = # of bit times per frame...) must be used." |
| 888 | * - DBRI data sheet, page 11 |
| 889 | */ |
| 890 | if (basepipe == 16 && direction == PIPEoutput && cycle == 0) |
| 891 | cycle = dbri->chi_bpf; |
| 892 | |
| 893 | if (basepipe == pipe) { |
| 894 | prevpipe = pipe; |
| 895 | nextpipe = pipe; |
| 896 | } else { |
| 897 | /* We're not initializing a new linked list (basepipe != pipe), |
| 898 | * so run through the linked list and find where this pipe |
| 899 | * should be sloted in, based on its cycle. CHI confuses |
| 900 | * things a bit, since it has a single anchor for both its |
| 901 | * transmit and receive lists. |
| 902 | */ |
| 903 | if (basepipe == 16) { |
| 904 | if (direction == PIPEinput) { |
| 905 | prevpipe = dbri->chi_in_pipe; |
| 906 | } else { |
| 907 | prevpipe = dbri->chi_out_pipe; |
| 908 | } |
| 909 | } else { |
| 910 | prevpipe = basepipe; |
| 911 | } |
| 912 | |
| 913 | nextpipe = dbri->pipes[prevpipe].nextpipe; |
| 914 | |
| 915 | while (dbri->pipes[nextpipe].cycle < cycle |
| 916 | && dbri->pipes[nextpipe].nextpipe != basepipe) { |
| 917 | prevpipe = nextpipe; |
| 918 | nextpipe = dbri->pipes[nextpipe].nextpipe; |
| 919 | } |
| 920 | } |
| 921 | |
| 922 | if (prevpipe == 16) { |
| 923 | if (direction == PIPEinput) { |
| 924 | dbri->chi_in_pipe = pipe; |
| 925 | } else { |
| 926 | dbri->chi_out_pipe = pipe; |
| 927 | } |
| 928 | } else { |
| 929 | dbri->pipes[prevpipe].nextpipe = pipe; |
| 930 | } |
| 931 | |
| 932 | dbri->pipes[pipe].nextpipe = nextpipe; |
| 933 | dbri->pipes[pipe].cycle = cycle; |
| 934 | dbri->pipes[pipe].length = length; |
| 935 | |
| 936 | cmd = dbri_cmdlock(dbri, NoGetLock); |
| 937 | |
| 938 | if (direction == PIPEinput) { |
| 939 | val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe; |
| 940 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 941 | *(cmd++) = |
| 942 | D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); |
| 943 | *(cmd++) = 0; |
| 944 | } else { |
| 945 | val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe; |
| 946 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 947 | *(cmd++) = 0; |
| 948 | *(cmd++) = |
| 949 | D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); |
| 950 | } |
| 951 | |
| 952 | dbri_cmdsend(dbri, cmd); |
| 953 | } |
| 954 | |
| 955 | static void unlink_time_slot(snd_dbri_t * dbri, int pipe, |
| 956 | enum in_or_out direction, int prevpipe, |
| 957 | int nextpipe) |
| 958 | { |
| 959 | volatile s32 *cmd; |
| 960 | int val; |
| 961 | |
| 962 | if (pipe < 0 || pipe > 31 || prevpipe < 0 || prevpipe > 31) { |
| 963 | printk |
| 964 | ("DBRI: unlink_time_slot called with illegal pipe number\n"); |
| 965 | return; |
| 966 | } |
| 967 | |
| 968 | cmd = dbri_cmdlock(dbri, NoGetLock); |
| 969 | |
| 970 | if (direction == PIPEinput) { |
| 971 | val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe; |
| 972 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 973 | *(cmd++) = D_TS_NEXT(nextpipe); |
| 974 | *(cmd++) = 0; |
| 975 | } else { |
| 976 | val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe; |
| 977 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 978 | *(cmd++) = 0; |
| 979 | *(cmd++) = D_TS_NEXT(nextpipe); |
| 980 | } |
| 981 | |
| 982 | dbri_cmdsend(dbri, cmd); |
| 983 | } |
| 984 | |
| 985 | /* xmit_fixed() / recv_fixed() |
| 986 | * |
| 987 | * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not |
| 988 | * expected to change much, and which we don't need to buffer. |
| 989 | * The DBRI only interrupts us when the data changes (receive pipes), |
| 990 | * or only changes the data when this function is called (transmit pipes). |
| 991 | * Only short pipes (numbers 16-31) can be used in fixed data mode. |
| 992 | * |
| 993 | * These function operate on a 32-bit field, no matter how large |
| 994 | * the actual time slot is. The interrupt handler takes care of bit |
| 995 | * ordering and alignment. An 8-bit time slot will always end up |
| 996 | * in the low-order 8 bits, filled either MSB-first or LSB-first, |
| 997 | * depending on the settings passed to setup_pipe() |
| 998 | */ |
| 999 | static void xmit_fixed(snd_dbri_t * dbri, int pipe, unsigned int data) |
| 1000 | { |
| 1001 | volatile s32 *cmd; |
| 1002 | |
| 1003 | if (pipe < 16 || pipe > 31) { |
| 1004 | printk("DBRI: xmit_fixed: Illegal pipe number\n"); |
| 1005 | return; |
| 1006 | } |
| 1007 | |
| 1008 | if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) { |
| 1009 | printk("DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe); |
| 1010 | return; |
| 1011 | } |
| 1012 | |
| 1013 | if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { |
| 1014 | printk("DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe); |
| 1015 | return; |
| 1016 | } |
| 1017 | |
| 1018 | if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) { |
| 1019 | printk("DBRI: xmit_fixed: Called on receive pipe %d\n", pipe); |
| 1020 | return; |
| 1021 | } |
| 1022 | |
| 1023 | /* DBRI short pipes always transmit LSB first */ |
| 1024 | |
| 1025 | if (dbri->pipes[pipe].sdp & D_SDP_MSB) |
| 1026 | data = reverse_bytes(data, dbri->pipes[pipe].length); |
| 1027 | |
| 1028 | cmd = dbri_cmdlock(dbri, GetLock); |
| 1029 | |
| 1030 | *(cmd++) = DBRI_CMD(D_SSP, 0, pipe); |
| 1031 | *(cmd++) = data; |
| 1032 | |
| 1033 | dbri_cmdsend(dbri, cmd); |
| 1034 | } |
| 1035 | |
| 1036 | static void recv_fixed(snd_dbri_t * dbri, int pipe, volatile __u32 * ptr) |
| 1037 | { |
| 1038 | if (pipe < 16 || pipe > 31) { |
| 1039 | printk("DBRI: recv_fixed called with illegal pipe number\n"); |
| 1040 | return; |
| 1041 | } |
| 1042 | |
| 1043 | if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { |
| 1044 | printk("DBRI: recv_fixed called on non-fixed pipe %d\n", pipe); |
| 1045 | return; |
| 1046 | } |
| 1047 | |
| 1048 | if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { |
| 1049 | printk("DBRI: recv_fixed called on transmit pipe %d\n", pipe); |
| 1050 | return; |
| 1051 | } |
| 1052 | |
| 1053 | dbri->pipes[pipe].recv_fixed_ptr = ptr; |
| 1054 | } |
| 1055 | |
| 1056 | /* setup_descs() |
| 1057 | * |
| 1058 | * Setup transmit/receive data on a "long" pipe - i.e, one associated |
| 1059 | * with a DMA buffer. |
| 1060 | * |
| 1061 | * Only pipe numbers 0-15 can be used in this mode. |
| 1062 | * |
| 1063 | * This function takes a stream number pointing to a data buffer, |
| 1064 | * and work by building chains of descriptors which identify the |
| 1065 | * data buffers. Buffers too large for a single descriptor will |
| 1066 | * be spread across multiple descriptors. |
| 1067 | */ |
| 1068 | static int setup_descs(snd_dbri_t * dbri, int streamno, unsigned int period) |
| 1069 | { |
| 1070 | dbri_streaminfo_t *info = &dbri->stream_info[streamno]; |
| 1071 | __u32 dvma_buffer; |
| 1072 | int desc = 0; |
| 1073 | int len; |
| 1074 | int first_desc = -1; |
| 1075 | int last_desc = -1; |
| 1076 | |
| 1077 | if (info->pipe < 0 || info->pipe > 15) { |
| 1078 | printk("DBRI: setup_descs: Illegal pipe number\n"); |
| 1079 | return -2; |
| 1080 | } |
| 1081 | |
| 1082 | if (dbri->pipes[info->pipe].sdp == 0) { |
| 1083 | printk("DBRI: setup_descs: Uninitialized pipe %d\n", |
| 1084 | info->pipe); |
| 1085 | return -2; |
| 1086 | } |
| 1087 | |
| 1088 | dvma_buffer = info->dvma_buffer; |
| 1089 | len = info->size; |
| 1090 | |
| 1091 | if (streamno == DBRI_PLAY) { |
| 1092 | if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) { |
| 1093 | printk("DBRI: setup_descs: Called on receive pipe %d\n", |
| 1094 | info->pipe); |
| 1095 | return -2; |
| 1096 | } |
| 1097 | } else { |
| 1098 | if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) { |
| 1099 | printk |
| 1100 | ("DBRI: setup_descs: Called on transmit pipe %d\n", |
| 1101 | info->pipe); |
| 1102 | return -2; |
| 1103 | } |
| 1104 | /* Should be able to queue multiple buffers to receive on a pipe */ |
| 1105 | if (pipe_active(dbri, info->pipe)) { |
| 1106 | printk("DBRI: recv_on_pipe: Called on active pipe %d\n", |
| 1107 | info->pipe); |
| 1108 | return -2; |
| 1109 | } |
| 1110 | |
| 1111 | /* Make sure buffer size is multiple of four */ |
| 1112 | len &= ~3; |
| 1113 | } |
| 1114 | |
| 1115 | while (len > 0) { |
| 1116 | int mylen; |
| 1117 | |
| 1118 | for (; desc < DBRI_NO_DESCS; desc++) { |
| 1119 | if (!dbri->descs[desc].inuse) |
| 1120 | break; |
| 1121 | } |
| 1122 | if (desc == DBRI_NO_DESCS) { |
| 1123 | printk("DBRI: setup_descs: No descriptors\n"); |
| 1124 | return -1; |
| 1125 | } |
| 1126 | |
| 1127 | if (len > DBRI_TD_MAXCNT) { |
| 1128 | mylen = DBRI_TD_MAXCNT; /* 8KB - 1 */ |
| 1129 | } else { |
| 1130 | mylen = len; |
| 1131 | } |
| 1132 | if (mylen > period) { |
| 1133 | mylen = period; |
| 1134 | } |
| 1135 | |
| 1136 | dbri->descs[desc].inuse = 1; |
| 1137 | dbri->descs[desc].next = -1; |
| 1138 | dbri->dma->desc[desc].ba = dvma_buffer; |
| 1139 | dbri->dma->desc[desc].nda = 0; |
| 1140 | |
| 1141 | if (streamno == DBRI_PLAY) { |
| 1142 | dbri->descs[desc].len = mylen; |
| 1143 | dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen); |
| 1144 | dbri->dma->desc[desc].word4 = 0; |
| 1145 | if (first_desc != -1) |
| 1146 | dbri->dma->desc[desc].word1 |= DBRI_TD_M; |
| 1147 | } else { |
| 1148 | dbri->descs[desc].len = 0; |
| 1149 | dbri->dma->desc[desc].word1 = 0; |
| 1150 | dbri->dma->desc[desc].word4 = |
| 1151 | DBRI_RD_B | DBRI_RD_BCNT(mylen); |
| 1152 | } |
| 1153 | |
| 1154 | if (first_desc == -1) { |
| 1155 | first_desc = desc; |
| 1156 | } else { |
| 1157 | dbri->descs[last_desc].next = desc; |
| 1158 | dbri->dma->desc[last_desc].nda = |
| 1159 | dbri->dma_dvma + dbri_dma_off(desc, desc); |
| 1160 | } |
| 1161 | |
| 1162 | last_desc = desc; |
| 1163 | dvma_buffer += mylen; |
| 1164 | len -= mylen; |
| 1165 | } |
| 1166 | |
| 1167 | if (first_desc == -1 || last_desc == -1) { |
| 1168 | printk("DBRI: setup_descs: Not enough descriptors available\n"); |
| 1169 | return -1; |
| 1170 | } |
| 1171 | |
| 1172 | dbri->dma->desc[last_desc].word1 &= ~DBRI_TD_M; |
| 1173 | if (streamno == DBRI_PLAY) { |
| 1174 | dbri->dma->desc[last_desc].word1 |= |
| 1175 | DBRI_TD_I | DBRI_TD_F | DBRI_TD_B; |
| 1176 | } |
| 1177 | dbri->pipes[info->pipe].first_desc = first_desc; |
| 1178 | dbri->pipes[info->pipe].desc = first_desc; |
| 1179 | |
| 1180 | for (desc = first_desc; desc != -1; desc = dbri->descs[desc].next) { |
| 1181 | dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n", |
| 1182 | desc, |
| 1183 | dbri->dma->desc[desc].word1, |
| 1184 | dbri->dma->desc[desc].ba, |
| 1185 | dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4); |
| 1186 | } |
| 1187 | return 0; |
| 1188 | } |
| 1189 | |
| 1190 | /* |
| 1191 | **************************************************************************** |
| 1192 | ************************** DBRI - CHI interface **************************** |
| 1193 | **************************************************************************** |
| 1194 | |
| 1195 | The CHI is a four-wire (clock, frame sync, data in, data out) time-division |
| 1196 | multiplexed serial interface which the DBRI can operate in either master |
| 1197 | (give clock/frame sync) or slave (take clock/frame sync) mode. |
| 1198 | |
| 1199 | */ |
| 1200 | |
| 1201 | enum master_or_slave { CHImaster, CHIslave }; |
| 1202 | |
| 1203 | static void reset_chi(snd_dbri_t * dbri, enum master_or_slave master_or_slave, |
| 1204 | int bits_per_frame) |
| 1205 | { |
| 1206 | volatile s32 *cmd; |
| 1207 | int val; |
| 1208 | static int chi_initialized = 0; /* FIXME: mutex? */ |
| 1209 | |
| 1210 | if (!chi_initialized) { |
| 1211 | |
| 1212 | cmd = dbri_cmdlock(dbri, GetLock); |
| 1213 | |
| 1214 | /* Set CHI Anchor: Pipe 16 */ |
| 1215 | |
| 1216 | val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(16) | D_PIPE(16); |
| 1217 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 1218 | *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); |
| 1219 | *(cmd++) = 0; |
| 1220 | |
| 1221 | val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(16) | D_PIPE(16); |
| 1222 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 1223 | *(cmd++) = 0; |
| 1224 | *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); |
| 1225 | |
| 1226 | dbri->pipes[16].sdp = 1; |
| 1227 | dbri->pipes[16].nextpipe = 16; |
| 1228 | dbri->chi_in_pipe = 16; |
| 1229 | dbri->chi_out_pipe = 16; |
| 1230 | |
| 1231 | #if 0 |
| 1232 | chi_initialized++; |
| 1233 | #endif |
| 1234 | } else { |
| 1235 | int pipe; |
| 1236 | |
| 1237 | for (pipe = dbri->chi_in_pipe; |
| 1238 | pipe != 16; pipe = dbri->pipes[pipe].nextpipe) { |
| 1239 | unlink_time_slot(dbri, pipe, PIPEinput, |
| 1240 | 16, dbri->pipes[pipe].nextpipe); |
| 1241 | } |
| 1242 | for (pipe = dbri->chi_out_pipe; |
| 1243 | pipe != 16; pipe = dbri->pipes[pipe].nextpipe) { |
| 1244 | unlink_time_slot(dbri, pipe, PIPEoutput, |
| 1245 | 16, dbri->pipes[pipe].nextpipe); |
| 1246 | } |
| 1247 | |
| 1248 | dbri->chi_in_pipe = 16; |
| 1249 | dbri->chi_out_pipe = 16; |
| 1250 | |
| 1251 | cmd = dbri_cmdlock(dbri, GetLock); |
| 1252 | } |
| 1253 | |
| 1254 | if (master_or_slave == CHIslave) { |
| 1255 | /* Setup DBRI for CHI Slave - receive clock, frame sync (FS) |
| 1256 | * |
| 1257 | * CHICM = 0 (slave mode, 8 kHz frame rate) |
| 1258 | * IR = give immediate CHI status interrupt |
| 1259 | * EN = give CHI status interrupt upon change |
| 1260 | */ |
| 1261 | *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0)); |
| 1262 | } else { |
| 1263 | /* Setup DBRI for CHI Master - generate clock, FS |
| 1264 | * |
| 1265 | * BPF = bits per 8 kHz frame |
| 1266 | * 12.288 MHz / CHICM_divisor = clock rate |
| 1267 | * FD = 1 - drive CHIFS on rising edge of CHICK |
| 1268 | */ |
| 1269 | int clockrate = bits_per_frame * 8; |
| 1270 | int divisor = 12288 / clockrate; |
| 1271 | |
| 1272 | if (divisor > 255 || divisor * clockrate != 12288) |
| 1273 | printk("DBRI: illegal bits_per_frame in setup_chi\n"); |
| 1274 | |
| 1275 | *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD |
| 1276 | | D_CHI_BPF(bits_per_frame)); |
| 1277 | } |
| 1278 | |
| 1279 | dbri->chi_bpf = bits_per_frame; |
| 1280 | |
| 1281 | /* CHI Data Mode |
| 1282 | * |
| 1283 | * RCE = 0 - receive on falling edge of CHICK |
| 1284 | * XCE = 1 - transmit on rising edge of CHICK |
| 1285 | * XEN = 1 - enable transmitter |
| 1286 | * REN = 1 - enable receiver |
| 1287 | */ |
| 1288 | |
| 1289 | *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
| 1290 | *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN); |
| 1291 | |
| 1292 | dbri_cmdsend(dbri, cmd); |
| 1293 | } |
| 1294 | |
| 1295 | /* |
| 1296 | **************************************************************************** |
| 1297 | *********************** CS4215 audio codec management ********************** |
| 1298 | **************************************************************************** |
| 1299 | |
| 1300 | In the standard SPARC audio configuration, the CS4215 codec is attached |
| 1301 | to the DBRI via the CHI interface and few of the DBRI's PIO pins. |
| 1302 | |
| 1303 | */ |
| 1304 | static void cs4215_setup_pipes(snd_dbri_t * dbri) |
| 1305 | { |
| 1306 | /* |
| 1307 | * Data mode: |
| 1308 | * Pipe 4: Send timeslots 1-4 (audio data) |
| 1309 | * Pipe 20: Send timeslots 5-8 (part of ctrl data) |
| 1310 | * Pipe 6: Receive timeslots 1-4 (audio data) |
| 1311 | * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via |
| 1312 | * interrupt, and the rest of the data (slot 5 and 8) is |
| 1313 | * not relevant for us (only for doublechecking). |
| 1314 | * |
| 1315 | * Control mode: |
| 1316 | * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly) |
| 1317 | * Pipe 18: Receive timeslot 1 (clb). |
| 1318 | * Pipe 19: Receive timeslot 7 (version). |
| 1319 | */ |
| 1320 | |
| 1321 | setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB); |
| 1322 | setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); |
| 1323 | setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB); |
| 1324 | setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); |
| 1325 | |
| 1326 | setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); |
| 1327 | setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); |
| 1328 | setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); |
| 1329 | } |
| 1330 | |
| 1331 | static int cs4215_init_data(struct cs4215 *mm) |
| 1332 | { |
| 1333 | /* |
| 1334 | * No action, memory resetting only. |
| 1335 | * |
| 1336 | * Data Time Slot 5-8 |
| 1337 | * Speaker,Line and Headphone enable. Gain set to the half. |
| 1338 | * Input is mike. |
| 1339 | */ |
| 1340 | mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE; |
| 1341 | mm->data[1] = CS4215_RO(0x20) | CS4215_SE; |
| 1342 | mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1; |
| 1343 | mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf); |
| 1344 | |
| 1345 | /* |
| 1346 | * Control Time Slot 1-4 |
| 1347 | * 0: Default I/O voltage scale |
| 1348 | * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled |
| 1349 | * 2: Serial enable, CHI master, 128 bits per frame, clock 1 |
| 1350 | * 3: Tests disabled |
| 1351 | */ |
| 1352 | mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB; |
| 1353 | mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; |
| 1354 | mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; |
| 1355 | mm->ctrl[3] = 0; |
| 1356 | |
| 1357 | mm->status = 0; |
| 1358 | mm->version = 0xff; |
| 1359 | mm->precision = 8; /* For ULAW */ |
| 1360 | mm->channels = 2; |
| 1361 | |
| 1362 | return 0; |
| 1363 | } |
| 1364 | |
| 1365 | static void cs4215_setdata(snd_dbri_t * dbri, int muted) |
| 1366 | { |
| 1367 | if (muted) { |
| 1368 | dbri->mm.data[0] |= 63; |
| 1369 | dbri->mm.data[1] |= 63; |
| 1370 | dbri->mm.data[2] &= ~15; |
| 1371 | dbri->mm.data[3] &= ~15; |
| 1372 | } else { |
| 1373 | /* Start by setting the playback attenuation. */ |
| 1374 | dbri_streaminfo_t *info = &dbri->stream_info[DBRI_PLAY]; |
| 1375 | int left_gain = info->left_gain % 64; |
| 1376 | int right_gain = info->right_gain % 64; |
| 1377 | |
| 1378 | if (info->balance < DBRI_MID_BALANCE) { |
| 1379 | right_gain *= info->balance; |
| 1380 | right_gain /= DBRI_MID_BALANCE; |
| 1381 | } else { |
| 1382 | left_gain *= DBRI_RIGHT_BALANCE - info->balance; |
| 1383 | left_gain /= DBRI_MID_BALANCE; |
| 1384 | } |
| 1385 | |
| 1386 | dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */ |
| 1387 | dbri->mm.data[1] &= ~0x3f; |
| 1388 | dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain); |
| 1389 | dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain); |
| 1390 | |
| 1391 | /* Now set the recording gain. */ |
| 1392 | info = &dbri->stream_info[DBRI_REC]; |
| 1393 | left_gain = info->left_gain % 16; |
| 1394 | right_gain = info->right_gain % 16; |
| 1395 | dbri->mm.data[2] |= CS4215_LG(left_gain); |
| 1396 | dbri->mm.data[3] |= CS4215_RG(right_gain); |
| 1397 | } |
| 1398 | |
| 1399 | xmit_fixed(dbri, 20, *(int *)dbri->mm.data); |
| 1400 | } |
| 1401 | |
| 1402 | /* |
| 1403 | * Set the CS4215 to data mode. |
| 1404 | */ |
| 1405 | static void cs4215_open(snd_dbri_t * dbri) |
| 1406 | { |
| 1407 | int data_width; |
| 1408 | u32 tmp; |
| 1409 | |
| 1410 | dprintk(D_MM, "cs4215_open: %d channels, %d bits\n", |
| 1411 | dbri->mm.channels, dbri->mm.precision); |
| 1412 | |
| 1413 | /* Temporarily mute outputs, and wait 1/8000 sec (125 us) |
| 1414 | * to make sure this takes. This avoids clicking noises. |
| 1415 | */ |
| 1416 | |
| 1417 | cs4215_setdata(dbri, 1); |
| 1418 | udelay(125); |
| 1419 | |
| 1420 | /* |
| 1421 | * Data mode: |
| 1422 | * Pipe 4: Send timeslots 1-4 (audio data) |
| 1423 | * Pipe 20: Send timeslots 5-8 (part of ctrl data) |
| 1424 | * Pipe 6: Receive timeslots 1-4 (audio data) |
| 1425 | * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via |
| 1426 | * interrupt, and the rest of the data (slot 5 and 8) is |
| 1427 | * not relevant for us (only for doublechecking). |
| 1428 | * |
| 1429 | * Just like in control mode, the time slots are all offset by eight |
| 1430 | * bits. The CS4215, it seems, observes TSIN (the delayed signal) |
| 1431 | * even if it's the CHI master. Don't ask me... |
| 1432 | */ |
| 1433 | tmp = sbus_readl(dbri->regs + REG0); |
| 1434 | tmp &= ~(D_C); /* Disable CHI */ |
| 1435 | sbus_writel(tmp, dbri->regs + REG0); |
| 1436 | |
| 1437 | /* Switch CS4215 to data mode - set PIO3 to 1 */ |
| 1438 | sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 | |
| 1439 | (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2); |
| 1440 | |
| 1441 | reset_chi(dbri, CHIslave, 128); |
| 1442 | |
| 1443 | /* Note: this next doesn't work for 8-bit stereo, because the two |
| 1444 | * channels would be on timeslots 1 and 3, with 2 and 4 idle. |
| 1445 | * (See CS4215 datasheet Fig 15) |
| 1446 | * |
| 1447 | * DBRI non-contiguous mode would be required to make this work. |
| 1448 | */ |
| 1449 | data_width = dbri->mm.channels * dbri->mm.precision; |
| 1450 | |
| 1451 | link_time_slot(dbri, 20, PIPEoutput, 16, 32, dbri->mm.offset + 32); |
| 1452 | link_time_slot(dbri, 4, PIPEoutput, 16, data_width, dbri->mm.offset); |
| 1453 | link_time_slot(dbri, 6, PIPEinput, 16, data_width, dbri->mm.offset); |
| 1454 | link_time_slot(dbri, 21, PIPEinput, 16, 16, dbri->mm.offset + 40); |
| 1455 | |
| 1456 | /* FIXME: enable CHI after _setdata? */ |
| 1457 | tmp = sbus_readl(dbri->regs + REG0); |
| 1458 | tmp |= D_C; /* Enable CHI */ |
| 1459 | sbus_writel(tmp, dbri->regs + REG0); |
| 1460 | |
| 1461 | cs4215_setdata(dbri, 0); |
| 1462 | } |
| 1463 | |
| 1464 | /* |
| 1465 | * Send the control information (i.e. audio format) |
| 1466 | */ |
| 1467 | static int cs4215_setctrl(snd_dbri_t * dbri) |
| 1468 | { |
| 1469 | int i, val; |
| 1470 | u32 tmp; |
| 1471 | |
| 1472 | /* FIXME - let the CPU do something useful during these delays */ |
| 1473 | |
| 1474 | /* Temporarily mute outputs, and wait 1/8000 sec (125 us) |
| 1475 | * to make sure this takes. This avoids clicking noises. |
| 1476 | */ |
| 1477 | |
| 1478 | cs4215_setdata(dbri, 1); |
| 1479 | udelay(125); |
| 1480 | |
| 1481 | /* |
| 1482 | * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait |
| 1483 | * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec |
| 1484 | */ |
| 1485 | val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2); |
| 1486 | sbus_writel(val, dbri->regs + REG2); |
| 1487 | dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val); |
| 1488 | udelay(34); |
| 1489 | |
| 1490 | /* In Control mode, the CS4215 is a slave device, so the DBRI must |
| 1491 | * operate as CHI master, supplying clocking and frame synchronization. |
| 1492 | * |
| 1493 | * In Data mode, however, the CS4215 must be CHI master to insure |
| 1494 | * that its data stream is synchronous with its codec. |
| 1495 | * |
| 1496 | * The upshot of all this? We start by putting the DBRI into master |
| 1497 | * mode, program the CS4215 in Control mode, then switch the CS4215 |
| 1498 | * into Data mode and put the DBRI into slave mode. Various timing |
| 1499 | * requirements must be observed along the way. |
| 1500 | * |
| 1501 | * Oh, and one more thing, on a SPARCStation 20 (and maybe |
| 1502 | * others?), the addressing of the CS4215's time slots is |
| 1503 | * offset by eight bits, so we add eight to all the "cycle" |
| 1504 | * values in the Define Time Slot (DTS) commands. This is |
| 1505 | * done in hardware by a TI 248 that delays the DBRI->4215 |
| 1506 | * frame sync signal by eight clock cycles. Anybody know why? |
| 1507 | */ |
| 1508 | tmp = sbus_readl(dbri->regs + REG0); |
| 1509 | tmp &= ~D_C; /* Disable CHI */ |
| 1510 | sbus_writel(tmp, dbri->regs + REG0); |
| 1511 | |
| 1512 | reset_chi(dbri, CHImaster, 128); |
| 1513 | |
| 1514 | /* |
| 1515 | * Control mode: |
| 1516 | * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly) |
| 1517 | * Pipe 18: Receive timeslot 1 (clb). |
| 1518 | * Pipe 19: Receive timeslot 7 (version). |
| 1519 | */ |
| 1520 | |
| 1521 | link_time_slot(dbri, 17, PIPEoutput, 16, 32, dbri->mm.offset); |
| 1522 | link_time_slot(dbri, 18, PIPEinput, 16, 8, dbri->mm.offset); |
| 1523 | link_time_slot(dbri, 19, PIPEinput, 16, 8, dbri->mm.offset + 48); |
| 1524 | |
| 1525 | /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */ |
| 1526 | dbri->mm.ctrl[0] &= ~CS4215_CLB; |
| 1527 | xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); |
| 1528 | |
| 1529 | tmp = sbus_readl(dbri->regs + REG0); |
| 1530 | tmp |= D_C; /* Enable CHI */ |
| 1531 | sbus_writel(tmp, dbri->regs + REG0); |
| 1532 | |
| 1533 | for (i = 64; ((dbri->mm.status & 0xe4) != 0x20); --i) { |
| 1534 | udelay(125); |
| 1535 | } |
| 1536 | if (i == 0) { |
| 1537 | dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n", |
| 1538 | dbri->mm.status); |
| 1539 | return -1; |
| 1540 | } |
| 1541 | |
| 1542 | /* Disable changes to our copy of the version number, as we are about |
| 1543 | * to leave control mode. |
| 1544 | */ |
| 1545 | recv_fixed(dbri, 19, NULL); |
| 1546 | |
| 1547 | /* Terminate CS4215 control mode - data sheet says |
| 1548 | * "Set CLB=1 and send two more frames of valid control info" |
| 1549 | */ |
| 1550 | dbri->mm.ctrl[0] |= CS4215_CLB; |
| 1551 | xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); |
| 1552 | |
| 1553 | /* Two frames of control info @ 8kHz frame rate = 250 us delay */ |
| 1554 | udelay(250); |
| 1555 | |
| 1556 | cs4215_setdata(dbri, 0); |
| 1557 | |
| 1558 | return 0; |
| 1559 | } |
| 1560 | |
| 1561 | /* |
| 1562 | * Setup the codec with the sampling rate, audio format and number of |
| 1563 | * channels. |
| 1564 | * As part of the process we resend the settings for the data |
| 1565 | * timeslots as well. |
| 1566 | */ |
| 1567 | static int cs4215_prepare(snd_dbri_t * dbri, unsigned int rate, |
| 1568 | snd_pcm_format_t format, unsigned int channels) |
| 1569 | { |
| 1570 | int freq_idx; |
| 1571 | int ret = 0; |
| 1572 | |
| 1573 | /* Lookup index for this rate */ |
| 1574 | for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) { |
| 1575 | if (CS4215_FREQ[freq_idx].freq == rate) |
| 1576 | break; |
| 1577 | } |
| 1578 | if (CS4215_FREQ[freq_idx].freq != rate) { |
| 1579 | printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate); |
| 1580 | return -1; |
| 1581 | } |
| 1582 | |
| 1583 | switch (format) { |
| 1584 | case SNDRV_PCM_FORMAT_MU_LAW: |
| 1585 | dbri->mm.ctrl[1] = CS4215_DFR_ULAW; |
| 1586 | dbri->mm.precision = 8; |
| 1587 | break; |
| 1588 | case SNDRV_PCM_FORMAT_A_LAW: |
| 1589 | dbri->mm.ctrl[1] = CS4215_DFR_ALAW; |
| 1590 | dbri->mm.precision = 8; |
| 1591 | break; |
| 1592 | case SNDRV_PCM_FORMAT_U8: |
| 1593 | dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8; |
| 1594 | dbri->mm.precision = 8; |
| 1595 | break; |
| 1596 | case SNDRV_PCM_FORMAT_S16_BE: |
| 1597 | dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16; |
| 1598 | dbri->mm.precision = 16; |
| 1599 | break; |
| 1600 | default: |
| 1601 | printk(KERN_WARNING "DBRI: Unsupported format %d\n", format); |
| 1602 | return -1; |
| 1603 | } |
| 1604 | |
| 1605 | /* Add rate parameters */ |
| 1606 | dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval; |
| 1607 | dbri->mm.ctrl[2] = CS4215_XCLK | |
| 1608 | CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal; |
| 1609 | |
| 1610 | dbri->mm.channels = channels; |
| 1611 | /* Stereo bit: 8 bit stereo not working yet. */ |
| 1612 | if ((channels > 1) && (dbri->mm.precision == 16)) |
| 1613 | dbri->mm.ctrl[1] |= CS4215_DFR_STEREO; |
| 1614 | |
| 1615 | ret = cs4215_setctrl(dbri); |
| 1616 | if (ret == 0) |
| 1617 | cs4215_open(dbri); /* set codec to data mode */ |
| 1618 | |
| 1619 | return ret; |
| 1620 | } |
| 1621 | |
| 1622 | /* |
| 1623 | * |
| 1624 | */ |
| 1625 | static int cs4215_init(snd_dbri_t * dbri) |
| 1626 | { |
| 1627 | u32 reg2 = sbus_readl(dbri->regs + REG2); |
| 1628 | dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2); |
| 1629 | |
| 1630 | /* Look for the cs4215 chips */ |
| 1631 | if (reg2 & D_PIO2) { |
| 1632 | dprintk(D_MM, "Onboard CS4215 detected\n"); |
| 1633 | dbri->mm.onboard = 1; |
| 1634 | } |
| 1635 | if (reg2 & D_PIO0) { |
| 1636 | dprintk(D_MM, "Speakerbox detected\n"); |
| 1637 | dbri->mm.onboard = 0; |
| 1638 | |
| 1639 | if (reg2 & D_PIO2) { |
| 1640 | printk(KERN_INFO "DBRI: Using speakerbox / " |
| 1641 | "ignoring onboard mmcodec.\n"); |
| 1642 | sbus_writel(D_ENPIO2, dbri->regs + REG2); |
| 1643 | } |
| 1644 | } |
| 1645 | |
| 1646 | if (!(reg2 & (D_PIO0 | D_PIO2))) { |
| 1647 | printk(KERN_ERR "DBRI: no mmcodec found.\n"); |
| 1648 | return -EIO; |
| 1649 | } |
| 1650 | |
| 1651 | cs4215_setup_pipes(dbri); |
| 1652 | |
| 1653 | cs4215_init_data(&dbri->mm); |
| 1654 | |
| 1655 | /* Enable capture of the status & version timeslots. */ |
| 1656 | recv_fixed(dbri, 18, &dbri->mm.status); |
| 1657 | recv_fixed(dbri, 19, &dbri->mm.version); |
| 1658 | |
| 1659 | dbri->mm.offset = dbri->mm.onboard ? 0 : 8; |
| 1660 | if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) { |
| 1661 | dprintk(D_MM, "CS4215 failed probe at offset %d\n", |
| 1662 | dbri->mm.offset); |
| 1663 | return -EIO; |
| 1664 | } |
| 1665 | dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset); |
| 1666 | |
| 1667 | return 0; |
| 1668 | } |
| 1669 | |
| 1670 | /* |
| 1671 | **************************************************************************** |
| 1672 | *************************** DBRI interrupt handler ************************* |
| 1673 | **************************************************************************** |
| 1674 | |
| 1675 | The DBRI communicates with the CPU mainly via a circular interrupt |
| 1676 | buffer. When an interrupt is signaled, the CPU walks through the |
| 1677 | buffer and calls dbri_process_one_interrupt() for each interrupt word. |
| 1678 | Complicated interrupts are handled by dedicated functions (which |
| 1679 | appear first in this file). Any pending interrupts can be serviced by |
| 1680 | calling dbri_process_interrupt_buffer(), which works even if the CPU's |
| 1681 | interrupts are disabled. This function is used by dbri_cmdsend() |
| 1682 | to make sure we're synced up with the chip after each command sequence, |
| 1683 | even if we're running cli'ed. |
| 1684 | |
| 1685 | */ |
| 1686 | |
| 1687 | /* xmit_descs() |
| 1688 | * |
| 1689 | * Transmit the current TD's for recording/playing, if needed. |
| 1690 | * For playback, ALSA has filled the DMA memory with new data (we hope). |
| 1691 | */ |
| 1692 | static void xmit_descs(unsigned long data) |
| 1693 | { |
| 1694 | snd_dbri_t *dbri = (snd_dbri_t *) data; |
| 1695 | dbri_streaminfo_t *info; |
| 1696 | volatile s32 *cmd; |
| 1697 | unsigned long flags; |
| 1698 | int first_td; |
| 1699 | |
| 1700 | if (dbri == NULL) |
| 1701 | return; /* Disabled */ |
| 1702 | |
| 1703 | /* First check the recording stream for buffer overflow */ |
| 1704 | info = &dbri->stream_info[DBRI_REC]; |
| 1705 | spin_lock_irqsave(&dbri->lock, flags); |
| 1706 | |
| 1707 | if ((info->left >= info->size) && (info->pipe >= 0)) { |
| 1708 | first_td = dbri->pipes[info->pipe].first_desc; |
| 1709 | |
| 1710 | dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td); |
| 1711 | |
| 1712 | /* Stream could be closed by the time we run. */ |
| 1713 | if (first_td < 0) { |
| 1714 | goto play; |
| 1715 | } |
| 1716 | |
| 1717 | cmd = dbri_cmdlock(dbri, NoGetLock); |
| 1718 | *(cmd++) = DBRI_CMD(D_SDP, 0, |
| 1719 | dbri->pipes[info->pipe].sdp |
| 1720 | | D_SDP_P | D_SDP_EVERY | D_SDP_C); |
| 1721 | *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td); |
| 1722 | dbri_cmdsend(dbri, cmd); |
| 1723 | |
| 1724 | /* Reset our admin of the pipe & bytes read. */ |
| 1725 | dbri->pipes[info->pipe].desc = first_td; |
| 1726 | info->left = 0; |
| 1727 | } |
| 1728 | |
| 1729 | play: |
| 1730 | spin_unlock_irqrestore(&dbri->lock, flags); |
| 1731 | |
| 1732 | /* Now check the playback stream for buffer underflow */ |
| 1733 | info = &dbri->stream_info[DBRI_PLAY]; |
| 1734 | spin_lock_irqsave(&dbri->lock, flags); |
| 1735 | |
| 1736 | if ((info->left <= 0) && (info->pipe >= 0)) { |
| 1737 | first_td = dbri->pipes[info->pipe].first_desc; |
| 1738 | |
| 1739 | dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td); |
| 1740 | |
| 1741 | /* Stream could be closed by the time we run. */ |
| 1742 | if (first_td < 0) { |
| 1743 | spin_unlock_irqrestore(&dbri->lock, flags); |
| 1744 | return; |
| 1745 | } |
| 1746 | |
| 1747 | cmd = dbri_cmdlock(dbri, NoGetLock); |
| 1748 | *(cmd++) = DBRI_CMD(D_SDP, 0, |
| 1749 | dbri->pipes[info->pipe].sdp |
| 1750 | | D_SDP_P | D_SDP_EVERY | D_SDP_C); |
| 1751 | *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td); |
| 1752 | dbri_cmdsend(dbri, cmd); |
| 1753 | |
| 1754 | /* Reset our admin of the pipe & bytes written. */ |
| 1755 | dbri->pipes[info->pipe].desc = first_td; |
| 1756 | info->left = info->size; |
| 1757 | } |
| 1758 | spin_unlock_irqrestore(&dbri->lock, flags); |
| 1759 | } |
| 1760 | |
| 1761 | DECLARE_TASKLET(xmit_descs_task, xmit_descs, 0); |
| 1762 | |
| 1763 | /* transmission_complete_intr() |
| 1764 | * |
| 1765 | * Called by main interrupt handler when DBRI signals transmission complete |
| 1766 | * on a pipe (interrupt triggered by the B bit in a transmit descriptor). |
| 1767 | * |
| 1768 | * Walks through the pipe's list of transmit buffer descriptors, releasing |
| 1769 | * each one's DMA buffer (if present), flagging the descriptor available, |
| 1770 | * and signaling its callback routine (if present), before proceeding |
| 1771 | * to the next one. Stops when the first descriptor is found without |
| 1772 | * TBC (Transmit Buffer Complete) set, or we've run through them all. |
| 1773 | */ |
| 1774 | |
| 1775 | static void transmission_complete_intr(snd_dbri_t * dbri, int pipe) |
| 1776 | { |
| 1777 | dbri_streaminfo_t *info; |
| 1778 | int td; |
| 1779 | int status; |
| 1780 | |
| 1781 | info = &dbri->stream_info[DBRI_PLAY]; |
| 1782 | |
| 1783 | td = dbri->pipes[pipe].desc; |
| 1784 | while (td >= 0) { |
| 1785 | if (td >= DBRI_NO_DESCS) { |
| 1786 | printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe); |
| 1787 | return; |
| 1788 | } |
| 1789 | |
| 1790 | status = DBRI_TD_STATUS(dbri->dma->desc[td].word4); |
| 1791 | if (!(status & DBRI_TD_TBC)) { |
| 1792 | break; |
| 1793 | } |
| 1794 | |
| 1795 | dprintk(D_INT, "TD %d, status 0x%02x\n", td, status); |
| 1796 | |
| 1797 | dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */ |
| 1798 | info->offset += dbri->descs[td].len; |
| 1799 | info->left -= dbri->descs[td].len; |
| 1800 | |
| 1801 | /* On the last TD, transmit them all again. */ |
| 1802 | if (dbri->descs[td].next == -1) { |
| 1803 | if (info->left > 0) { |
| 1804 | printk(KERN_WARNING |
| 1805 | "%d bytes left after last transfer.\n", |
| 1806 | info->left); |
| 1807 | info->left = 0; |
| 1808 | } |
| 1809 | tasklet_schedule(&xmit_descs_task); |
| 1810 | } |
| 1811 | |
| 1812 | td = dbri->descs[td].next; |
| 1813 | dbri->pipes[pipe].desc = td; |
| 1814 | } |
| 1815 | |
| 1816 | /* Notify ALSA */ |
| 1817 | if (spin_is_locked(&dbri->lock)) { |
| 1818 | spin_unlock(&dbri->lock); |
| 1819 | snd_pcm_period_elapsed(info->substream); |
| 1820 | spin_lock(&dbri->lock); |
| 1821 | } else |
| 1822 | snd_pcm_period_elapsed(info->substream); |
| 1823 | } |
| 1824 | |
| 1825 | static void reception_complete_intr(snd_dbri_t * dbri, int pipe) |
| 1826 | { |
| 1827 | dbri_streaminfo_t *info; |
| 1828 | int rd = dbri->pipes[pipe].desc; |
| 1829 | s32 status; |
| 1830 | |
| 1831 | if (rd < 0 || rd >= DBRI_NO_DESCS) { |
| 1832 | printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe); |
| 1833 | return; |
| 1834 | } |
| 1835 | |
| 1836 | dbri->descs[rd].inuse = 0; |
| 1837 | dbri->pipes[pipe].desc = dbri->descs[rd].next; |
| 1838 | status = dbri->dma->desc[rd].word1; |
| 1839 | dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */ |
| 1840 | |
| 1841 | info = &dbri->stream_info[DBRI_REC]; |
| 1842 | info->offset += DBRI_RD_CNT(status); |
| 1843 | info->left += DBRI_RD_CNT(status); |
| 1844 | |
| 1845 | /* FIXME: Check status */ |
| 1846 | |
| 1847 | dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n", |
| 1848 | rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)); |
| 1849 | |
| 1850 | /* On the last TD, transmit them all again. */ |
| 1851 | if (dbri->descs[rd].next == -1) { |
| 1852 | if (info->left > info->size) { |
| 1853 | printk(KERN_WARNING |
| 1854 | "%d bytes recorded in %d size buffer.\n", |
| 1855 | info->left, info->size); |
| 1856 | } |
| 1857 | tasklet_schedule(&xmit_descs_task); |
| 1858 | } |
| 1859 | |
| 1860 | /* Notify ALSA */ |
| 1861 | if (spin_is_locked(&dbri->lock)) { |
| 1862 | spin_unlock(&dbri->lock); |
| 1863 | snd_pcm_period_elapsed(info->substream); |
| 1864 | spin_lock(&dbri->lock); |
| 1865 | } else |
| 1866 | snd_pcm_period_elapsed(info->substream); |
| 1867 | } |
| 1868 | |
| 1869 | static void dbri_process_one_interrupt(snd_dbri_t * dbri, int x) |
| 1870 | { |
| 1871 | int val = D_INTR_GETVAL(x); |
| 1872 | int channel = D_INTR_GETCHAN(x); |
| 1873 | int command = D_INTR_GETCMD(x); |
| 1874 | int code = D_INTR_GETCODE(x); |
| 1875 | #ifdef DBRI_DEBUG |
| 1876 | int rval = D_INTR_GETRVAL(x); |
| 1877 | #endif |
| 1878 | |
| 1879 | if (channel == D_INTR_CMD) { |
| 1880 | dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n", |
| 1881 | cmds[command], val); |
| 1882 | } else { |
| 1883 | dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n", |
| 1884 | channel, code, rval); |
| 1885 | } |
| 1886 | |
| 1887 | if (channel == D_INTR_CMD && command == D_WAIT) { |
| 1888 | dbri->wait_seen++; |
| 1889 | return; |
| 1890 | } |
| 1891 | |
| 1892 | switch (code) { |
| 1893 | case D_INTR_BRDY: |
| 1894 | reception_complete_intr(dbri, channel); |
| 1895 | break; |
| 1896 | case D_INTR_XCMP: |
| 1897 | case D_INTR_MINT: |
| 1898 | transmission_complete_intr(dbri, channel); |
| 1899 | break; |
| 1900 | case D_INTR_UNDR: |
| 1901 | /* UNDR - Transmission underrun |
| 1902 | * resend SDP command with clear pipe bit (C) set |
| 1903 | */ |
| 1904 | { |
| 1905 | volatile s32 *cmd; |
| 1906 | |
| 1907 | int pipe = channel; |
| 1908 | int td = dbri->pipes[pipe].desc; |
| 1909 | |
| 1910 | dbri->dma->desc[td].word4 = 0; |
| 1911 | cmd = dbri_cmdlock(dbri, NoGetLock); |
| 1912 | *(cmd++) = DBRI_CMD(D_SDP, 0, |
| 1913 | dbri->pipes[pipe].sdp |
| 1914 | | D_SDP_P | D_SDP_C | D_SDP_2SAME); |
| 1915 | *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td); |
| 1916 | dbri_cmdsend(dbri, cmd); |
| 1917 | } |
| 1918 | break; |
| 1919 | case D_INTR_FXDT: |
| 1920 | /* FXDT - Fixed data change */ |
| 1921 | if (dbri->pipes[channel].sdp & D_SDP_MSB) |
| 1922 | val = reverse_bytes(val, dbri->pipes[channel].length); |
| 1923 | |
| 1924 | if (dbri->pipes[channel].recv_fixed_ptr) |
| 1925 | *(dbri->pipes[channel].recv_fixed_ptr) = val; |
| 1926 | break; |
| 1927 | default: |
| 1928 | if (channel != D_INTR_CMD) |
| 1929 | printk(KERN_WARNING |
| 1930 | "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x); |
| 1931 | } |
| 1932 | } |
| 1933 | |
| 1934 | /* dbri_process_interrupt_buffer advances through the DBRI's interrupt |
| 1935 | * buffer until it finds a zero word (indicating nothing more to do |
| 1936 | * right now). Non-zero words require processing and are handed off |
| 1937 | * to dbri_process_one_interrupt AFTER advancing the pointer. This |
| 1938 | * order is important since we might recurse back into this function |
| 1939 | * and need to make sure the pointer has been advanced first. |
| 1940 | */ |
| 1941 | static void dbri_process_interrupt_buffer(snd_dbri_t * dbri) |
| 1942 | { |
| 1943 | s32 x; |
| 1944 | |
| 1945 | while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) { |
| 1946 | dbri->dma->intr[dbri->dbri_irqp] = 0; |
| 1947 | dbri->dbri_irqp++; |
| 1948 | if (dbri->dbri_irqp == (DBRI_NO_INTS * DBRI_INT_BLK)) |
| 1949 | dbri->dbri_irqp = 1; |
| 1950 | else if ((dbri->dbri_irqp & (DBRI_INT_BLK - 1)) == 0) |
| 1951 | dbri->dbri_irqp++; |
| 1952 | |
| 1953 | dbri_process_one_interrupt(dbri, x); |
| 1954 | } |
| 1955 | } |
| 1956 | |
| 1957 | static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id, |
| 1958 | struct pt_regs *regs) |
| 1959 | { |
| 1960 | snd_dbri_t *dbri = dev_id; |
| 1961 | static int errcnt = 0; |
| 1962 | int x; |
| 1963 | |
| 1964 | if (dbri == NULL) |
| 1965 | return IRQ_NONE; |
| 1966 | spin_lock(&dbri->lock); |
| 1967 | |
| 1968 | /* |
| 1969 | * Read it, so the interrupt goes away. |
| 1970 | */ |
| 1971 | x = sbus_readl(dbri->regs + REG1); |
| 1972 | |
| 1973 | if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) { |
| 1974 | u32 tmp; |
| 1975 | |
| 1976 | if (x & D_MRR) |
| 1977 | printk(KERN_ERR |
| 1978 | "DBRI: Multiple Error Ack on SBus reg1=0x%x\n", |
| 1979 | x); |
| 1980 | if (x & D_MLE) |
| 1981 | printk(KERN_ERR |
| 1982 | "DBRI: Multiple Late Error on SBus reg1=0x%x\n", |
| 1983 | x); |
| 1984 | if (x & D_LBG) |
| 1985 | printk(KERN_ERR |
| 1986 | "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x); |
| 1987 | if (x & D_MBE) |
| 1988 | printk(KERN_ERR |
| 1989 | "DBRI: Burst Error on SBus reg1=0x%x\n", x); |
| 1990 | |
| 1991 | /* Some of these SBus errors cause the chip's SBus circuitry |
| 1992 | * to be disabled, so just re-enable and try to keep going. |
| 1993 | * |
| 1994 | * The only one I've seen is MRR, which will be triggered |
| 1995 | * if you let a transmit pipe underrun, then try to CDP it. |
| 1996 | * |
| 1997 | * If these things persist, we should probably reset |
| 1998 | * and re-init the chip. |
| 1999 | */ |
| 2000 | if ((++errcnt) % 10 == 0) { |
| 2001 | dprintk(D_INT, "Interrupt errors exceeded.\n"); |
| 2002 | dbri_reset(dbri); |
| 2003 | } else { |
| 2004 | tmp = sbus_readl(dbri->regs + REG0); |
| 2005 | tmp &= ~(D_D); |
| 2006 | sbus_writel(tmp, dbri->regs + REG0); |
| 2007 | } |
| 2008 | } |
| 2009 | |
| 2010 | dbri_process_interrupt_buffer(dbri); |
| 2011 | |
| 2012 | /* FIXME: Write 0 into regs to ACK interrupt */ |
| 2013 | |
| 2014 | spin_unlock(&dbri->lock); |
| 2015 | |
| 2016 | return IRQ_HANDLED; |
| 2017 | } |
| 2018 | |
| 2019 | /**************************************************************************** |
| 2020 | PCM Interface |
| 2021 | ****************************************************************************/ |
| 2022 | static snd_pcm_hardware_t snd_dbri_pcm_hw = { |
| 2023 | .info = (SNDRV_PCM_INFO_MMAP | |
| 2024 | SNDRV_PCM_INFO_INTERLEAVED | |
| 2025 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
| 2026 | SNDRV_PCM_INFO_MMAP_VALID), |
| 2027 | .formats = SNDRV_PCM_FMTBIT_MU_LAW | |
| 2028 | SNDRV_PCM_FMTBIT_A_LAW | |
| 2029 | SNDRV_PCM_FMTBIT_U8 | |
| 2030 | SNDRV_PCM_FMTBIT_S16_BE, |
| 2031 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 2032 | .rate_min = 8000, |
| 2033 | .rate_max = 48000, |
| 2034 | .channels_min = 1, |
| 2035 | .channels_max = 2, |
| 2036 | .buffer_bytes_max = (64 * 1024), |
| 2037 | .period_bytes_min = 1, |
| 2038 | .period_bytes_max = DBRI_TD_MAXCNT, |
| 2039 | .periods_min = 1, |
| 2040 | .periods_max = 1024, |
| 2041 | }; |
| 2042 | |
| 2043 | static int snd_dbri_open(snd_pcm_substream_t * substream) |
| 2044 | { |
| 2045 | snd_dbri_t *dbri = snd_pcm_substream_chip(substream); |
| 2046 | snd_pcm_runtime_t *runtime = substream->runtime; |
| 2047 | dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); |
| 2048 | unsigned long flags; |
| 2049 | |
| 2050 | dprintk(D_USR, "open audio output.\n"); |
| 2051 | runtime->hw = snd_dbri_pcm_hw; |
| 2052 | |
| 2053 | spin_lock_irqsave(&dbri->lock, flags); |
| 2054 | info->substream = substream; |
| 2055 | info->left = 0; |
| 2056 | info->offset = 0; |
| 2057 | info->dvma_buffer = 0; |
| 2058 | info->pipe = -1; |
| 2059 | spin_unlock_irqrestore(&dbri->lock, flags); |
| 2060 | |
| 2061 | cs4215_open(dbri); |
| 2062 | |
| 2063 | return 0; |
| 2064 | } |
| 2065 | |
| 2066 | static int snd_dbri_close(snd_pcm_substream_t * substream) |
| 2067 | { |
| 2068 | snd_dbri_t *dbri = snd_pcm_substream_chip(substream); |
| 2069 | dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); |
| 2070 | |
| 2071 | dprintk(D_USR, "close audio output.\n"); |
| 2072 | info->substream = NULL; |
| 2073 | info->left = 0; |
| 2074 | info->offset = 0; |
| 2075 | |
| 2076 | return 0; |
| 2077 | } |
| 2078 | |
| 2079 | static int snd_dbri_hw_params(snd_pcm_substream_t * substream, |
| 2080 | snd_pcm_hw_params_t * hw_params) |
| 2081 | { |
| 2082 | snd_pcm_runtime_t *runtime = substream->runtime; |
| 2083 | snd_dbri_t *dbri = snd_pcm_substream_chip(substream); |
| 2084 | dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); |
| 2085 | int direction; |
| 2086 | int ret; |
| 2087 | |
| 2088 | /* set sampling rate, audio format and number of channels */ |
| 2089 | ret = cs4215_prepare(dbri, params_rate(hw_params), |
| 2090 | params_format(hw_params), |
| 2091 | params_channels(hw_params)); |
| 2092 | if (ret != 0) |
| 2093 | return ret; |
| 2094 | |
| 2095 | if ((ret = snd_pcm_lib_malloc_pages(substream, |
| 2096 | params_buffer_bytes(hw_params))) < 0) { |
| 2097 | snd_printk(KERN_ERR "malloc_pages failed with %d\n", ret); |
| 2098 | return ret; |
| 2099 | } |
| 2100 | |
| 2101 | /* hw_params can get called multiple times. Only map the DMA once. |
| 2102 | */ |
| 2103 | if (info->dvma_buffer == 0) { |
| 2104 | if (DBRI_STREAMNO(substream) == DBRI_PLAY) |
| 2105 | direction = SBUS_DMA_TODEVICE; |
| 2106 | else |
| 2107 | direction = SBUS_DMA_FROMDEVICE; |
| 2108 | |
| 2109 | info->dvma_buffer = sbus_map_single(dbri->sdev, |
| 2110 | runtime->dma_area, |
| 2111 | params_buffer_bytes(hw_params), |
| 2112 | direction); |
| 2113 | } |
| 2114 | |
| 2115 | direction = params_buffer_bytes(hw_params); |
| 2116 | dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n", |
| 2117 | direction, info->dvma_buffer); |
| 2118 | return 0; |
| 2119 | } |
| 2120 | |
| 2121 | static int snd_dbri_hw_free(snd_pcm_substream_t * substream) |
| 2122 | { |
| 2123 | snd_dbri_t *dbri = snd_pcm_substream_chip(substream); |
| 2124 | dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); |
| 2125 | int direction; |
| 2126 | dprintk(D_USR, "hw_free.\n"); |
| 2127 | |
| 2128 | /* hw_free can get called multiple times. Only unmap the DMA once. |
| 2129 | */ |
| 2130 | if (info->dvma_buffer) { |
| 2131 | if (DBRI_STREAMNO(substream) == DBRI_PLAY) |
| 2132 | direction = SBUS_DMA_TODEVICE; |
| 2133 | else |
| 2134 | direction = SBUS_DMA_FROMDEVICE; |
| 2135 | |
| 2136 | sbus_unmap_single(dbri->sdev, info->dvma_buffer, |
| 2137 | substream->runtime->buffer_size, direction); |
| 2138 | info->dvma_buffer = 0; |
| 2139 | } |
| 2140 | info->pipe = -1; |
| 2141 | |
| 2142 | return snd_pcm_lib_free_pages(substream); |
| 2143 | } |
| 2144 | |
| 2145 | static int snd_dbri_prepare(snd_pcm_substream_t * substream) |
| 2146 | { |
| 2147 | snd_dbri_t *dbri = snd_pcm_substream_chip(substream); |
| 2148 | dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); |
| 2149 | snd_pcm_runtime_t *runtime = substream->runtime; |
| 2150 | int ret; |
| 2151 | |
| 2152 | info->size = snd_pcm_lib_buffer_bytes(substream); |
| 2153 | if (DBRI_STREAMNO(substream) == DBRI_PLAY) |
| 2154 | info->pipe = 4; /* Send pipe */ |
| 2155 | else { |
| 2156 | info->pipe = 6; /* Receive pipe */ |
| 2157 | info->left = info->size; /* To trigger submittal */ |
| 2158 | } |
| 2159 | |
| 2160 | spin_lock_irq(&dbri->lock); |
| 2161 | |
| 2162 | /* Setup the all the transmit/receive desciptors to cover the |
| 2163 | * whole DMA buffer. |
| 2164 | */ |
| 2165 | ret = setup_descs(dbri, DBRI_STREAMNO(substream), |
| 2166 | snd_pcm_lib_period_bytes(substream)); |
| 2167 | |
| 2168 | runtime->stop_threshold = DBRI_TD_MAXCNT / runtime->channels; |
| 2169 | |
| 2170 | spin_unlock_irq(&dbri->lock); |
| 2171 | |
| 2172 | dprintk(D_USR, "prepare audio output. %d bytes\n", info->size); |
| 2173 | return ret; |
| 2174 | } |
| 2175 | |
| 2176 | static int snd_dbri_trigger(snd_pcm_substream_t * substream, int cmd) |
| 2177 | { |
| 2178 | snd_dbri_t *dbri = snd_pcm_substream_chip(substream); |
| 2179 | dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); |
| 2180 | int ret = 0; |
| 2181 | |
| 2182 | switch (cmd) { |
| 2183 | case SNDRV_PCM_TRIGGER_START: |
| 2184 | dprintk(D_USR, "start audio, period is %d bytes\n", |
| 2185 | (int)snd_pcm_lib_period_bytes(substream)); |
| 2186 | /* Enable & schedule the tasklet that re-submits the TDs. */ |
| 2187 | xmit_descs_task.data = (unsigned long)dbri; |
| 2188 | tasklet_schedule(&xmit_descs_task); |
| 2189 | break; |
| 2190 | case SNDRV_PCM_TRIGGER_STOP: |
| 2191 | dprintk(D_USR, "stop audio.\n"); |
| 2192 | /* Make the tasklet bail out immediately. */ |
| 2193 | xmit_descs_task.data = 0; |
| 2194 | reset_pipe(dbri, info->pipe); |
| 2195 | break; |
| 2196 | default: |
| 2197 | ret = -EINVAL; |
| 2198 | } |
| 2199 | |
| 2200 | return ret; |
| 2201 | } |
| 2202 | |
| 2203 | static snd_pcm_uframes_t snd_dbri_pointer(snd_pcm_substream_t * substream) |
| 2204 | { |
| 2205 | snd_dbri_t *dbri = snd_pcm_substream_chip(substream); |
| 2206 | dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream); |
| 2207 | snd_pcm_uframes_t ret; |
| 2208 | |
| 2209 | ret = bytes_to_frames(substream->runtime, info->offset) |
| 2210 | % substream->runtime->buffer_size; |
| 2211 | dprintk(D_USR, "I/O pointer: %ld frames, %d bytes left.\n", |
| 2212 | ret, info->left); |
| 2213 | return ret; |
| 2214 | } |
| 2215 | |
| 2216 | static snd_pcm_ops_t snd_dbri_ops = { |
| 2217 | .open = snd_dbri_open, |
| 2218 | .close = snd_dbri_close, |
| 2219 | .ioctl = snd_pcm_lib_ioctl, |
| 2220 | .hw_params = snd_dbri_hw_params, |
| 2221 | .hw_free = snd_dbri_hw_free, |
| 2222 | .prepare = snd_dbri_prepare, |
| 2223 | .trigger = snd_dbri_trigger, |
| 2224 | .pointer = snd_dbri_pointer, |
| 2225 | }; |
| 2226 | |
| 2227 | static int __devinit snd_dbri_pcm(snd_dbri_t * dbri) |
| 2228 | { |
| 2229 | snd_pcm_t *pcm; |
| 2230 | int err; |
| 2231 | |
| 2232 | if ((err = snd_pcm_new(dbri->card, |
| 2233 | /* ID */ "sun_dbri", |
| 2234 | /* device */ 0, |
| 2235 | /* playback count */ 1, |
| 2236 | /* capture count */ 1, &pcm)) < 0) |
| 2237 | return err; |
| 2238 | snd_assert(pcm != NULL, return -EINVAL); |
| 2239 | |
| 2240 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops); |
| 2241 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops); |
| 2242 | |
| 2243 | pcm->private_data = dbri; |
| 2244 | pcm->info_flags = 0; |
| 2245 | strcpy(pcm->name, dbri->card->shortname); |
| 2246 | dbri->pcm = pcm; |
| 2247 | |
| 2248 | if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm, |
| 2249 | SNDRV_DMA_TYPE_CONTINUOUS, |
| 2250 | snd_dma_continuous_data(GFP_KERNEL), |
| 2251 | 64 * 1024, 64 * 1024)) < 0) { |
| 2252 | return err; |
| 2253 | } |
| 2254 | |
| 2255 | return 0; |
| 2256 | } |
| 2257 | |
| 2258 | /***************************************************************************** |
| 2259 | Mixer interface |
| 2260 | *****************************************************************************/ |
| 2261 | |
| 2262 | static int snd_cs4215_info_volume(snd_kcontrol_t * kcontrol, |
| 2263 | snd_ctl_elem_info_t * uinfo) |
| 2264 | { |
| 2265 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
| 2266 | uinfo->count = 2; |
| 2267 | uinfo->value.integer.min = 0; |
| 2268 | if (kcontrol->private_value == DBRI_PLAY) { |
| 2269 | uinfo->value.integer.max = DBRI_MAX_VOLUME; |
| 2270 | } else { |
| 2271 | uinfo->value.integer.max = DBRI_MAX_GAIN; |
| 2272 | } |
| 2273 | return 0; |
| 2274 | } |
| 2275 | |
| 2276 | static int snd_cs4215_get_volume(snd_kcontrol_t * kcontrol, |
| 2277 | snd_ctl_elem_value_t * ucontrol) |
| 2278 | { |
| 2279 | snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol); |
| 2280 | dbri_streaminfo_t *info; |
| 2281 | snd_assert(dbri != NULL, return -EINVAL); |
| 2282 | info = &dbri->stream_info[kcontrol->private_value]; |
| 2283 | snd_assert(info != NULL, return -EINVAL); |
| 2284 | |
| 2285 | ucontrol->value.integer.value[0] = info->left_gain; |
| 2286 | ucontrol->value.integer.value[1] = info->right_gain; |
| 2287 | return 0; |
| 2288 | } |
| 2289 | |
| 2290 | static int snd_cs4215_put_volume(snd_kcontrol_t * kcontrol, |
| 2291 | snd_ctl_elem_value_t * ucontrol) |
| 2292 | { |
| 2293 | snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol); |
| 2294 | dbri_streaminfo_t *info = &dbri->stream_info[kcontrol->private_value]; |
| 2295 | unsigned long flags; |
| 2296 | int changed = 0; |
| 2297 | |
| 2298 | if (info->left_gain != ucontrol->value.integer.value[0]) { |
| 2299 | info->left_gain = ucontrol->value.integer.value[0]; |
| 2300 | changed = 1; |
| 2301 | } |
| 2302 | if (info->right_gain != ucontrol->value.integer.value[1]) { |
| 2303 | info->right_gain = ucontrol->value.integer.value[1]; |
| 2304 | changed = 1; |
| 2305 | } |
| 2306 | if (changed == 1) { |
| 2307 | /* First mute outputs, and wait 1/8000 sec (125 us) |
| 2308 | * to make sure this takes. This avoids clicking noises. |
| 2309 | */ |
| 2310 | spin_lock_irqsave(&dbri->lock, flags); |
| 2311 | |
| 2312 | cs4215_setdata(dbri, 1); |
| 2313 | udelay(125); |
| 2314 | cs4215_setdata(dbri, 0); |
| 2315 | |
| 2316 | spin_unlock_irqrestore(&dbri->lock, flags); |
| 2317 | } |
| 2318 | return changed; |
| 2319 | } |
| 2320 | |
| 2321 | static int snd_cs4215_info_single(snd_kcontrol_t * kcontrol, |
| 2322 | snd_ctl_elem_info_t * uinfo) |
| 2323 | { |
| 2324 | int mask = (kcontrol->private_value >> 16) & 0xff; |
| 2325 | |
| 2326 | uinfo->type = (mask == 1) ? |
| 2327 | SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; |
| 2328 | uinfo->count = 1; |
| 2329 | uinfo->value.integer.min = 0; |
| 2330 | uinfo->value.integer.max = mask; |
| 2331 | return 0; |
| 2332 | } |
| 2333 | |
| 2334 | static int snd_cs4215_get_single(snd_kcontrol_t * kcontrol, |
| 2335 | snd_ctl_elem_value_t * ucontrol) |
| 2336 | { |
| 2337 | snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol); |
| 2338 | int elem = kcontrol->private_value & 0xff; |
| 2339 | int shift = (kcontrol->private_value >> 8) & 0xff; |
| 2340 | int mask = (kcontrol->private_value >> 16) & 0xff; |
| 2341 | int invert = (kcontrol->private_value >> 24) & 1; |
| 2342 | snd_assert(dbri != NULL, return -EINVAL); |
| 2343 | |
| 2344 | if (elem < 4) { |
| 2345 | ucontrol->value.integer.value[0] = |
| 2346 | (dbri->mm.data[elem] >> shift) & mask; |
| 2347 | } else { |
| 2348 | ucontrol->value.integer.value[0] = |
| 2349 | (dbri->mm.ctrl[elem - 4] >> shift) & mask; |
| 2350 | } |
| 2351 | |
| 2352 | if (invert == 1) { |
| 2353 | ucontrol->value.integer.value[0] = |
| 2354 | mask - ucontrol->value.integer.value[0]; |
| 2355 | } |
| 2356 | return 0; |
| 2357 | } |
| 2358 | |
| 2359 | static int snd_cs4215_put_single(snd_kcontrol_t * kcontrol, |
| 2360 | snd_ctl_elem_value_t * ucontrol) |
| 2361 | { |
| 2362 | snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol); |
| 2363 | unsigned long flags; |
| 2364 | int elem = kcontrol->private_value & 0xff; |
| 2365 | int shift = (kcontrol->private_value >> 8) & 0xff; |
| 2366 | int mask = (kcontrol->private_value >> 16) & 0xff; |
| 2367 | int invert = (kcontrol->private_value >> 24) & 1; |
| 2368 | int changed = 0; |
| 2369 | unsigned short val; |
| 2370 | snd_assert(dbri != NULL, return -EINVAL); |
| 2371 | |
| 2372 | val = (ucontrol->value.integer.value[0] & mask); |
| 2373 | if (invert == 1) |
| 2374 | val = mask - val; |
| 2375 | val <<= shift; |
| 2376 | |
| 2377 | if (elem < 4) { |
| 2378 | dbri->mm.data[elem] = (dbri->mm.data[elem] & |
| 2379 | ~(mask << shift)) | val; |
| 2380 | changed = (val != dbri->mm.data[elem]); |
| 2381 | } else { |
| 2382 | dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] & |
| 2383 | ~(mask << shift)) | val; |
| 2384 | changed = (val != dbri->mm.ctrl[elem - 4]); |
| 2385 | } |
| 2386 | |
| 2387 | dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, " |
| 2388 | "mixer-value=%ld, mm-value=0x%x\n", |
| 2389 | mask, changed, ucontrol->value.integer.value[0], |
| 2390 | dbri->mm.data[elem & 3]); |
| 2391 | |
| 2392 | if (changed) { |
| 2393 | /* First mute outputs, and wait 1/8000 sec (125 us) |
| 2394 | * to make sure this takes. This avoids clicking noises. |
| 2395 | */ |
| 2396 | spin_lock_irqsave(&dbri->lock, flags); |
| 2397 | |
| 2398 | cs4215_setdata(dbri, 1); |
| 2399 | udelay(125); |
| 2400 | cs4215_setdata(dbri, 0); |
| 2401 | |
| 2402 | spin_unlock_irqrestore(&dbri->lock, flags); |
| 2403 | } |
| 2404 | return changed; |
| 2405 | } |
| 2406 | |
| 2407 | /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control |
| 2408 | timeslots. Shift is the bit offset in the timeslot, mask defines the |
| 2409 | number of bits. invert is a boolean for use with attenuation. |
| 2410 | */ |
| 2411 | #define CS4215_SINGLE(xname, entry, shift, mask, invert) \ |
| 2412 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ |
| 2413 | .info = snd_cs4215_info_single, \ |
| 2414 | .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \ |
| 2415 | .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) }, |
| 2416 | |
| 2417 | static snd_kcontrol_new_t dbri_controls[] __devinitdata = { |
| 2418 | { |
| 2419 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
| 2420 | .name = "Playback Volume", |
| 2421 | .info = snd_cs4215_info_volume, |
| 2422 | .get = snd_cs4215_get_volume, |
| 2423 | .put = snd_cs4215_put_volume, |
| 2424 | .private_value = DBRI_PLAY, |
| 2425 | }, |
| 2426 | CS4215_SINGLE("Headphone switch", 0, 7, 1, 0) |
| 2427 | CS4215_SINGLE("Line out switch", 0, 6, 1, 0) |
| 2428 | CS4215_SINGLE("Speaker switch", 1, 6, 1, 0) |
| 2429 | { |
| 2430 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
| 2431 | .name = "Capture Volume", |
| 2432 | .info = snd_cs4215_info_volume, |
| 2433 | .get = snd_cs4215_get_volume, |
| 2434 | .put = snd_cs4215_put_volume, |
| 2435 | .private_value = DBRI_REC, |
| 2436 | }, |
| 2437 | /* FIXME: mic/line switch */ |
| 2438 | CS4215_SINGLE("Line in switch", 2, 4, 1, 0) |
| 2439 | CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0) |
| 2440 | CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1) |
| 2441 | CS4215_SINGLE("Mic boost", 4, 4, 1, 1) |
| 2442 | }; |
| 2443 | |
| 2444 | #define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(snd_kcontrol_new_t)) |
| 2445 | |
| 2446 | static int __init snd_dbri_mixer(snd_dbri_t * dbri) |
| 2447 | { |
| 2448 | snd_card_t *card; |
| 2449 | int idx, err; |
| 2450 | |
| 2451 | snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL); |
| 2452 | |
| 2453 | card = dbri->card; |
| 2454 | strcpy(card->mixername, card->shortname); |
| 2455 | |
| 2456 | for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) { |
| 2457 | if ((err = snd_ctl_add(card, |
| 2458 | snd_ctl_new1(&dbri_controls[idx], |
| 2459 | dbri))) < 0) |
| 2460 | return err; |
| 2461 | } |
| 2462 | |
| 2463 | for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) { |
| 2464 | dbri->stream_info[idx].left_gain = 0; |
| 2465 | dbri->stream_info[idx].right_gain = 0; |
| 2466 | dbri->stream_info[idx].balance = DBRI_MID_BALANCE; |
| 2467 | } |
| 2468 | |
| 2469 | return 0; |
| 2470 | } |
| 2471 | |
| 2472 | /**************************************************************************** |
| 2473 | /proc interface |
| 2474 | ****************************************************************************/ |
| 2475 | static void dbri_regs_read(snd_info_entry_t * entry, snd_info_buffer_t * buffer) |
| 2476 | { |
| 2477 | snd_dbri_t *dbri = entry->private_data; |
| 2478 | |
| 2479 | snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0)); |
| 2480 | snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2)); |
| 2481 | snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8)); |
| 2482 | snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9)); |
| 2483 | } |
| 2484 | |
| 2485 | #ifdef DBRI_DEBUG |
| 2486 | static void dbri_debug_read(snd_info_entry_t * entry, |
| 2487 | snd_info_buffer_t * buffer) |
| 2488 | { |
| 2489 | snd_dbri_t *dbri = entry->private_data; |
| 2490 | int pipe; |
| 2491 | snd_iprintf(buffer, "debug=%d\n", dbri_debug); |
| 2492 | |
| 2493 | snd_iprintf(buffer, "CHI pipe in=%d, out=%d\n", |
| 2494 | dbri->chi_in_pipe, dbri->chi_out_pipe); |
| 2495 | for (pipe = 0; pipe < 32; pipe++) { |
| 2496 | if (pipe_active(dbri, pipe)) { |
| 2497 | struct dbri_pipe *pptr = &dbri->pipes[pipe]; |
| 2498 | snd_iprintf(buffer, |
| 2499 | "Pipe %d: %s SDP=0x%x desc=%d, " |
| 2500 | "len=%d @ %d prev: %d next %d\n", |
| 2501 | pipe, |
| 2502 | (pptr->direction == |
| 2503 | PIPEinput ? "input" : "output"), pptr->sdp, |
| 2504 | pptr->desc, pptr->length, pptr->cycle, |
| 2505 | pptr->prevpipe, pptr->nextpipe); |
| 2506 | } |
| 2507 | } |
| 2508 | } |
| 2509 | |
| 2510 | static void dbri_debug_write(snd_info_entry_t * entry, |
| 2511 | snd_info_buffer_t * buffer) |
| 2512 | { |
| 2513 | char line[80]; |
| 2514 | int i; |
| 2515 | |
| 2516 | if (snd_info_get_line(buffer, line, 80) == 0) { |
| 2517 | sscanf(line, "%d\n", &i); |
| 2518 | dbri_debug = i & 0x3f; |
| 2519 | } |
| 2520 | } |
| 2521 | #endif |
| 2522 | |
| 2523 | void snd_dbri_proc(snd_dbri_t * dbri) |
| 2524 | { |
| 2525 | snd_info_entry_t *entry; |
| 2526 | int err; |
| 2527 | |
| 2528 | err = snd_card_proc_new(dbri->card, "regs", &entry); |
| 2529 | snd_info_set_text_ops(entry, dbri, 1024, dbri_regs_read); |
| 2530 | |
| 2531 | #ifdef DBRI_DEBUG |
| 2532 | err = snd_card_proc_new(dbri->card, "debug", &entry); |
| 2533 | snd_info_set_text_ops(entry, dbri, 4096, dbri_debug_read); |
| 2534 | entry->mode = S_IFREG | S_IRUGO | S_IWUSR; /* Writable for root */ |
| 2535 | entry->c.text.write_size = 256; |
| 2536 | entry->c.text.write = dbri_debug_write; |
| 2537 | #endif |
| 2538 | } |
| 2539 | |
| 2540 | /* |
| 2541 | **************************************************************************** |
| 2542 | **************************** Initialization ******************************** |
| 2543 | **************************************************************************** |
| 2544 | */ |
| 2545 | static void snd_dbri_free(snd_dbri_t * dbri); |
| 2546 | |
| 2547 | static int __init snd_dbri_create(snd_card_t * card, |
| 2548 | struct sbus_dev *sdev, |
| 2549 | struct linux_prom_irqs *irq, int dev) |
| 2550 | { |
| 2551 | snd_dbri_t *dbri = card->private_data; |
| 2552 | int err; |
| 2553 | |
| 2554 | spin_lock_init(&dbri->lock); |
| 2555 | dbri->card = card; |
| 2556 | dbri->sdev = sdev; |
| 2557 | dbri->irq = irq->pri; |
| 2558 | dbri->dbri_version = sdev->prom_name[9]; |
| 2559 | |
| 2560 | dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma), |
| 2561 | &dbri->dma_dvma); |
| 2562 | memset((void *)dbri->dma, 0, sizeof(struct dbri_dma)); |
| 2563 | |
| 2564 | dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n", |
| 2565 | dbri->dma, dbri->dma_dvma); |
| 2566 | |
| 2567 | /* Map the registers into memory. */ |
| 2568 | dbri->regs_size = sdev->reg_addrs[0].reg_size; |
| 2569 | dbri->regs = sbus_ioremap(&sdev->resource[0], 0, |
| 2570 | dbri->regs_size, "DBRI Registers"); |
| 2571 | if (!dbri->regs) { |
| 2572 | printk(KERN_ERR "DBRI: could not allocate registers\n"); |
| 2573 | sbus_free_consistent(sdev, sizeof(struct dbri_dma), |
| 2574 | (void *)dbri->dma, dbri->dma_dvma); |
| 2575 | return -EIO; |
| 2576 | } |
| 2577 | |
| 2578 | err = request_irq(dbri->irq, snd_dbri_interrupt, SA_SHIRQ, |
| 2579 | "DBRI audio", dbri); |
| 2580 | if (err) { |
| 2581 | printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq); |
| 2582 | sbus_iounmap(dbri->regs, dbri->regs_size); |
| 2583 | sbus_free_consistent(sdev, sizeof(struct dbri_dma), |
| 2584 | (void *)dbri->dma, dbri->dma_dvma); |
| 2585 | return err; |
| 2586 | } |
| 2587 | |
| 2588 | /* Do low level initialization of the DBRI and CS4215 chips */ |
| 2589 | dbri_initialize(dbri); |
| 2590 | err = cs4215_init(dbri); |
| 2591 | if (err) { |
| 2592 | snd_dbri_free(dbri); |
| 2593 | return err; |
| 2594 | } |
| 2595 | |
| 2596 | dbri->next = dbri_list; |
| 2597 | dbri_list = dbri; |
| 2598 | |
| 2599 | return 0; |
| 2600 | } |
| 2601 | |
| 2602 | static void snd_dbri_free(snd_dbri_t * dbri) |
| 2603 | { |
| 2604 | dprintk(D_GEN, "snd_dbri_free\n"); |
| 2605 | dbri_reset(dbri); |
| 2606 | |
| 2607 | if (dbri->irq) |
| 2608 | free_irq(dbri->irq, dbri); |
| 2609 | |
| 2610 | if (dbri->regs) |
| 2611 | sbus_iounmap(dbri->regs, dbri->regs_size); |
| 2612 | |
| 2613 | if (dbri->dma) |
| 2614 | sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma), |
| 2615 | (void *)dbri->dma, dbri->dma_dvma); |
| 2616 | } |
| 2617 | |
| 2618 | static int __init dbri_attach(int prom_node, struct sbus_dev *sdev) |
| 2619 | { |
| 2620 | snd_dbri_t *dbri; |
| 2621 | struct linux_prom_irqs irq; |
| 2622 | struct resource *rp; |
| 2623 | snd_card_t *card; |
| 2624 | static int dev = 0; |
| 2625 | int err; |
| 2626 | |
| 2627 | if (sdev->prom_name[9] < 'e') { |
| 2628 | printk(KERN_ERR "DBRI: unsupported chip version %c found.\n", |
| 2629 | sdev->prom_name[9]); |
| 2630 | return -EIO; |
| 2631 | } |
| 2632 | |
| 2633 | if (dev >= SNDRV_CARDS) |
| 2634 | return -ENODEV; |
| 2635 | if (!enable[dev]) { |
| 2636 | dev++; |
| 2637 | return -ENOENT; |
| 2638 | } |
| 2639 | |
| 2640 | prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq)); |
| 2641 | |
| 2642 | card = snd_card_new(index[dev], id[dev], THIS_MODULE, |
| 2643 | sizeof(snd_dbri_t)); |
| 2644 | if (card == NULL) |
| 2645 | return -ENOMEM; |
| 2646 | |
| 2647 | strcpy(card->driver, "DBRI"); |
| 2648 | strcpy(card->shortname, "Sun DBRI"); |
| 2649 | rp = &sdev->resource[0]; |
| 2650 | sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s", |
| 2651 | card->shortname, |
| 2652 | rp->flags & 0xffL, rp->start, __irq_itoa(irq.pri)); |
| 2653 | |
| 2654 | if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) { |
| 2655 | snd_card_free(card); |
| 2656 | return err; |
| 2657 | } |
| 2658 | |
| 2659 | dbri = (snd_dbri_t *) card->private_data; |
Takashi Iwai | 16dab54 | 2005-09-05 17:17:58 +0200 | [diff] [blame^] | 2660 | if ((err = snd_dbri_pcm(dbri)) < 0) |
| 2661 | goto _err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2662 | |
Takashi Iwai | 16dab54 | 2005-09-05 17:17:58 +0200 | [diff] [blame^] | 2663 | if ((err = snd_dbri_mixer(dbri)) < 0) |
| 2664 | goto _err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2665 | |
| 2666 | /* /proc file handling */ |
| 2667 | snd_dbri_proc(dbri); |
| 2668 | |
Takashi Iwai | 16dab54 | 2005-09-05 17:17:58 +0200 | [diff] [blame^] | 2669 | if ((err = snd_card_set_generic_dev(card)) < 0) |
| 2670 | goto _err; |
| 2671 | |
| 2672 | if ((err = snd_card_register(card)) < 0) |
| 2673 | goto _err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2674 | |
| 2675 | printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n", |
| 2676 | dev, dbri->regs, |
| 2677 | dbri->irq, dbri->dbri_version, dbri->mm.version); |
| 2678 | dev++; |
| 2679 | |
| 2680 | return 0; |
Takashi Iwai | 16dab54 | 2005-09-05 17:17:58 +0200 | [diff] [blame^] | 2681 | |
| 2682 | _err: |
| 2683 | snd_dbri_free(dbri); |
| 2684 | snd_card_free(card); |
| 2685 | return err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2686 | } |
| 2687 | |
| 2688 | /* Probe for the dbri chip and then attach the driver. */ |
| 2689 | static int __init dbri_init(void) |
| 2690 | { |
| 2691 | struct sbus_bus *sbus; |
| 2692 | struct sbus_dev *sdev; |
| 2693 | int found = 0; |
| 2694 | |
| 2695 | /* Probe each SBUS for the DBRI chip(s). */ |
| 2696 | for_all_sbusdev(sdev, sbus) { |
| 2697 | /* |
| 2698 | * The version is coded in the last character |
| 2699 | */ |
| 2700 | if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) { |
| 2701 | dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n", |
| 2702 | sdev->prom_name, sdev->slot); |
| 2703 | |
| 2704 | if (dbri_attach(sdev->prom_node, sdev) == 0) |
| 2705 | found++; |
| 2706 | } |
| 2707 | } |
| 2708 | |
| 2709 | return (found > 0) ? 0 : -EIO; |
| 2710 | } |
| 2711 | |
| 2712 | static void __exit dbri_exit(void) |
| 2713 | { |
| 2714 | snd_dbri_t *this = dbri_list; |
| 2715 | |
| 2716 | while (this != NULL) { |
| 2717 | snd_dbri_t *next = this->next; |
| 2718 | snd_card_t *card = this->card; |
| 2719 | |
| 2720 | snd_dbri_free(this); |
| 2721 | snd_card_free(card); |
| 2722 | this = next; |
| 2723 | } |
| 2724 | dbri_list = NULL; |
| 2725 | } |
| 2726 | |
| 2727 | module_init(dbri_init); |
| 2728 | module_exit(dbri_exit); |