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gerrit-public.fairphone.software / kernel / msm-4.9 / 173d6681380aa1d60dfc35ed7178bd7811ba2784 / . / arch / xtensa / mm / misc.S
blob: ae085332c607095281bf1ad963c0f6c213c5eeeb [file] [log] [blame]
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]1/*
2 * arch/xtensa/mm/misc.S
3 *
4 * Miscellaneous assembly functions.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 *
12 * Chris Zankel <chris@zankel.net>
13 */
14
15/* Note: we might want to implement some of the loops as zero-overhead-loops,
16 * where applicable and if supported by the processor.
17 */
18
19#include <linux/linkage.h>
20#include <asm/page.h>
21#include <asm/pgtable.h>
Chris Zankel173d66812006-12-10 02:18:48 -0800[diff] [blame^]22#include <asm/asmmacro.h>
23#include <asm/cacheasm.h>
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]24
25/* clear_page (page) */
26
27ENTRY(clear_page)
28 entry a1, 16
29 addi a4, a2, PAGE_SIZE
30 movi a3, 0
31
321: s32i a3, a2, 0
33 s32i a3, a2, 4
34 s32i a3, a2, 8
35 s32i a3, a2, 12
36 s32i a3, a2, 16
37 s32i a3, a2, 20
38 s32i a3, a2, 24
39 s32i a3, a2, 28
40 addi a2, a2, 32
41 blt a2, a4, 1b
42
43 retw
44
45/*
46 * copy_page (void *to, void *from)
47 * a2 a3
48 */
49
50ENTRY(copy_page)
51 entry a1, 16
52 addi a4, a2, PAGE_SIZE
53
541: l32i a5, a3, 0
55 l32i a6, a3, 4
56 l32i a7, a3, 8
57 s32i a5, a2, 0
58 s32i a6, a2, 4
59 s32i a7, a2, 8
60 l32i a5, a3, 12
61 l32i a6, a3, 16
62 l32i a7, a3, 20
63 s32i a5, a2, 12
64 s32i a6, a2, 16
65 s32i a7, a2, 20
66 l32i a5, a3, 24
67 l32i a6, a3, 28
68 s32i a5, a2, 24
69 s32i a6, a2, 28
70 addi a2, a2, 32
71 addi a3, a3, 32
72 blt a2, a4, 1b
73
74 retw
75
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]76/*
77 * void __invalidate_icache_page(ulong start)
78 */
79
80ENTRY(__invalidate_icache_page)
81 entry sp, 16
Chris Zankel173d66812006-12-10 02:18:48 -0800[diff] [blame^]82
83 ___invalidate_icache_page a2 a3
84 isync
85
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]86 retw
87
88/*
89 * void __invalidate_dcache_page(ulong start)
90 */
91
92ENTRY(__invalidate_dcache_page)
93 entry sp, 16
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]94
Chris Zankel173d66812006-12-10 02:18:48 -0800[diff] [blame^]95 ___invalidate_dcache_page a2 a3
96 dsync
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]97
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]98 retw
99
100/*
101 * void __flush_invalidate_dcache_page(ulong start)
102 */
103
104ENTRY(__flush_invalidate_dcache_page)
105 entry sp, 16
Chris Zankel173d66812006-12-10 02:18:48 -0800[diff] [blame^]106
107 ___flush_invalidate_dcache_page a2 a3
108
109 dsync
110 retw
111
112/*
113 * void __flush_dcache_page(ulong start)
114 */
115
116ENTRY(__flush_dcache_page)
117 entry sp, 16
118
119 ___flush_dcache_page a2 a3
120
121 dsync
122 retw
123
124
125
126/*
127 * void __invalidate_icache_range(ulong start, ulong size)
128 */
129
130ENTRY(__invalidate_icache_range)
131 entry sp, 16
132
133 ___invalidate_icache_range a2 a3 a4
134 isync
135
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]136 retw
137
138/*
139 * void __flush_invalidate_dcache_range(ulong start, ulong size)
140 */
141
142ENTRY(__flush_invalidate_dcache_range)
143 entry sp, 16
Chris Zankel173d66812006-12-10 02:18:48 -0800[diff] [blame^]144
145 ___flush_invalidate_dcache_range a2 a3 a4
146 dsync
147
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]148 retw
149
150/*
Chris Zankel173d66812006-12-10 02:18:48 -0800[diff] [blame^]151 * void _flush_dcache_range(ulong start, ulong size)
152 */
153
154ENTRY(__flush_dcache_range)
155 entry sp, 16
156
157 ___flush_dcache_range a2 a3 a4
158 dsync
159
160 retw
161
162/*
163 * void _invalidate_dcache_range(ulong start, ulong size)
164 */
165
166ENTRY(__invalidate_dcache_range)
167 entry sp, 16
168
169 ___invalidate_dcache_range a2 a3 a4
170
171
172 retw
173
174/*
175 * void _invalidate_icache_all(void)
176 */
177
178ENTRY(__invalidate_icache_all)
179 entry sp, 16
180
181 ___invalidate_icache_all a2 a3
182 isync
183
184 retw
185
186/*
187 * void _flush_invalidate_dcache_all(void)
188 */
189
190ENTRY(__flush_invalidate_dcache_all)
191 entry sp, 16
192
193 ___flush_invalidate_dcache_all a2 a3
194 dsync
195
196 retw
197
198/*
199 * void _invalidate_dcache_all(void)
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]200 */
201
202ENTRY(__invalidate_dcache_all)
203 entry sp, 16
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]204
Chris Zankel173d66812006-12-10 02:18:48 -0800[diff] [blame^]205 ___invalidate_dcache_all a2 a3
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]206 dsync
Chris Zankel3f65ce42005-06-23 22:01:24 -0700[diff] [blame]207
208 retw
209