| Max Filippov | 93e294a | 2013-03-04 23:48:14 +0400 | [diff] [blame] | 1 | MMUv3 initialization sequence. |
| 2 | |
| 3 | The code in the initialize_mmu macro sets up MMUv3 memory mapping |
| 4 | identically to MMUv2 fixed memory mapping. Depending on |
| 5 | CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is |
| 6 | located in one of the following address ranges: |
| 7 | |
| 8 | 0xF0000000..0xFFFFFFFF (will keep same address in MMU v2 layout; |
| 9 | typically ROM) |
| 10 | 0x00000000..0x07FFFFFF (system RAM; this code is actually linked |
| 11 | at 0xD0000000..0xD7FFFFFF [cached] |
| 12 | or 0xD8000000..0xDFFFFFFF [uncached]; |
| 13 | in any case, initially runs elsewhere |
| 14 | than linked, so have to be careful) |
| 15 | |
| 16 | The code has the following assumptions: |
| 17 | This code fragment is run only on an MMU v3. |
| 18 | TLBs are in their reset state. |
| 19 | ITLBCFG and DTLBCFG are zero (reset state). |
| 20 | RASID is 0x04030201 (reset state). |
| 21 | PS.RING is zero (reset state). |
| 22 | LITBASE is zero (reset state, PC-relative literals); required to be PIC. |
| 23 | |
| 24 | TLB setup proceeds along the following steps. |
| 25 | |
| 26 | Legend: |
| 27 | VA = virtual address (two upper nibbles of it); |
| 28 | PA = physical address (two upper nibbles of it); |
| 29 | pc = physical range that contains this code; |
| 30 | |
| 31 | After step 2, we jump to virtual address in 0x40000000..0x5fffffff |
| 32 | that corresponds to next instruction to execute in this code. |
| 33 | After step 4, we jump to intended (linked) address of this code. |
| 34 | |
| 35 | Step 0 Step1 Step 2 Step3 Step 4 Step5 |
| 36 | ============ ===== ============ ===== ============ ===== |
| 37 | VA PA PA VA PA PA VA PA PA |
| 38 | ------ -- -- ------ -- -- ------ -- -- |
| 39 | E0..FF -> E0 -> E0 E0..FF -> E0 F0..FF -> F0 -> F0 |
| 40 | C0..DF -> C0 -> C0 C0..DF -> C0 E0..EF -> F0 -> F0 |
| 41 | A0..BF -> A0 -> A0 A0..BF -> A0 D8..DF -> 00 -> 00 |
| 42 | 80..9F -> 80 -> 80 80..9F -> 80 D0..D7 -> 00 -> 00 |
| 43 | 60..7F -> 60 -> 60 60..7F -> 60 |
| 44 | 40..5F -> 40 40..5F -> pc -> pc 40..5F -> pc |
| 45 | 20..3F -> 20 -> 20 20..3F -> 20 |
| 46 | 00..1F -> 00 -> 00 00..1F -> 00 |
| Baruch Siach | 6cb9711 | 2013-12-29 11:03:30 +0200 | [diff] [blame] | 47 | |
| 48 | The default location of IO peripherals is above 0xf0000000. This may change |
| 49 | using a "ranges" property in a device tree simple-bus node. See ePAPR 1.1, ยง6.5 |
| 50 | for details on the syntax and semantic of simple-bus nodes. The following |
| 51 | limitations apply: |
| 52 | |
| 53 | 1. Only top level simple-bus nodes are considered |
| 54 | |
| 55 | 2. Only one (first) simple-bus node is considered |
| 56 | |
| 57 | 3. Empty "ranges" properties are not supported |
| 58 | |
| 59 | 4. Only the first triplet in the "ranges" property is considered |
| 60 | |
| 61 | 5. The parent-bus-address value is rounded down to the nearest 256MB boundary |
| 62 | |
| 63 | 6. The IO area covers the entire 256MB segment of parent-bus-address; the |
| 64 | "ranges" triplet length field is ignored |