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gerrit-public.fairphone.software / kernel / msm-4.9 / 1765d671b18e58fdd6341edac9c22e57d90ef6a8 / . / drivers / clk / sirf / clk-prima2.c
blob: 6968e2ebcd8a4d09959d02b2edbf5ffe19e7b9da [file] [log] [blame]
Barry Song7bf21bc2014-01-15 14:11:34 +0800[diff] [blame]1/*
2 * Clock tree for CSR SiRFprimaII
3 *
Barry Song77366922014-02-12 22:16:11 +0800[diff] [blame]4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
Barry Song7bf21bc2014-01-15 14:11:34 +0800[diff] [blame]6 *
7 * Licensed under GPLv2 or later.
8 */
9
10#include <linux/module.h>
11#include <linux/bitops.h>
12#include <linux/io.h>
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of_address.h>
17#include <linux/syscore_ops.h>
18
19#include "prima2.h"
20#include "clk-common.c"
21
22static struct clk_dmn clk_mmc01 = {
23 .regofs = SIRFSOC_CLKC_MMC_CFG,
24 .enable_bit = 59,
25 .hw = {
26 .init = &clk_mmc01_init,
27 },
28};
29
30static struct clk_dmn clk_mmc23 = {
31 .regofs = SIRFSOC_CLKC_MMC_CFG,
32 .enable_bit = 60,
33 .hw = {
34 .init = &clk_mmc23_init,
35 },
36};
37
38static struct clk_dmn clk_mmc45 = {
39 .regofs = SIRFSOC_CLKC_MMC_CFG,
40 .enable_bit = 61,
41 .hw = {
42 .init = &clk_mmc45_init,
43 },
44};
45
46static struct clk_init_data clk_nand_init = {
47 .name = "nand",
48 .ops = &ios_ops,
49 .parent_names = std_clk_io_parents,
50 .num_parents = ARRAY_SIZE(std_clk_io_parents),
51};
52
53static struct clk_std clk_nand = {
54 .enable_bit = 34,
55 .hw = {
56 .init = &clk_nand_init,
57 },
58};
59
60enum prima2_clk_index {
61 /* 0 1 2 3 4 5 6 7 8 9 */
62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
63 mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
64 spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
65 usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
66 usb0, usb1, cphif, maxclk,
67};
68
69static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = {
70 NULL, /* dummy */
71 NULL,
72 &clk_pll1.hw,
73 &clk_pll2.hw,
74 &clk_pll3.hw,
75 &clk_mem.hw,
76 &clk_sys.hw,
77 &clk_security.hw,
78 &clk_dsp.hw,
79 &clk_gps.hw,
80 &clk_mf.hw,
81 &clk_io.hw,
82 &clk_cpu.hw,
83 &clk_uart0.hw,
84 &clk_uart1.hw,
85 &clk_uart2.hw,
86 &clk_tsc.hw,
87 &clk_i2c0.hw,
88 &clk_i2c1.hw,
89 &clk_spi0.hw,
90 &clk_spi1.hw,
91 &clk_pwmc.hw,
92 &clk_efuse.hw,
93 &clk_pulse.hw,
94 &clk_dmac0.hw,
95 &clk_dmac1.hw,
96 &clk_nand.hw,
97 &clk_audio.hw,
98 &clk_usp0.hw,
99 &clk_usp1.hw,
100 &clk_usp2.hw,
101 &clk_vip.hw,
102 &clk_gfx.hw,
103 &clk_mm.hw,
104 &clk_lcd.hw,
105 &clk_vpp.hw,
106 &clk_mmc01.hw,
107 &clk_mmc23.hw,
108 &clk_mmc45.hw,
109 &usb_pll_clk_hw,
110 &clk_usb0.hw,
111 &clk_usb1.hw,
112 &clk_cphif.hw,
113};
114
115static struct clk *prima2_clks[maxclk];
116
117static void __init prima2_clk_init(struct device_node *np)
118{
119 struct device_node *rscnp;
120 int i;
121
122 rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
123 sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
124 if (!sirfsoc_rsc_vbase)
125 panic("unable to map rsc registers\n");
126 of_node_put(rscnp);
127
128 sirfsoc_clk_vbase = of_iomap(np, 0);
129 if (!sirfsoc_clk_vbase)
130 panic("unable to map clkc registers\n");
131
132 /* These are always available (RTC and 26MHz OSC)*/
133 prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
134 CLK_IS_ROOT, 32768);
135 prima2_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL,
136 CLK_IS_ROOT, 26000000);
137
138 for (i = pll1; i < maxclk; i++) {
139 prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
140 BUG_ON(!prima2_clks[i]);
141 }
142 clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
143 clk_register_clkdev(prima2_clks[io], NULL, "io");
144 clk_register_clkdev(prima2_clks[mem], NULL, "mem");
145 clk_register_clkdev(prima2_clks[mem], NULL, "osc");
146
147 clk_data.clks = prima2_clks;
148 clk_data.clk_num = maxclk;
149
150 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
151}
152CLK_OF_DECLARE(prima2_clk, "sirf,prima2-clkc", prima2_clk_init);