blob: 84a88ca9200821c4fbd9b1266967ded716c89d72 [file] [log] [blame]
Paul Mundt2d5efc12009-04-20 21:42:59 +09001#include <linux/kernel.h>
2#include <linux/types.h>
3#include <linux/init.h>
4#include <linux/delay.h>
5#include <linux/pci.h>
6#include <linux/io.h>
Paul Mundt58796ce2012-05-18 17:42:29 +09007#include <linux/sh_intc.h>
Paul Mundt2d5efc12009-04-20 21:42:59 +09008#include "pci-sh4.h"
9
Ralf Baechled5341942011-06-10 15:30:21 +010010int __init pcibios_map_platform_irq(const struct pci_dev *, u8 slot, u8 pin)
Paul Mundt2d5efc12009-04-20 21:42:59 +090011{
12 switch (slot) {
Paul Mundt58796ce2012-05-18 17:42:29 +090013 case 0: return evt2irq(0x3a0);
14 case 1: return evt2irq(0x3a0); /* AMD Ethernet controller */
Paul Mundt2d5efc12009-04-20 21:42:59 +090015 case 2: return -1;
16 case 3: return -1;
17 case 4: return -1;
18 default:
19 printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
20 return -1;
21 }
22}
23
24#define PCIMCR_MRSET_OFF 0xBFFFFFFF
25#define PCIMCR_RFSH_OFF 0xFFFFFFFB
26
27/*
28 * Only long word accesses of the PCIC's internal local registers and the
29 * configuration registers from the CPU is supported.
30 */
31#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
32#define PCIC_READ(x) readl(PCI_REG(x))
33
34/*
35 * Description: This function sets up and initializes the pcic, sets
36 * up the BARS, maps the DRAM into the address space etc, etc.
37 */
38int pci_fixup_pcic(struct pci_channel *chan)
39{
40 unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
41 unsigned short bcr2;
42
43 /*
44 * Initialize the slave bus controller on the pcic. The values used
45 * here should not be hardcoded, but they should be taken from the bsc
46 * on the processor, to make this function as generic as possible.
47 * (i.e. Another sbc may usr different SDRAM timing settings -- in order
48 * for the pcic to work, its settings need to be exactly the same.)
49 */
50 bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
51 bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
52 wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
53 wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
54 wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
55 mcr = (*(volatile unsigned long*)(SH7751_MCR));
56
57 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
58 (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
59
60 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
61 PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
62 PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
63 PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
64 PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
65 PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
66 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
67 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
68
69
70 /* Enable all interrupts, so we know what to fix */
71 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
72 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
73
74 /* Set up standard PCI config registers */
75 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
76 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
77 PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
78 PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
79 PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
80 PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
81 PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
82 PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
83 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
84 PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
85
86 /* Now turn it on... */
87 PCIC_WRITE(SH7751_PCICR, 0xa5000001);
88
89 /*
90 * Set PCIMBR and PCIIOBR here, assuming a single window
91 * (16M MEM, 256K IO) is enough. If a larger space is
92 * needed, the readx/writex and inx/outx functions will
93 * have to do more (e.g. setting registers for each call).
94 */
95
96 /*
97 * Set the MBR so PCI address is one-to-one with window,
98 * meaning all calls go straight through... use BUG_ON to
99 * catch erroneous assumption.
100 */
Paul Mundtb6c58b12010-02-01 20:01:50 +0900101 BUG_ON(chan->resources[1].start != SH7751_PCI_MEMORY_BASE);
Paul Mundt2d5efc12009-04-20 21:42:59 +0900102
Paul Mundtb6c58b12010-02-01 20:01:50 +0900103 PCIC_WRITE(SH7751_PCIMBR, chan->resources[1].start);
Paul Mundt2d5efc12009-04-20 21:42:59 +0900104
105 /* Set IOBR for window containing area specified in pci.h */
Paul Mundtb6c58b12010-02-01 20:01:50 +0900106 PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK));
Paul Mundt2d5efc12009-04-20 21:42:59 +0900107
108 /* All done, may as well say so... */
109 printk("SH7751 PCI: Finished initialization of the PCI controller\n");
110
111 return 1;
112}