Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1 | /* |
Sujith Manoharan | 5b68138 | 2011-05-17 13:36:18 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
Luis R. Rodriguez | 990b70a | 2009-09-13 23:55:05 -0700 | [diff] [blame] | 17 | #include "hw.h" |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 18 | #include "hw-ops.h" |
Paul Gortmaker | ee40fa0 | 2011-05-27 16:14:23 -0400 | [diff] [blame] | 19 | #include <linux/export.h> |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 20 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 21 | static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 22 | struct ath9k_tx_queue_info *qi) |
| 23 | { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 24 | ath_dbg(ath9k_hw_common(ah), INTERRUPT, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 25 | "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", |
| 26 | ah->txok_interrupt_mask, ah->txerr_interrupt_mask, |
| 27 | ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, |
| 28 | ah->txurn_interrupt_mask); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 29 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 30 | ENABLE_REGWRITE_BUFFER(ah); |
| 31 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 32 | REG_WRITE(ah, AR_IMR_S0, |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 33 | SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) |
| 34 | | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 35 | REG_WRITE(ah, AR_IMR_S1, |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 36 | SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) |
| 37 | | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); |
Pavel Roskin | 74bad5c | 2010-02-23 18:15:27 -0500 | [diff] [blame] | 38 | |
| 39 | ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN; |
| 40 | ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN); |
| 41 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 42 | |
| 43 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 44 | } |
| 45 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 46 | u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 47 | { |
| 48 | return REG_READ(ah, AR_QTXDP(q)); |
| 49 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 50 | EXPORT_SYMBOL(ath9k_hw_gettxbuf); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 51 | |
Sujith | 54e4cec | 2009-08-07 09:45:09 +0530 | [diff] [blame] | 52 | void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 53 | { |
| 54 | REG_WRITE(ah, AR_QTXDP(q), txdp); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 55 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 56 | EXPORT_SYMBOL(ath9k_hw_puttxbuf); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 57 | |
Sujith | 54e4cec | 2009-08-07 09:45:09 +0530 | [diff] [blame] | 58 | void ath9k_hw_txstart(struct ath_hw *ah, u32 q) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 59 | { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 60 | ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 61 | REG_WRITE(ah, AR_Q_TXE, 1 << q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 62 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 63 | EXPORT_SYMBOL(ath9k_hw_txstart); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 64 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 65 | u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 66 | { |
| 67 | u32 npend; |
| 68 | |
| 69 | npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; |
| 70 | if (npend == 0) { |
| 71 | |
| 72 | if (REG_READ(ah, AR_Q_TXE) & (1 << q)) |
| 73 | npend = 1; |
| 74 | } |
| 75 | |
| 76 | return npend; |
| 77 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 78 | EXPORT_SYMBOL(ath9k_hw_numtxpending); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 79 | |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 80 | /** |
| 81 | * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level |
| 82 | * |
| 83 | * @ah: atheros hardware struct |
| 84 | * @bIncTrigLevel: whether or not the frame trigger level should be updated |
| 85 | * |
| 86 | * The frame trigger level specifies the minimum number of bytes, |
| 87 | * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO |
| 88 | * before the PCU will initiate sending the frame on the air. This can |
| 89 | * mean we initiate transmit before a full frame is on the PCU TX FIFO. |
| 90 | * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs |
| 91 | * first) |
| 92 | * |
| 93 | * Caution must be taken to ensure to set the frame trigger level based |
| 94 | * on the DMA request size. For example if the DMA request size is set to |
| 95 | * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because |
| 96 | * there need to be enough space in the tx FIFO for the requested transfer |
| 97 | * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set |
| 98 | * the threshold to a value beyond 6, then the transmit will hang. |
| 99 | * |
| 100 | * Current dual stream devices have a PCU TX FIFO size of 8 KB. |
| 101 | * Current single stream devices have a PCU TX FIFO size of 4 KB, however, |
| 102 | * there is a hardware issue which forces us to use 2 KB instead so the |
| 103 | * frame trigger level must not exceed 2 KB for these chipsets. |
| 104 | */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 105 | bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 106 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 107 | u32 txcfg, curLevel, newLevel; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 108 | |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 109 | if (ah->tx_trig_level >= ah->config.max_txtrig_level) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 110 | return false; |
| 111 | |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 112 | ath9k_hw_disable_interrupts(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 113 | |
| 114 | txcfg = REG_READ(ah, AR_TXCFG); |
| 115 | curLevel = MS(txcfg, AR_FTRIG); |
| 116 | newLevel = curLevel; |
| 117 | if (bIncTrigLevel) { |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 118 | if (curLevel < ah->config.max_txtrig_level) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 119 | newLevel++; |
| 120 | } else if (curLevel > MIN_TX_FIFO_THRESHOLD) |
| 121 | newLevel--; |
| 122 | if (newLevel != curLevel) |
| 123 | REG_WRITE(ah, AR_TXCFG, |
| 124 | (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); |
| 125 | |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 126 | ath9k_hw_enable_interrupts(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 127 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 128 | ah->tx_trig_level = newLevel; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 129 | |
| 130 | return newLevel != curLevel; |
| 131 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 132 | EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 133 | |
Felix Fietkau | 0d51ccc | 2011-03-11 21:38:18 +0100 | [diff] [blame] | 134 | void ath9k_hw_abort_tx_dma(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 135 | { |
Felix Fietkau | 8d1bd2a | 2012-04-19 21:18:29 +0200 | [diff] [blame] | 136 | int maxdelay = 1000; |
Felix Fietkau | 0d51ccc | 2011-03-11 21:38:18 +0100 | [diff] [blame] | 137 | int i, q; |
| 138 | |
Felix Fietkau | 8d1bd2a | 2012-04-19 21:18:29 +0200 | [diff] [blame] | 139 | if (ah->curchan) { |
| 140 | if (IS_CHAN_HALF_RATE(ah->curchan)) |
| 141 | maxdelay *= 2; |
| 142 | else if (IS_CHAN_QUARTER_RATE(ah->curchan)) |
| 143 | maxdelay *= 4; |
| 144 | } |
| 145 | |
Felix Fietkau | 0d51ccc | 2011-03-11 21:38:18 +0100 | [diff] [blame] | 146 | REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); |
| 147 | |
| 148 | REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); |
| 149 | REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); |
| 150 | REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); |
| 151 | |
| 152 | for (q = 0; q < AR_NUM_QCU; q++) { |
Felix Fietkau | 8d1bd2a | 2012-04-19 21:18:29 +0200 | [diff] [blame] | 153 | for (i = 0; i < maxdelay; i++) { |
Felix Fietkau | 0d51ccc | 2011-03-11 21:38:18 +0100 | [diff] [blame] | 154 | if (i) |
| 155 | udelay(5); |
| 156 | |
| 157 | if (!ath9k_hw_numtxpending(ah, q)) |
| 158 | break; |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); |
| 163 | REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); |
| 164 | REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); |
| 165 | |
| 166 | REG_WRITE(ah, AR_Q_TXD, 0); |
| 167 | } |
| 168 | EXPORT_SYMBOL(ath9k_hw_abort_tx_dma); |
| 169 | |
Felix Fietkau | efff395 | 2011-03-11 21:38:20 +0100 | [diff] [blame] | 170 | bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 171 | { |
Felix Fietkau | efff395 | 2011-03-11 21:38:20 +0100 | [diff] [blame] | 172 | #define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */ |
Sujith | 94ff91d | 2009-01-27 15:06:38 +0530 | [diff] [blame] | 173 | #define ATH9K_TIME_QUANTUM 100 /* usec */ |
Felix Fietkau | efff395 | 2011-03-11 21:38:20 +0100 | [diff] [blame] | 174 | int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; |
| 175 | int wait; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 176 | |
| 177 | REG_WRITE(ah, AR_Q_TXD, 1 << q); |
| 178 | |
Sujith | 94ff91d | 2009-01-27 15:06:38 +0530 | [diff] [blame] | 179 | for (wait = wait_time; wait != 0; wait--) { |
Felix Fietkau | efff395 | 2011-03-11 21:38:20 +0100 | [diff] [blame] | 180 | if (wait != wait_time) |
| 181 | udelay(ATH9K_TIME_QUANTUM); |
| 182 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 183 | if (ath9k_hw_numtxpending(ah, q) == 0) |
| 184 | break; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | REG_WRITE(ah, AR_Q_TXD, 0); |
Felix Fietkau | efff395 | 2011-03-11 21:38:20 +0100 | [diff] [blame] | 188 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 189 | return wait != 0; |
Sujith | 94ff91d | 2009-01-27 15:06:38 +0530 | [diff] [blame] | 190 | |
| 191 | #undef ATH9K_TX_STOP_DMA_TIMEOUT |
| 192 | #undef ATH9K_TIME_QUANTUM |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 193 | } |
Felix Fietkau | efff395 | 2011-03-11 21:38:20 +0100 | [diff] [blame] | 194 | EXPORT_SYMBOL(ath9k_hw_stop_dma_queue); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 195 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 196 | bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 197 | const struct ath9k_tx_queue_info *qinfo) |
| 198 | { |
| 199 | u32 cw; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 200 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 201 | struct ath9k_tx_queue_info *qi; |
| 202 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 203 | qi = &ah->txq[q]; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 204 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 205 | ath_dbg(common, QUEUE, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 206 | "Set TXQ properties, inactive queue: %u\n", q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 207 | return false; |
| 208 | } |
| 209 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 210 | ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 211 | |
| 212 | qi->tqi_ver = qinfo->tqi_ver; |
| 213 | qi->tqi_subtype = qinfo->tqi_subtype; |
| 214 | qi->tqi_qflags = qinfo->tqi_qflags; |
| 215 | qi->tqi_priority = qinfo->tqi_priority; |
| 216 | if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT) |
| 217 | qi->tqi_aifs = min(qinfo->tqi_aifs, 255U); |
| 218 | else |
| 219 | qi->tqi_aifs = INIT_AIFS; |
| 220 | if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) { |
| 221 | cw = min(qinfo->tqi_cwmin, 1024U); |
| 222 | qi->tqi_cwmin = 1; |
| 223 | while (qi->tqi_cwmin < cw) |
| 224 | qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1; |
| 225 | } else |
| 226 | qi->tqi_cwmin = qinfo->tqi_cwmin; |
| 227 | if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) { |
| 228 | cw = min(qinfo->tqi_cwmax, 1024U); |
| 229 | qi->tqi_cwmax = 1; |
| 230 | while (qi->tqi_cwmax < cw) |
| 231 | qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1; |
| 232 | } else |
| 233 | qi->tqi_cwmax = INIT_CWMAX; |
| 234 | |
| 235 | if (qinfo->tqi_shretry != 0) |
| 236 | qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U); |
| 237 | else |
| 238 | qi->tqi_shretry = INIT_SH_RETRY; |
| 239 | if (qinfo->tqi_lgretry != 0) |
| 240 | qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U); |
| 241 | else |
| 242 | qi->tqi_lgretry = INIT_LG_RETRY; |
| 243 | qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod; |
| 244 | qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit; |
| 245 | qi->tqi_burstTime = qinfo->tqi_burstTime; |
| 246 | qi->tqi_readyTime = qinfo->tqi_readyTime; |
| 247 | |
| 248 | switch (qinfo->tqi_subtype) { |
| 249 | case ATH9K_WME_UPSD: |
| 250 | if (qi->tqi_type == ATH9K_TX_QUEUE_DATA) |
| 251 | qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS; |
| 252 | break; |
| 253 | default: |
| 254 | break; |
| 255 | } |
| 256 | |
| 257 | return true; |
| 258 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 259 | EXPORT_SYMBOL(ath9k_hw_set_txq_props); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 260 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 261 | bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 262 | struct ath9k_tx_queue_info *qinfo) |
| 263 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 264 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 265 | struct ath9k_tx_queue_info *qi; |
| 266 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 267 | qi = &ah->txq[q]; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 268 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 269 | ath_dbg(common, QUEUE, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 270 | "Get TXQ properties, inactive queue: %u\n", q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 271 | return false; |
| 272 | } |
| 273 | |
| 274 | qinfo->tqi_qflags = qi->tqi_qflags; |
| 275 | qinfo->tqi_ver = qi->tqi_ver; |
| 276 | qinfo->tqi_subtype = qi->tqi_subtype; |
| 277 | qinfo->tqi_qflags = qi->tqi_qflags; |
| 278 | qinfo->tqi_priority = qi->tqi_priority; |
| 279 | qinfo->tqi_aifs = qi->tqi_aifs; |
| 280 | qinfo->tqi_cwmin = qi->tqi_cwmin; |
| 281 | qinfo->tqi_cwmax = qi->tqi_cwmax; |
| 282 | qinfo->tqi_shretry = qi->tqi_shretry; |
| 283 | qinfo->tqi_lgretry = qi->tqi_lgretry; |
| 284 | qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod; |
| 285 | qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit; |
| 286 | qinfo->tqi_burstTime = qi->tqi_burstTime; |
| 287 | qinfo->tqi_readyTime = qi->tqi_readyTime; |
| 288 | |
| 289 | return true; |
| 290 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 291 | EXPORT_SYMBOL(ath9k_hw_get_txq_props); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 292 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 293 | int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 294 | const struct ath9k_tx_queue_info *qinfo) |
| 295 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 296 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 297 | struct ath9k_tx_queue_info *qi; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 298 | int q; |
| 299 | |
| 300 | switch (type) { |
| 301 | case ATH9K_TX_QUEUE_BEACON: |
Felix Fietkau | f4c607d | 2011-03-23 20:57:28 +0100 | [diff] [blame] | 302 | q = ATH9K_NUM_TX_QUEUES - 1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 303 | break; |
| 304 | case ATH9K_TX_QUEUE_CAB: |
Felix Fietkau | f4c607d | 2011-03-23 20:57:28 +0100 | [diff] [blame] | 305 | q = ATH9K_NUM_TX_QUEUES - 2; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 306 | break; |
| 307 | case ATH9K_TX_QUEUE_PSPOLL: |
| 308 | q = 1; |
| 309 | break; |
| 310 | case ATH9K_TX_QUEUE_UAPSD: |
Felix Fietkau | f4c607d | 2011-03-23 20:57:28 +0100 | [diff] [blame] | 311 | q = ATH9K_NUM_TX_QUEUES - 3; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 312 | break; |
| 313 | case ATH9K_TX_QUEUE_DATA: |
Felix Fietkau | f4c607d | 2011-03-23 20:57:28 +0100 | [diff] [blame] | 314 | for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 315 | if (ah->txq[q].tqi_type == |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 316 | ATH9K_TX_QUEUE_INACTIVE) |
| 317 | break; |
Felix Fietkau | f4c607d | 2011-03-23 20:57:28 +0100 | [diff] [blame] | 318 | if (q == ATH9K_NUM_TX_QUEUES) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 319 | ath_err(common, "No available TX queue\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 320 | return -1; |
| 321 | } |
| 322 | break; |
| 323 | default: |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 324 | ath_err(common, "Invalid TX queue type: %u\n", type); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 325 | return -1; |
| 326 | } |
| 327 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 328 | ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 329 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 330 | qi = &ah->txq[q]; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 331 | if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 332 | ath_err(common, "TX queue: %u already active\n", q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 333 | return -1; |
| 334 | } |
| 335 | memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); |
| 336 | qi->tqi_type = type; |
Rajkumar Manoharan | 479c689 | 2011-08-13 10:28:12 +0530 | [diff] [blame] | 337 | qi->tqi_physCompBuf = qinfo->tqi_physCompBuf; |
| 338 | (void) ath9k_hw_set_txq_props(ah, q, qinfo); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 339 | |
| 340 | return q; |
| 341 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 342 | EXPORT_SYMBOL(ath9k_hw_setuptxqueue); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 343 | |
Felix Fietkau | 7e03072 | 2012-03-14 16:40:21 +0100 | [diff] [blame] | 344 | static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q) |
| 345 | { |
| 346 | ah->txok_interrupt_mask &= ~(1 << q); |
| 347 | ah->txerr_interrupt_mask &= ~(1 << q); |
| 348 | ah->txdesc_interrupt_mask &= ~(1 << q); |
| 349 | ah->txeol_interrupt_mask &= ~(1 << q); |
| 350 | ah->txurn_interrupt_mask &= ~(1 << q); |
| 351 | } |
| 352 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 353 | bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 354 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 355 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 356 | struct ath9k_tx_queue_info *qi; |
| 357 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 358 | qi = &ah->txq[q]; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 359 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 360 | ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 361 | return false; |
| 362 | } |
| 363 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 364 | ath_dbg(common, QUEUE, "Release TX queue: %u\n", q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 365 | |
| 366 | qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; |
Felix Fietkau | 7e03072 | 2012-03-14 16:40:21 +0100 | [diff] [blame] | 367 | ath9k_hw_clear_queue_interrupts(ah, q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 368 | ath9k_hw_set_txq_interrupts(ah, qi); |
| 369 | |
| 370 | return true; |
| 371 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 372 | EXPORT_SYMBOL(ath9k_hw_releasetxqueue); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 373 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 374 | bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 375 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 376 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 377 | struct ath9k_channel *chan = ah->curchan; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 378 | struct ath9k_tx_queue_info *qi; |
| 379 | u32 cwMin, chanCwMin, value; |
| 380 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 381 | qi = &ah->txq[q]; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 382 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 383 | ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 384 | return true; |
| 385 | } |
| 386 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 387 | ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 388 | |
| 389 | if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { |
| 390 | if (chan && IS_CHAN_B(chan)) |
| 391 | chanCwMin = INIT_CWMIN_11B; |
| 392 | else |
| 393 | chanCwMin = INIT_CWMIN; |
| 394 | |
| 395 | for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1); |
| 396 | } else |
| 397 | cwMin = qi->tqi_cwmin; |
| 398 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 399 | ENABLE_REGWRITE_BUFFER(ah); |
| 400 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 401 | REG_WRITE(ah, AR_DLCL_IFS(q), |
| 402 | SM(cwMin, AR_D_LCL_IFS_CWMIN) | |
| 403 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | |
| 404 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); |
| 405 | |
| 406 | REG_WRITE(ah, AR_DRETRY_LIMIT(q), |
| 407 | SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | |
| 408 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | |
| 409 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); |
| 410 | |
| 411 | REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); |
Rajkumar Manoharan | 94333f5 | 2011-05-09 19:11:27 +0530 | [diff] [blame] | 412 | |
Felix Fietkau | 86c157b | 2013-05-23 12:20:56 +0200 | [diff] [blame] | 413 | if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah)) |
Rajkumar Manoharan | 94333f5 | 2011-05-09 19:11:27 +0530 | [diff] [blame] | 414 | REG_WRITE(ah, AR_DMISC(q), |
| 415 | AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1); |
| 416 | else |
| 417 | REG_WRITE(ah, AR_DMISC(q), |
| 418 | AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 419 | |
| 420 | if (qi->tqi_cbrPeriod) { |
| 421 | REG_WRITE(ah, AR_QCBRCFG(q), |
| 422 | SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | |
| 423 | SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH)); |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 424 | REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | |
| 425 | (qi->tqi_cbrOverflowLimit ? |
| 426 | AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 427 | } |
| 428 | if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) { |
| 429 | REG_WRITE(ah, AR_QRDYTIMECFG(q), |
| 430 | SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | |
| 431 | AR_Q_RDYTIMECFG_EN); |
| 432 | } |
| 433 | |
| 434 | REG_WRITE(ah, AR_DCHNTIME(q), |
| 435 | SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | |
| 436 | (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); |
| 437 | |
| 438 | if (qi->tqi_burstTime |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 439 | && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) |
| 440 | REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 441 | |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 442 | if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) |
| 443 | REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 444 | |
| 445 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 446 | |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 447 | if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) |
| 448 | REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); |
| 449 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 450 | switch (qi->tqi_type) { |
| 451 | case ATH9K_TX_QUEUE_BEACON: |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 452 | ENABLE_REGWRITE_BUFFER(ah); |
| 453 | |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 454 | REG_SET_BIT(ah, AR_QMISC(q), |
| 455 | AR_Q_MISC_FSP_DBA_GATED |
| 456 | | AR_Q_MISC_BEACON_USE |
| 457 | | AR_Q_MISC_CBR_INCR_DIS1); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 458 | |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 459 | REG_SET_BIT(ah, AR_DMISC(q), |
| 460 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 461 | AR_D_MISC_ARB_LOCKOUT_CNTRL_S) |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 462 | | AR_D_MISC_BEACON_USE |
| 463 | | AR_D_MISC_POST_FR_BKOFF_DIS); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 464 | |
| 465 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 466 | |
Luis R. Rodriguez | 9a2af88 | 2010-06-14 20:17:36 -0400 | [diff] [blame] | 467 | /* |
| 468 | * cwmin and cwmax should be 0 for beacon queue |
| 469 | * but not for IBSS as we would create an imbalance |
| 470 | * on beaconing fairness for participating nodes. |
| 471 | */ |
| 472 | if (AR_SREV_9300_20_OR_LATER(ah) && |
| 473 | ah->opmode != NL80211_IFTYPE_ADHOC) { |
Luis R. Rodriguez | 3deb4da | 2010-04-15 17:39:32 -0400 | [diff] [blame] | 474 | REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) |
| 475 | | SM(0, AR_D_LCL_IFS_CWMAX) |
| 476 | | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); |
| 477 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 478 | break; |
| 479 | case ATH9K_TX_QUEUE_CAB: |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 480 | ENABLE_REGWRITE_BUFFER(ah); |
| 481 | |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 482 | REG_SET_BIT(ah, AR_QMISC(q), |
| 483 | AR_Q_MISC_FSP_DBA_GATED |
| 484 | | AR_Q_MISC_CBR_INCR_DIS1 |
| 485 | | AR_Q_MISC_CBR_INCR_DIS0); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 486 | value = (qi->tqi_readyTime - |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 487 | (ah->config.sw_beacon_response_time - |
| 488 | ah->config.dma_beacon_response_time) - |
| 489 | ah->config.additional_swba_backoff) * 1024; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 490 | REG_WRITE(ah, AR_QRDYTIMECFG(q), |
| 491 | value | AR_Q_RDYTIMECFG_EN); |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 492 | REG_SET_BIT(ah, AR_DMISC(q), |
| 493 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 494 | AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 495 | |
| 496 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 497 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 498 | break; |
| 499 | case ATH9K_TX_QUEUE_PSPOLL: |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 500 | REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 501 | break; |
| 502 | case ATH9K_TX_QUEUE_UAPSD: |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 503 | REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 504 | break; |
| 505 | default: |
| 506 | break; |
| 507 | } |
| 508 | |
| 509 | if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) { |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 510 | REG_SET_BIT(ah, AR_DMISC(q), |
| 511 | SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, |
| 512 | AR_D_MISC_ARB_LOCKOUT_CNTRL) | |
| 513 | AR_D_MISC_POST_FR_BKOFF_DIS); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 514 | } |
| 515 | |
Luis R. Rodriguez | 79de237 | 2010-04-15 17:39:31 -0400 | [diff] [blame] | 516 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 517 | REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); |
| 518 | |
Felix Fietkau | 7e03072 | 2012-03-14 16:40:21 +0100 | [diff] [blame] | 519 | ath9k_hw_clear_queue_interrupts(ah, q); |
Felix Fietkau | ce8fdf6 | 2012-03-14 16:40:22 +0100 | [diff] [blame] | 520 | if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 521 | ah->txok_interrupt_mask |= 1 << q; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 522 | ah->txerr_interrupt_mask |= 1 << q; |
Felix Fietkau | ce8fdf6 | 2012-03-14 16:40:22 +0100 | [diff] [blame] | 523 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 524 | if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 525 | ah->txdesc_interrupt_mask |= 1 << q; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 526 | if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 527 | ah->txeol_interrupt_mask |= 1 << q; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 528 | if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 529 | ah->txurn_interrupt_mask |= 1 << q; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 530 | ath9k_hw_set_txq_interrupts(ah, qi); |
| 531 | |
| 532 | return true; |
| 533 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 534 | EXPORT_SYMBOL(ath9k_hw_resettxqueue); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 535 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 536 | int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, |
Rajkumar Manoharan | 3de2111 | 2011-08-13 10:28:11 +0530 | [diff] [blame] | 537 | struct ath_rx_status *rs) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 538 | { |
| 539 | struct ar5416_desc ads; |
| 540 | struct ar5416_desc *adsp = AR5416DESC(ds); |
| 541 | u32 phyerr; |
| 542 | |
| 543 | if ((adsp->ds_rxstatus8 & AR_RxDone) == 0) |
| 544 | return -EINPROGRESS; |
| 545 | |
| 546 | ads.u.rx = adsp->u.rx; |
| 547 | |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 548 | rs->rs_status = 0; |
| 549 | rs->rs_flags = 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 550 | |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 551 | rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen; |
| 552 | rs->rs_tstamp = ads.AR_RcvTimestamp; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 553 | |
Senthil Balasubramanian | dd8b15b | 2009-07-14 20:17:08 -0400 | [diff] [blame] | 554 | if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) { |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 555 | rs->rs_rssi = ATH9K_RSSI_BAD; |
| 556 | rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD; |
| 557 | rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD; |
| 558 | rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD; |
| 559 | rs->rs_rssi_ext0 = ATH9K_RSSI_BAD; |
| 560 | rs->rs_rssi_ext1 = ATH9K_RSSI_BAD; |
| 561 | rs->rs_rssi_ext2 = ATH9K_RSSI_BAD; |
Senthil Balasubramanian | dd8b15b | 2009-07-14 20:17:08 -0400 | [diff] [blame] | 562 | } else { |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 563 | rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); |
| 564 | rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, |
Senthil Balasubramanian | dd8b15b | 2009-07-14 20:17:08 -0400 | [diff] [blame] | 565 | AR_RxRSSIAnt00); |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 566 | rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, |
Senthil Balasubramanian | dd8b15b | 2009-07-14 20:17:08 -0400 | [diff] [blame] | 567 | AR_RxRSSIAnt01); |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 568 | rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, |
Senthil Balasubramanian | dd8b15b | 2009-07-14 20:17:08 -0400 | [diff] [blame] | 569 | AR_RxRSSIAnt02); |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 570 | rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4, |
Senthil Balasubramanian | dd8b15b | 2009-07-14 20:17:08 -0400 | [diff] [blame] | 571 | AR_RxRSSIAnt10); |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 572 | rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4, |
Senthil Balasubramanian | dd8b15b | 2009-07-14 20:17:08 -0400 | [diff] [blame] | 573 | AR_RxRSSIAnt11); |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 574 | rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4, |
Senthil Balasubramanian | dd8b15b | 2009-07-14 20:17:08 -0400 | [diff] [blame] | 575 | AR_RxRSSIAnt12); |
| 576 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 577 | if (ads.ds_rxstatus8 & AR_RxKeyIdxValid) |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 578 | rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 579 | else |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 580 | rs->rs_keyix = ATH9K_RXKEYIX_INVALID; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 581 | |
Felix Fietkau | 1b8714f | 2011-09-15 14:25:35 +0200 | [diff] [blame] | 582 | rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate); |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 583 | rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 584 | |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 585 | rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0; |
| 586 | rs->rs_moreaggr = |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 587 | (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 588 | rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna); |
| 589 | rs->rs_flags = |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 590 | (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0; |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 591 | rs->rs_flags |= |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 592 | (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0; |
| 593 | |
| 594 | if (ads.ds_rxstatus8 & AR_PreDelimCRCErr) |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 595 | rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 596 | if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 597 | rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 598 | if (ads.ds_rxstatus8 & AR_DecryptBusyErr) |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 599 | rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 600 | |
| 601 | if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) { |
Felix Fietkau | 115dad7 | 2011-01-14 00:06:27 +0100 | [diff] [blame] | 602 | /* |
| 603 | * Treat these errors as mutually exclusive to avoid spurious |
| 604 | * extra error reports from the hardware. If a CRC error is |
| 605 | * reported, then decryption and MIC errors are irrelevant, |
| 606 | * the frame is going to be dropped either way |
| 607 | */ |
Simon Wunderlich | 3a32556 | 2013-01-23 17:38:06 +0100 | [diff] [blame] | 608 | if (ads.ds_rxstatus8 & AR_PHYErr) { |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 609 | rs->rs_status |= ATH9K_RXERR_PHY; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 610 | phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode); |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 611 | rs->rs_phyerr = phyerr; |
Simon Wunderlich | 3a32556 | 2013-01-23 17:38:06 +0100 | [diff] [blame] | 612 | } else if (ads.ds_rxstatus8 & AR_CRCErr) |
| 613 | rs->rs_status |= ATH9K_RXERR_CRC; |
| 614 | else if (ads.ds_rxstatus8 & AR_DecryptCRCErr) |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 615 | rs->rs_status |= ATH9K_RXERR_DECRYPT; |
Felix Fietkau | 115dad7 | 2011-01-14 00:06:27 +0100 | [diff] [blame] | 616 | else if (ads.ds_rxstatus8 & AR_MichaelErr) |
Felix Fietkau | 8e6f5aa | 2010-03-29 20:09:27 -0700 | [diff] [blame] | 617 | rs->rs_status |= ATH9K_RXERR_MIC; |
Felix Fietkau | 3747c3e | 2013-04-08 00:04:12 +0200 | [diff] [blame] | 618 | } else { |
| 619 | if (ads.ds_rxstatus8 & |
| 620 | (AR_CRCErr | AR_PHYErr | AR_DecryptCRCErr | AR_MichaelErr)) |
| 621 | rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC; |
| 622 | |
| 623 | /* Only up to MCS16 supported, everything above is invalid */ |
| 624 | if (rs->rs_rate >= 0x90) |
| 625 | rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 626 | } |
| 627 | |
Felix Fietkau | 7a532fe | 2012-01-14 15:08:34 +0100 | [diff] [blame] | 628 | if (ads.ds_rxstatus8 & AR_KeyMiss) |
| 629 | rs->rs_status |= ATH9K_RXERR_KEYMISS; |
| 630 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 631 | return 0; |
| 632 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 633 | EXPORT_SYMBOL(ath9k_hw_rxprocdesc); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 634 | |
Luis R. Rodriguez | e7824a5 | 2009-11-24 02:53:25 -0500 | [diff] [blame] | 635 | /* |
| 636 | * This can stop or re-enables RX. |
| 637 | * |
| 638 | * If bool is set this will kill any frame which is currently being |
| 639 | * transferred between the MAC and baseband and also prevent any new |
| 640 | * frames from getting started. |
| 641 | */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 642 | bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 643 | { |
| 644 | u32 reg; |
| 645 | |
| 646 | if (set) { |
| 647 | REG_SET_BIT(ah, AR_DIAG_SW, |
| 648 | (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); |
| 649 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 650 | if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, |
| 651 | 0, AH_WAIT_TIMEOUT)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 652 | REG_CLR_BIT(ah, AR_DIAG_SW, |
| 653 | (AR_DIAG_RX_DIS | |
| 654 | AR_DIAG_RX_ABORT)); |
| 655 | |
| 656 | reg = REG_READ(ah, AR_OBS_BUS_1); |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 657 | ath_err(ath9k_hw_common(ah), |
| 658 | "RX failed to go idle in 10 ms RXSM=0x%x\n", |
| 659 | reg); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 660 | |
| 661 | return false; |
| 662 | } |
| 663 | } else { |
| 664 | REG_CLR_BIT(ah, AR_DIAG_SW, |
| 665 | (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); |
| 666 | } |
| 667 | |
| 668 | return true; |
| 669 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 670 | EXPORT_SYMBOL(ath9k_hw_setrxabort); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 671 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 672 | void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 673 | { |
| 674 | REG_WRITE(ah, AR_RXDP, rxdp); |
| 675 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 676 | EXPORT_SYMBOL(ath9k_hw_putrxbuf); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 677 | |
Luis R. Rodriguez | 40346b6 | 2010-06-12 00:33:44 -0400 | [diff] [blame] | 678 | void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 679 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 680 | ath9k_enable_mib_counters(ah); |
| 681 | |
Luis R. Rodriguez | 40346b6 | 2010-06-12 00:33:44 -0400 | [diff] [blame] | 682 | ath9k_ani_reset(ah, is_scanning); |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 683 | |
Senthil Balasubramanian | 8aa15e1 | 2008-12-08 19:43:50 +0530 | [diff] [blame] | 684 | REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 685 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 686 | EXPORT_SYMBOL(ath9k_hw_startpcureceive); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 687 | |
Vasanthakumar Thiagarajan | 9b9cc61 | 2010-04-15 17:39:41 -0400 | [diff] [blame] | 688 | void ath9k_hw_abortpcurecv(struct ath_hw *ah) |
| 689 | { |
| 690 | REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS); |
| 691 | |
| 692 | ath9k_hw_disable_mib_counters(ah); |
| 693 | } |
| 694 | EXPORT_SYMBOL(ath9k_hw_abortpcurecv); |
| 695 | |
Felix Fietkau | 5882da02 | 2011-04-08 20:13:18 +0200 | [diff] [blame] | 696 | bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 697 | { |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 698 | #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 699 | struct ath_common *common = ath9k_hw_common(ah); |
Felix Fietkau | 5882da02 | 2011-04-08 20:13:18 +0200 | [diff] [blame] | 700 | u32 mac_status, last_mac_status = 0; |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 701 | int i; |
| 702 | |
Felix Fietkau | 5882da02 | 2011-04-08 20:13:18 +0200 | [diff] [blame] | 703 | /* Enable access to the DMA observation bus */ |
| 704 | REG_WRITE(ah, AR_MACMISC, |
| 705 | ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | |
| 706 | (AR_MACMISC_MISC_OBS_BUS_1 << |
| 707 | AR_MACMISC_MISC_OBS_BUS_MSB_S))); |
| 708 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 709 | REG_WRITE(ah, AR_CR, AR_CR_RXD); |
| 710 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 711 | /* Wait for rx enable bit to go low */ |
| 712 | for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) { |
| 713 | if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) |
| 714 | break; |
Felix Fietkau | 5882da02 | 2011-04-08 20:13:18 +0200 | [diff] [blame] | 715 | |
| 716 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
| 717 | mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; |
| 718 | if (mac_status == 0x1c0 && mac_status == last_mac_status) { |
| 719 | *reset = true; |
| 720 | break; |
| 721 | } |
| 722 | |
| 723 | last_mac_status = mac_status; |
| 724 | } |
| 725 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 726 | udelay(AH_TIME_QUANTUM); |
| 727 | } |
| 728 | |
| 729 | if (i == 0) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 730 | ath_err(common, |
Felix Fietkau | 5882da02 | 2011-04-08 20:13:18 +0200 | [diff] [blame] | 731 | "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n", |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 732 | AH_RX_STOP_DMA_TIMEOUT / 1000, |
| 733 | REG_READ(ah, AR_CR), |
Felix Fietkau | 5882da02 | 2011-04-08 20:13:18 +0200 | [diff] [blame] | 734 | REG_READ(ah, AR_DIAG_SW), |
| 735 | REG_READ(ah, AR_DMADBG_7)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 736 | return false; |
| 737 | } else { |
| 738 | return true; |
| 739 | } |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 740 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 741 | #undef AH_RX_STOP_DMA_TIMEOUT |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 742 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 743 | EXPORT_SYMBOL(ath9k_hw_stopdmarecv); |
Luis R. Rodriguez | 536b3a7 | 2009-10-06 21:19:11 -0400 | [diff] [blame] | 744 | |
| 745 | int ath9k_hw_beaconq_setup(struct ath_hw *ah) |
| 746 | { |
| 747 | struct ath9k_tx_queue_info qi; |
| 748 | |
| 749 | memset(&qi, 0, sizeof(qi)); |
| 750 | qi.tqi_aifs = 1; |
| 751 | qi.tqi_cwmin = 0; |
| 752 | qi.tqi_cwmax = 0; |
Felix Fietkau | 627e67a | 2012-02-27 19:58:41 +0100 | [diff] [blame] | 753 | |
| 754 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
Felix Fietkau | ce8fdf6 | 2012-03-14 16:40:22 +0100 | [diff] [blame] | 755 | qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; |
Felix Fietkau | 627e67a | 2012-02-27 19:58:41 +0100 | [diff] [blame] | 756 | |
Luis R. Rodriguez | 536b3a7 | 2009-10-06 21:19:11 -0400 | [diff] [blame] | 757 | return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); |
| 758 | } |
| 759 | EXPORT_SYMBOL(ath9k_hw_beaconq_setup); |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 760 | |
| 761 | bool ath9k_hw_intrpend(struct ath_hw *ah) |
| 762 | { |
| 763 | u32 host_isr; |
| 764 | |
| 765 | if (AR_SREV_9100(ah)) |
| 766 | return true; |
| 767 | |
| 768 | host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); |
Mohammed Shafi Shajakhan | e358481 | 2011-11-30 10:41:20 +0530 | [diff] [blame] | 769 | |
| 770 | if (((host_isr & AR_INTR_MAC_IRQ) || |
| 771 | (host_isr & AR_INTR_ASYNC_MASK_MCI)) && |
| 772 | (host_isr != AR_INTR_SPURIOUS)) |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 773 | return true; |
| 774 | |
| 775 | host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); |
| 776 | if ((host_isr & AR_INTR_SYNC_DEFAULT) |
| 777 | && (host_isr != AR_INTR_SPURIOUS)) |
| 778 | return true; |
| 779 | |
| 780 | return false; |
| 781 | } |
| 782 | EXPORT_SYMBOL(ath9k_hw_intrpend); |
| 783 | |
Felix Fietkau | f41a9b3 | 2012-08-08 16:25:03 +0200 | [diff] [blame] | 784 | void ath9k_hw_kill_interrupts(struct ath_hw *ah) |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 785 | { |
| 786 | struct ath_common *common = ath9k_hw_common(ah); |
| 787 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 788 | ath_dbg(common, INTERRUPT, "disable IER\n"); |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 789 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); |
| 790 | (void) REG_READ(ah, AR_IER); |
| 791 | if (!AR_SREV_9100(ah)) { |
| 792 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); |
| 793 | (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); |
| 794 | |
| 795 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
| 796 | (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); |
| 797 | } |
| 798 | } |
Felix Fietkau | f41a9b3 | 2012-08-08 16:25:03 +0200 | [diff] [blame] | 799 | EXPORT_SYMBOL(ath9k_hw_kill_interrupts); |
| 800 | |
| 801 | void ath9k_hw_disable_interrupts(struct ath_hw *ah) |
| 802 | { |
| 803 | if (!(ah->imask & ATH9K_INT_GLOBAL)) |
| 804 | atomic_set(&ah->intr_ref_cnt, -1); |
| 805 | else |
| 806 | atomic_dec(&ah->intr_ref_cnt); |
| 807 | |
| 808 | ath9k_hw_kill_interrupts(ah); |
| 809 | } |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 810 | EXPORT_SYMBOL(ath9k_hw_disable_interrupts); |
| 811 | |
| 812 | void ath9k_hw_enable_interrupts(struct ath_hw *ah) |
| 813 | { |
| 814 | struct ath_common *common = ath9k_hw_common(ah); |
Vasanthakumar Thiagarajan | 79d1d2b | 2011-04-19 19:29:19 +0530 | [diff] [blame] | 815 | u32 sync_default = AR_INTR_SYNC_DEFAULT; |
Mohammed Shafi Shajakhan | f229f815 | 2011-11-30 10:41:19 +0530 | [diff] [blame] | 816 | u32 async_mask; |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 817 | |
| 818 | if (!(ah->imask & ATH9K_INT_GLOBAL)) |
| 819 | return; |
| 820 | |
Rajkumar Manoharan | e8fe733 | 2011-08-05 18:59:41 +0530 | [diff] [blame] | 821 | if (!atomic_inc_and_test(&ah->intr_ref_cnt)) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 822 | ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n", |
Rajkumar Manoharan | e8fe733 | 2011-08-05 18:59:41 +0530 | [diff] [blame] | 823 | atomic_read(&ah->intr_ref_cnt)); |
| 824 | return; |
| 825 | } |
| 826 | |
Gabor Juhos | 3b8a057 | 2012-07-03 19:13:29 +0200 | [diff] [blame] | 827 | if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) |
Vasanthakumar Thiagarajan | 79d1d2b | 2011-04-19 19:29:19 +0530 | [diff] [blame] | 828 | sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; |
| 829 | |
Mohammed Shafi Shajakhan | f229f815 | 2011-11-30 10:41:19 +0530 | [diff] [blame] | 830 | async_mask = AR_INTR_MAC_IRQ; |
| 831 | |
| 832 | if (ah->imask & ATH9K_INT_MCI) |
| 833 | async_mask |= AR_INTR_ASYNC_MASK_MCI; |
| 834 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 835 | ath_dbg(common, INTERRUPT, "enable IER\n"); |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 836 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
| 837 | if (!AR_SREV_9100(ah)) { |
Mohammed Shafi Shajakhan | f229f815 | 2011-11-30 10:41:19 +0530 | [diff] [blame] | 838 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask); |
| 839 | REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask); |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 840 | |
Vasanthakumar Thiagarajan | 79d1d2b | 2011-04-19 19:29:19 +0530 | [diff] [blame] | 841 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); |
| 842 | REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default); |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 843 | } |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 844 | ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 845 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 846 | } |
| 847 | EXPORT_SYMBOL(ath9k_hw_enable_interrupts); |
| 848 | |
Felix Fietkau | 72d874c | 2011-10-08 20:06:19 +0200 | [diff] [blame] | 849 | void ath9k_hw_set_interrupts(struct ath_hw *ah) |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 850 | { |
Felix Fietkau | 72d874c | 2011-10-08 20:06:19 +0200 | [diff] [blame] | 851 | enum ath9k_int ints = ah->imask; |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 852 | u32 mask, mask2; |
| 853 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
| 854 | struct ath_common *common = ath9k_hw_common(ah); |
| 855 | |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 856 | if (!(ints & ATH9K_INT_GLOBAL)) |
Stanislaw Gruszka | 385918c | 2011-02-21 15:02:41 +0100 | [diff] [blame] | 857 | ath9k_hw_disable_interrupts(ah); |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 858 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 859 | ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints); |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 860 | |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 861 | mask = ints & ATH9K_INT_COMMON; |
| 862 | mask2 = 0; |
| 863 | |
| 864 | if (ints & ATH9K_INT_TX) { |
| 865 | if (ah->config.tx_intr_mitigation) |
| 866 | mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM; |
Luis R. Rodriguez | 5bea400 | 2010-04-26 15:04:41 -0400 | [diff] [blame] | 867 | else { |
| 868 | if (ah->txok_interrupt_mask) |
| 869 | mask |= AR_IMR_TXOK; |
| 870 | if (ah->txdesc_interrupt_mask) |
| 871 | mask |= AR_IMR_TXDESC; |
| 872 | } |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 873 | if (ah->txerr_interrupt_mask) |
| 874 | mask |= AR_IMR_TXERR; |
| 875 | if (ah->txeol_interrupt_mask) |
| 876 | mask |= AR_IMR_TXEOL; |
| 877 | } |
| 878 | if (ints & ATH9K_INT_RX) { |
| 879 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 880 | mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP; |
| 881 | if (ah->config.rx_intr_mitigation) { |
| 882 | mask &= ~AR_IMR_RXOK_LP; |
| 883 | mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; |
| 884 | } else { |
| 885 | mask |= AR_IMR_RXOK_LP; |
| 886 | } |
| 887 | } else { |
| 888 | if (ah->config.rx_intr_mitigation) |
| 889 | mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; |
| 890 | else |
| 891 | mask |= AR_IMR_RXOK | AR_IMR_RXDESC; |
| 892 | } |
| 893 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
| 894 | mask |= AR_IMR_GENTMR; |
| 895 | } |
| 896 | |
Vivek Natarajan | f78eb65 | 2011-04-26 10:39:54 +0530 | [diff] [blame] | 897 | if (ints & ATH9K_INT_GENTIMER) |
| 898 | mask |= AR_IMR_GENTMR; |
| 899 | |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 900 | if (ints & (ATH9K_INT_BMISC)) { |
| 901 | mask |= AR_IMR_BCNMISC; |
| 902 | if (ints & ATH9K_INT_TIM) |
| 903 | mask2 |= AR_IMR_S2_TIM; |
| 904 | if (ints & ATH9K_INT_DTIM) |
| 905 | mask2 |= AR_IMR_S2_DTIM; |
| 906 | if (ints & ATH9K_INT_DTIMSYNC) |
| 907 | mask2 |= AR_IMR_S2_DTIMSYNC; |
| 908 | if (ints & ATH9K_INT_CABEND) |
| 909 | mask2 |= AR_IMR_S2_CABEND; |
| 910 | if (ints & ATH9K_INT_TSFOOR) |
| 911 | mask2 |= AR_IMR_S2_TSFOOR; |
| 912 | } |
| 913 | |
| 914 | if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { |
| 915 | mask |= AR_IMR_BCNMISC; |
| 916 | if (ints & ATH9K_INT_GTT) |
| 917 | mask2 |= AR_IMR_S2_GTT; |
| 918 | if (ints & ATH9K_INT_CST) |
| 919 | mask2 |= AR_IMR_S2_CST; |
| 920 | } |
| 921 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 922 | ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask); |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 923 | REG_WRITE(ah, AR_IMR, mask); |
| 924 | ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | |
| 925 | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | |
| 926 | AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); |
| 927 | ah->imrs2_reg |= mask2; |
| 928 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); |
| 929 | |
| 930 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
| 931 | if (ints & ATH9K_INT_TIM_TIMER) |
| 932 | REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); |
| 933 | else |
| 934 | REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); |
| 935 | } |
| 936 | |
Felix Fietkau | 4df3071 | 2010-11-08 20:54:47 +0100 | [diff] [blame] | 937 | return; |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 938 | } |
| 939 | EXPORT_SYMBOL(ath9k_hw_set_interrupts); |