Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 1 | /* |
| 2 | * arch/powerpc/sysdev/qe_lib/qe_ic.c |
| 3 | * |
Yang Li | 8a56e1e | 2012-11-01 18:53:42 +0000 | [diff] [blame] | 4 | * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 5 | * |
| 6 | * Author: Li Yang <leoli@freescale.com> |
| 7 | * Based on code from Shlomi Gridish <gridish@freescale.com> |
| 8 | * |
| 9 | * QUICC ENGINE Interrupt Controller |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the |
| 13 | * Free Software Foundation; either version 2 of the License, or (at your |
| 14 | * option) any later version. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/errno.h> |
| 20 | #include <linux/reboot.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/stddef.h> |
| 23 | #include <linux/sched.h> |
| 24 | #include <linux/signal.h> |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 25 | #include <linux/device.h> |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 26 | #include <linux/spinlock.h> |
| 27 | #include <asm/irq.h> |
| 28 | #include <asm/io.h> |
| 29 | #include <asm/prom.h> |
| 30 | #include <asm/qe_ic.h> |
| 31 | |
| 32 | #include "qe_ic.h" |
| 33 | |
Anton Vorontsov | 43a5a01 | 2010-02-18 16:43:12 +0300 | [diff] [blame] | 34 | static DEFINE_RAW_SPINLOCK(qe_ic_lock); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 35 | |
| 36 | static struct qe_ic_info qe_ic_info[] = { |
| 37 | [1] = { |
| 38 | .mask = 0x00008000, |
| 39 | .mask_reg = QEIC_CIMR, |
| 40 | .pri_code = 0, |
| 41 | .pri_reg = QEIC_CIPWCC, |
| 42 | }, |
| 43 | [2] = { |
| 44 | .mask = 0x00004000, |
| 45 | .mask_reg = QEIC_CIMR, |
| 46 | .pri_code = 1, |
| 47 | .pri_reg = QEIC_CIPWCC, |
| 48 | }, |
| 49 | [3] = { |
| 50 | .mask = 0x00002000, |
| 51 | .mask_reg = QEIC_CIMR, |
| 52 | .pri_code = 2, |
| 53 | .pri_reg = QEIC_CIPWCC, |
| 54 | }, |
| 55 | [10] = { |
| 56 | .mask = 0x00000040, |
| 57 | .mask_reg = QEIC_CIMR, |
| 58 | .pri_code = 1, |
| 59 | .pri_reg = QEIC_CIPZCC, |
| 60 | }, |
| 61 | [11] = { |
| 62 | .mask = 0x00000020, |
| 63 | .mask_reg = QEIC_CIMR, |
| 64 | .pri_code = 2, |
| 65 | .pri_reg = QEIC_CIPZCC, |
| 66 | }, |
| 67 | [12] = { |
| 68 | .mask = 0x00000010, |
| 69 | .mask_reg = QEIC_CIMR, |
| 70 | .pri_code = 3, |
| 71 | .pri_reg = QEIC_CIPZCC, |
| 72 | }, |
| 73 | [13] = { |
| 74 | .mask = 0x00000008, |
| 75 | .mask_reg = QEIC_CIMR, |
| 76 | .pri_code = 4, |
| 77 | .pri_reg = QEIC_CIPZCC, |
| 78 | }, |
| 79 | [14] = { |
| 80 | .mask = 0x00000004, |
| 81 | .mask_reg = QEIC_CIMR, |
| 82 | .pri_code = 5, |
| 83 | .pri_reg = QEIC_CIPZCC, |
| 84 | }, |
| 85 | [15] = { |
| 86 | .mask = 0x00000002, |
| 87 | .mask_reg = QEIC_CIMR, |
| 88 | .pri_code = 6, |
| 89 | .pri_reg = QEIC_CIPZCC, |
| 90 | }, |
| 91 | [20] = { |
| 92 | .mask = 0x10000000, |
| 93 | .mask_reg = QEIC_CRIMR, |
| 94 | .pri_code = 3, |
| 95 | .pri_reg = QEIC_CIPRTA, |
| 96 | }, |
| 97 | [25] = { |
| 98 | .mask = 0x00800000, |
| 99 | .mask_reg = QEIC_CRIMR, |
| 100 | .pri_code = 0, |
| 101 | .pri_reg = QEIC_CIPRTB, |
| 102 | }, |
| 103 | [26] = { |
| 104 | .mask = 0x00400000, |
| 105 | .mask_reg = QEIC_CRIMR, |
| 106 | .pri_code = 1, |
| 107 | .pri_reg = QEIC_CIPRTB, |
| 108 | }, |
| 109 | [27] = { |
| 110 | .mask = 0x00200000, |
| 111 | .mask_reg = QEIC_CRIMR, |
| 112 | .pri_code = 2, |
| 113 | .pri_reg = QEIC_CIPRTB, |
| 114 | }, |
| 115 | [28] = { |
| 116 | .mask = 0x00100000, |
| 117 | .mask_reg = QEIC_CRIMR, |
| 118 | .pri_code = 3, |
| 119 | .pri_reg = QEIC_CIPRTB, |
| 120 | }, |
| 121 | [32] = { |
| 122 | .mask = 0x80000000, |
| 123 | .mask_reg = QEIC_CIMR, |
| 124 | .pri_code = 0, |
| 125 | .pri_reg = QEIC_CIPXCC, |
| 126 | }, |
| 127 | [33] = { |
| 128 | .mask = 0x40000000, |
| 129 | .mask_reg = QEIC_CIMR, |
| 130 | .pri_code = 1, |
| 131 | .pri_reg = QEIC_CIPXCC, |
| 132 | }, |
| 133 | [34] = { |
| 134 | .mask = 0x20000000, |
| 135 | .mask_reg = QEIC_CIMR, |
| 136 | .pri_code = 2, |
| 137 | .pri_reg = QEIC_CIPXCC, |
| 138 | }, |
| 139 | [35] = { |
| 140 | .mask = 0x10000000, |
| 141 | .mask_reg = QEIC_CIMR, |
| 142 | .pri_code = 3, |
| 143 | .pri_reg = QEIC_CIPXCC, |
| 144 | }, |
| 145 | [36] = { |
| 146 | .mask = 0x08000000, |
| 147 | .mask_reg = QEIC_CIMR, |
| 148 | .pri_code = 4, |
| 149 | .pri_reg = QEIC_CIPXCC, |
| 150 | }, |
| 151 | [40] = { |
| 152 | .mask = 0x00800000, |
| 153 | .mask_reg = QEIC_CIMR, |
| 154 | .pri_code = 0, |
| 155 | .pri_reg = QEIC_CIPYCC, |
| 156 | }, |
| 157 | [41] = { |
| 158 | .mask = 0x00400000, |
| 159 | .mask_reg = QEIC_CIMR, |
| 160 | .pri_code = 1, |
| 161 | .pri_reg = QEIC_CIPYCC, |
| 162 | }, |
| 163 | [42] = { |
| 164 | .mask = 0x00200000, |
| 165 | .mask_reg = QEIC_CIMR, |
| 166 | .pri_code = 2, |
| 167 | .pri_reg = QEIC_CIPYCC, |
| 168 | }, |
| 169 | [43] = { |
| 170 | .mask = 0x00100000, |
| 171 | .mask_reg = QEIC_CIMR, |
| 172 | .pri_code = 3, |
| 173 | .pri_reg = QEIC_CIPYCC, |
| 174 | }, |
| 175 | }; |
| 176 | |
| 177 | static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg) |
| 178 | { |
| 179 | return in_be32(base + (reg >> 2)); |
| 180 | } |
| 181 | |
| 182 | static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg, |
| 183 | u32 value) |
| 184 | { |
| 185 | out_be32(base + (reg >> 2), value); |
| 186 | } |
| 187 | |
| 188 | static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) |
| 189 | { |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 190 | return irq_get_chip_data(virq); |
Lennert Buytenhek | 3a0adfa | 2011-03-08 22:27:00 +0000 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) |
| 194 | { |
| 195 | return irq_data_get_irq_chip_data(d); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 196 | } |
| 197 | |
Lennert Buytenhek | 3a0adfa | 2011-03-08 22:27:00 +0000 | [diff] [blame] | 198 | static void qe_ic_unmask_irq(struct irq_data *d) |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 199 | { |
Lennert Buytenhek | 3a0adfa | 2011-03-08 22:27:00 +0000 | [diff] [blame] | 200 | struct qe_ic *qe_ic = qe_ic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 201 | unsigned int src = irqd_to_hwirq(d); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 202 | unsigned long flags; |
| 203 | u32 temp; |
| 204 | |
Anton Vorontsov | 43a5a01 | 2010-02-18 16:43:12 +0300 | [diff] [blame] | 205 | raw_spin_lock_irqsave(&qe_ic_lock, flags); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 206 | |
| 207 | temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); |
| 208 | qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, |
| 209 | temp | qe_ic_info[src].mask); |
| 210 | |
Anton Vorontsov | 43a5a01 | 2010-02-18 16:43:12 +0300 | [diff] [blame] | 211 | raw_spin_unlock_irqrestore(&qe_ic_lock, flags); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 212 | } |
| 213 | |
Lennert Buytenhek | 3a0adfa | 2011-03-08 22:27:00 +0000 | [diff] [blame] | 214 | static void qe_ic_mask_irq(struct irq_data *d) |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 215 | { |
Lennert Buytenhek | 3a0adfa | 2011-03-08 22:27:00 +0000 | [diff] [blame] | 216 | struct qe_ic *qe_ic = qe_ic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 217 | unsigned int src = irqd_to_hwirq(d); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 218 | unsigned long flags; |
| 219 | u32 temp; |
| 220 | |
Anton Vorontsov | 43a5a01 | 2010-02-18 16:43:12 +0300 | [diff] [blame] | 221 | raw_spin_lock_irqsave(&qe_ic_lock, flags); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 222 | |
| 223 | temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); |
| 224 | qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, |
| 225 | temp & ~qe_ic_info[src].mask); |
| 226 | |
Scott Wood | 2c1d2f3 | 2006-12-06 15:16:24 -0600 | [diff] [blame] | 227 | /* Flush the above write before enabling interrupts; otherwise, |
| 228 | * spurious interrupts will sometimes happen. To be 100% sure |
| 229 | * that the write has reached the device before interrupts are |
| 230 | * enabled, the mask register would have to be read back; however, |
| 231 | * this is not required for correctness, only to avoid wasting |
| 232 | * time on a large number of spurious interrupts. In testing, |
| 233 | * a sync reduced the observed spurious interrupts to zero. |
| 234 | */ |
| 235 | mb(); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 236 | |
Anton Vorontsov | 43a5a01 | 2010-02-18 16:43:12 +0300 | [diff] [blame] | 237 | raw_spin_unlock_irqrestore(&qe_ic_lock, flags); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 238 | } |
| 239 | |
| 240 | static struct irq_chip qe_ic_irq_chip = { |
Anton Blanchard | fc380c0 | 2010-01-31 20:33:41 +0000 | [diff] [blame] | 241 | .name = "QEIC", |
Lennert Buytenhek | 3a0adfa | 2011-03-08 22:27:00 +0000 | [diff] [blame] | 242 | .irq_unmask = qe_ic_unmask_irq, |
| 243 | .irq_mask = qe_ic_mask_irq, |
| 244 | .irq_mask_ack = qe_ic_mask_irq, |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 245 | }; |
| 246 | |
Marc Zyngier | ad3aedf | 2015-07-28 14:46:08 +0100 | [diff] [blame] | 247 | static int qe_ic_host_match(struct irq_domain *h, struct device_node *node, |
| 248 | enum irq_domain_bus_token bus_token) |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 249 | { |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 250 | /* Exact match, unless qe_ic node is NULL */ |
Michael Ellerman | 52964f8 | 2007-08-28 18:47:54 +1000 | [diff] [blame] | 251 | return h->of_node == NULL || h->of_node == node; |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 252 | } |
| 253 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 254 | static int qe_ic_host_map(struct irq_domain *h, unsigned int virq, |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 255 | irq_hw_number_t hw) |
| 256 | { |
| 257 | struct qe_ic *qe_ic = h->host_data; |
| 258 | struct irq_chip *chip; |
| 259 | |
| 260 | if (qe_ic_info[hw].mask == 0) { |
Frans Pop | 8354be9 | 2010-02-06 07:47:20 +0000 | [diff] [blame] | 261 | printk(KERN_ERR "Can't map reserved IRQ\n"); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 262 | return -EINVAL; |
| 263 | } |
| 264 | /* Default chip */ |
| 265 | chip = &qe_ic->hc_irq; |
| 266 | |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 267 | irq_set_chip_data(virq, qe_ic); |
Thomas Gleixner | 98488db | 2011-03-25 15:43:57 +0100 | [diff] [blame] | 268 | irq_set_status_flags(virq, IRQ_LEVEL); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 269 | |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 270 | irq_set_chip_and_handler(virq, chip, handle_level_irq); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
Krzysztof Kozlowski | 202648a | 2015-04-27 21:48:47 +0900 | [diff] [blame] | 275 | static const struct irq_domain_ops qe_ic_host_ops = { |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 276 | .match = qe_ic_host_match, |
| 277 | .map = qe_ic_host_map, |
Grant Likely | ff8c3ab | 2012-01-24 17:09:13 -0700 | [diff] [blame] | 278 | .xlate = irq_domain_xlate_onetwocell, |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 279 | }; |
| 280 | |
| 281 | /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 282 | unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic) |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 283 | { |
| 284 | int irq; |
| 285 | |
| 286 | BUG_ON(qe_ic == NULL); |
| 287 | |
| 288 | /* get the interrupt source vector. */ |
| 289 | irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26; |
| 290 | |
| 291 | if (irq == 0) |
| 292 | return NO_IRQ; |
| 293 | |
| 294 | return irq_linear_revmap(qe_ic->irqhost, irq); |
| 295 | } |
| 296 | |
| 297 | /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 298 | unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic) |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 299 | { |
| 300 | int irq; |
| 301 | |
| 302 | BUG_ON(qe_ic == NULL); |
| 303 | |
| 304 | /* get the interrupt source vector. */ |
| 305 | irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26; |
| 306 | |
| 307 | if (irq == 0) |
| 308 | return NO_IRQ; |
| 309 | |
| 310 | return irq_linear_revmap(qe_ic->irqhost, irq); |
| 311 | } |
| 312 | |
Anton Vorontsov | cccd210 | 2007-10-05 21:47:29 +0400 | [diff] [blame] | 313 | void __init qe_ic_init(struct device_node *node, unsigned int flags, |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 314 | void (*low_handler)(struct irq_desc *desc), |
| 315 | void (*high_handler)(struct irq_desc *desc)) |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 316 | { |
| 317 | struct qe_ic *qe_ic; |
| 318 | struct resource res; |
| 319 | u32 temp = 0, ret, high_active = 0; |
| 320 | |
Michael Ellerman | 2272a55 | 2008-05-26 12:12:31 +1000 | [diff] [blame] | 321 | ret = of_address_to_resource(node, 0, &res); |
| 322 | if (ret) |
| 323 | return; |
| 324 | |
Anton Vorontsov | ea96025 | 2009-07-01 10:59:57 +0000 | [diff] [blame] | 325 | qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 326 | if (qe_ic == NULL) |
| 327 | return; |
| 328 | |
Grant Likely | a8db8cf | 2012-02-14 14:06:54 -0700 | [diff] [blame] | 329 | qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS, |
| 330 | &qe_ic_host_ops, qe_ic); |
Julia Lawall | 3475dd8 | 2009-08-01 10:52:51 +0200 | [diff] [blame] | 331 | if (qe_ic->irqhost == NULL) { |
| 332 | kfree(qe_ic); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 333 | return; |
Julia Lawall | 3475dd8 | 2009-08-01 10:52:51 +0200 | [diff] [blame] | 334 | } |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 335 | |
Joe Perches | 28f65c11 | 2011-06-09 09:13:32 -0700 | [diff] [blame] | 336 | qe_ic->regs = ioremap(res.start, resource_size(&res)); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 337 | |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 338 | qe_ic->hc_irq = qe_ic_irq_chip; |
| 339 | |
| 340 | qe_ic->virq_high = irq_of_parse_and_map(node, 0); |
| 341 | qe_ic->virq_low = irq_of_parse_and_map(node, 1); |
| 342 | |
| 343 | if (qe_ic->virq_low == NO_IRQ) { |
| 344 | printk(KERN_ERR "Failed to map QE_IC low IRQ\n"); |
Julia Lawall | 3475dd8 | 2009-08-01 10:52:51 +0200 | [diff] [blame] | 345 | kfree(qe_ic); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 346 | return; |
| 347 | } |
| 348 | |
| 349 | /* default priority scheme is grouped. If spread mode is */ |
| 350 | /* required, configure cicr accordingly. */ |
| 351 | if (flags & QE_IC_SPREADMODE_GRP_W) |
| 352 | temp |= CICR_GWCC; |
| 353 | if (flags & QE_IC_SPREADMODE_GRP_X) |
| 354 | temp |= CICR_GXCC; |
| 355 | if (flags & QE_IC_SPREADMODE_GRP_Y) |
| 356 | temp |= CICR_GYCC; |
| 357 | if (flags & QE_IC_SPREADMODE_GRP_Z) |
| 358 | temp |= CICR_GZCC; |
| 359 | if (flags & QE_IC_SPREADMODE_GRP_RISCA) |
| 360 | temp |= CICR_GRTA; |
| 361 | if (flags & QE_IC_SPREADMODE_GRP_RISCB) |
| 362 | temp |= CICR_GRTB; |
| 363 | |
| 364 | /* choose destination signal for highest priority interrupt */ |
| 365 | if (flags & QE_IC_HIGH_SIGNAL) { |
| 366 | temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT); |
| 367 | high_active = 1; |
| 368 | } |
| 369 | |
| 370 | qe_ic_write(qe_ic->regs, QEIC_CICR, temp); |
| 371 | |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 372 | irq_set_handler_data(qe_ic->virq_low, qe_ic); |
| 373 | irq_set_chained_handler(qe_ic->virq_low, low_handler); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 374 | |
Anton Vorontsov | cccd210 | 2007-10-05 21:47:29 +0400 | [diff] [blame] | 375 | if (qe_ic->virq_high != NO_IRQ && |
| 376 | qe_ic->virq_high != qe_ic->virq_low) { |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 377 | irq_set_handler_data(qe_ic->virq_high, qe_ic); |
| 378 | irq_set_chained_handler(qe_ic->virq_high, high_handler); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 379 | } |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 380 | } |
| 381 | |
| 382 | void qe_ic_set_highest_priority(unsigned int virq, int high) |
| 383 | { |
| 384 | struct qe_ic *qe_ic = qe_ic_from_irq(virq); |
| 385 | unsigned int src = virq_to_hw(virq); |
| 386 | u32 temp = 0; |
| 387 | |
| 388 | temp = qe_ic_read(qe_ic->regs, QEIC_CICR); |
| 389 | |
| 390 | temp &= ~CICR_HP_MASK; |
| 391 | temp |= src << CICR_HP_SHIFT; |
| 392 | |
| 393 | temp &= ~CICR_HPIT_MASK; |
| 394 | temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT; |
| 395 | |
| 396 | qe_ic_write(qe_ic->regs, QEIC_CICR, temp); |
| 397 | } |
| 398 | |
| 399 | /* Set Priority level within its group, from 1 to 8 */ |
| 400 | int qe_ic_set_priority(unsigned int virq, unsigned int priority) |
| 401 | { |
| 402 | struct qe_ic *qe_ic = qe_ic_from_irq(virq); |
| 403 | unsigned int src = virq_to_hw(virq); |
| 404 | u32 temp; |
| 405 | |
| 406 | if (priority > 8 || priority == 0) |
| 407 | return -EINVAL; |
| 408 | if (src > 127) |
| 409 | return -EINVAL; |
| 410 | if (qe_ic_info[src].pri_reg == 0) |
| 411 | return -EINVAL; |
| 412 | |
| 413 | temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg); |
| 414 | |
| 415 | if (priority < 4) { |
| 416 | temp &= ~(0x7 << (32 - priority * 3)); |
| 417 | temp |= qe_ic_info[src].pri_code << (32 - priority * 3); |
| 418 | } else { |
| 419 | temp &= ~(0x7 << (24 - priority * 3)); |
| 420 | temp |= qe_ic_info[src].pri_code << (24 - priority * 3); |
| 421 | } |
| 422 | |
| 423 | qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp); |
| 424 | |
| 425 | return 0; |
| 426 | } |
| 427 | |
| 428 | /* Set a QE priority to use high irq, only priority 1~2 can use high irq */ |
| 429 | int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high) |
| 430 | { |
| 431 | struct qe_ic *qe_ic = qe_ic_from_irq(virq); |
| 432 | unsigned int src = virq_to_hw(virq); |
| 433 | u32 temp, control_reg = QEIC_CICNR, shift = 0; |
| 434 | |
| 435 | if (priority > 2 || priority == 0) |
| 436 | return -EINVAL; |
| 437 | |
| 438 | switch (qe_ic_info[src].pri_reg) { |
| 439 | case QEIC_CIPZCC: |
| 440 | shift = CICNR_ZCC1T_SHIFT; |
| 441 | break; |
| 442 | case QEIC_CIPWCC: |
| 443 | shift = CICNR_WCC1T_SHIFT; |
| 444 | break; |
| 445 | case QEIC_CIPYCC: |
| 446 | shift = CICNR_YCC1T_SHIFT; |
| 447 | break; |
| 448 | case QEIC_CIPXCC: |
| 449 | shift = CICNR_XCC1T_SHIFT; |
| 450 | break; |
| 451 | case QEIC_CIPRTA: |
| 452 | shift = CRICR_RTA1T_SHIFT; |
| 453 | control_reg = QEIC_CRICR; |
| 454 | break; |
| 455 | case QEIC_CIPRTB: |
| 456 | shift = CRICR_RTB1T_SHIFT; |
| 457 | control_reg = QEIC_CRICR; |
| 458 | break; |
| 459 | default: |
| 460 | return -EINVAL; |
| 461 | } |
| 462 | |
| 463 | shift += (2 - priority) * 2; |
| 464 | temp = qe_ic_read(qe_ic->regs, control_reg); |
| 465 | temp &= ~(SIGNAL_MASK << shift); |
| 466 | temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift; |
| 467 | qe_ic_write(qe_ic->regs, control_reg, temp); |
| 468 | |
| 469 | return 0; |
| 470 | } |
| 471 | |
Kay Sievers | cfde779 | 2011-12-21 15:09:51 -0800 | [diff] [blame] | 472 | static struct bus_type qe_ic_subsys = { |
Kay Sievers | af5ca3f | 2007-12-20 02:09:39 +0100 | [diff] [blame] | 473 | .name = "qe_ic", |
Kay Sievers | cfde779 | 2011-12-21 15:09:51 -0800 | [diff] [blame] | 474 | .dev_name = "qe_ic", |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 475 | }; |
| 476 | |
Kay Sievers | cfde779 | 2011-12-21 15:09:51 -0800 | [diff] [blame] | 477 | static struct device device_qe_ic = { |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 478 | .id = 0, |
Kay Sievers | cfde779 | 2011-12-21 15:09:51 -0800 | [diff] [blame] | 479 | .bus = &qe_ic_subsys, |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 480 | }; |
| 481 | |
| 482 | static int __init init_qe_ic_sysfs(void) |
| 483 | { |
| 484 | int rc; |
| 485 | |
| 486 | printk(KERN_DEBUG "Registering qe_ic with sysfs...\n"); |
| 487 | |
Kay Sievers | cfde779 | 2011-12-21 15:09:51 -0800 | [diff] [blame] | 488 | rc = subsys_system_register(&qe_ic_subsys, NULL); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 489 | if (rc) { |
| 490 | printk(KERN_ERR "Failed registering qe_ic sys class\n"); |
| 491 | return -ENODEV; |
| 492 | } |
Kay Sievers | cfde779 | 2011-12-21 15:09:51 -0800 | [diff] [blame] | 493 | rc = device_register(&device_qe_ic); |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 494 | if (rc) { |
| 495 | printk(KERN_ERR "Failed registering qe_ic sys device\n"); |
| 496 | return -ENODEV; |
| 497 | } |
| 498 | return 0; |
| 499 | } |
| 500 | |
| 501 | subsys_initcall(init_qe_ic_sysfs); |