Kukjin Kim | f7d7707 | 2011-06-01 14:18:22 -0700 | [diff] [blame] | 1 | /* |
Kukjin Kim | 7d30e8b | 2011-02-14 16:33:10 +0900 | [diff] [blame] | 2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 3 | * http://www.samsung.com |
| 4 | * |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 5 | * EXYNOS4210 - CPU frequency scaling support |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
Jaecheol Lee | 6c523c6 | 2012-01-07 20:18:39 +0900 | [diff] [blame] | 12 | #include <linux/module.h> |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/io.h> |
| 17 | #include <linux/slab.h> |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 18 | #include <linux/cpufreq.h> |
| 19 | |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 20 | #include <mach/regs-clock.h> |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 21 | #include <mach/cpufreq.h> |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 22 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 23 | #define CPUFREQ_LEVEL_END L5 |
| 24 | |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 25 | static struct clk *cpu_clk; |
| 26 | static struct clk *moutcore; |
| 27 | static struct clk *mout_mpll; |
| 28 | static struct clk *mout_apll; |
| 29 | |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 30 | struct cpufreq_clkdiv { |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 31 | unsigned int index; |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 32 | unsigned int clkdiv; |
| 33 | }; |
| 34 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 35 | static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END] = { |
| 36 | 1250000, 1150000, 1050000, 975000, 950000, |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 37 | }; |
| 38 | |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 39 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 40 | static struct cpufreq_clkdiv exynos4210_clkdiv_table[CPUFREQ_LEVEL_END]; |
| 41 | |
| 42 | static struct cpufreq_frequency_table exynos4210_freq_table[] = { |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 43 | {L0, 1200*1000}, |
| 44 | {L1, 1000*1000}, |
| 45 | {L2, 800*1000}, |
| 46 | {L3, 500*1000}, |
| 47 | {L4, 200*1000}, |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 48 | {0, CPUFREQ_TABLE_END}, |
| 49 | }; |
| 50 | |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 51 | static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = { |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 52 | /* |
| 53 | * Clock divider value for following |
| 54 | * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, |
| 55 | * DIVATB, DIVPCLK_DBG, DIVAPLL } |
| 56 | */ |
| 57 | |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 58 | /* ARM L0: 1200MHz */ |
| 59 | { 0, 3, 7, 3, 4, 1, 7 }, |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 60 | |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 61 | /* ARM L1: 1000MHz */ |
| 62 | { 0, 3, 7, 3, 4, 1, 7 }, |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 63 | |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 64 | /* ARM L2: 800MHz */ |
| 65 | { 0, 3, 7, 3, 3, 1, 7 }, |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 66 | |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 67 | /* ARM L3: 500MHz */ |
| 68 | { 0, 3, 7, 3, 3, 1, 7 }, |
| 69 | |
| 70 | /* ARM L4: 200MHz */ |
| 71 | { 0, 1, 3, 1, 3, 1, 0 }, |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 72 | }; |
| 73 | |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 74 | static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = { |
| 75 | /* |
| 76 | * Clock divider value for following |
| 77 | * { DIVCOPY, DIVHPM } |
| 78 | */ |
| 79 | |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 80 | /* ARM L0: 1200MHz */ |
| 81 | { 5, 0 }, |
| 82 | |
| 83 | /* ARM L1: 1000MHz */ |
| 84 | { 4, 0 }, |
| 85 | |
| 86 | /* ARM L2: 800MHz */ |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 87 | { 3, 0 }, |
| 88 | |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 89 | /* ARM L3: 500MHz */ |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 90 | { 3, 0 }, |
| 91 | |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 92 | /* ARM L4: 200MHz */ |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 93 | { 3, 0 }, |
| 94 | }; |
| 95 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 96 | static unsigned int exynos4210_apll_pms_table[CPUFREQ_LEVEL_END] = { |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 97 | /* APLL FOUT L0: 1200MHz */ |
| 98 | ((150 << 16) | (3 << 8) | 1), |
| 99 | |
| 100 | /* APLL FOUT L1: 1000MHz */ |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 101 | ((250 << 16) | (6 << 8) | 1), |
| 102 | |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 103 | /* APLL FOUT L2: 800MHz */ |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 104 | ((200 << 16) | (6 << 8) | 1), |
| 105 | |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 106 | /* APLL FOUT L3: 500MHz */ |
| 107 | ((250 << 16) | (6 << 8) | 2), |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 108 | |
Jaecheol Lee | ba9d780 | 2011-12-07 11:43:56 +0900 | [diff] [blame] | 109 | /* APLL FOUT L4: 200MHz */ |
| 110 | ((200 << 16) | (6 << 8) | 3), |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 111 | }; |
| 112 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 113 | static void exynos4210_set_clkdiv(unsigned int div_index) |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 114 | { |
| 115 | unsigned int tmp; |
| 116 | |
| 117 | /* Change Divider - CPU0 */ |
| 118 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 119 | tmp = exynos4210_clkdiv_table[div_index].clkdiv; |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 120 | |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 121 | __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 122 | |
| 123 | do { |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 124 | tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU); |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 125 | } while (tmp & 0x1111111); |
| 126 | |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 127 | /* Change Divider - CPU1 */ |
| 128 | |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 129 | tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 130 | |
| 131 | tmp &= ~((0x7 << 4) | 0x7); |
| 132 | |
| 133 | tmp |= ((clkdiv_cpu1[div_index][0] << 4) | |
| 134 | (clkdiv_cpu1[div_index][1] << 0)); |
| 135 | |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 136 | __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 137 | |
| 138 | do { |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 139 | tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 140 | } while (tmp & 0x11); |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 141 | } |
| 142 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 143 | static void exynos4210_set_apll(unsigned int index) |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 144 | { |
| 145 | unsigned int tmp; |
| 146 | |
| 147 | /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ |
| 148 | clk_set_parent(moutcore, mout_mpll); |
| 149 | |
| 150 | do { |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 151 | tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU) |
| 152 | >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 153 | tmp &= 0x7; |
| 154 | } while (tmp != 0x2); |
| 155 | |
| 156 | /* 2. Set APLL Lock time */ |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 157 | __raw_writel(EXYNOS4_APLL_LOCKTIME, EXYNOS4_APLL_LOCK); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 158 | |
| 159 | /* 3. Change PLL PMS values */ |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 160 | tmp = __raw_readl(EXYNOS4_APLL_CON0); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 161 | tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 162 | tmp |= exynos4210_apll_pms_table[index]; |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 163 | __raw_writel(tmp, EXYNOS4_APLL_CON0); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 164 | |
| 165 | /* 4. wait_lock_time */ |
| 166 | do { |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 167 | tmp = __raw_readl(EXYNOS4_APLL_CON0); |
| 168 | } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT))); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 169 | |
| 170 | /* 5. MUX_CORE_SEL = APLL */ |
| 171 | clk_set_parent(moutcore, mout_apll); |
| 172 | |
| 173 | do { |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 174 | tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU); |
| 175 | tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK; |
| 176 | } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 177 | } |
| 178 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 179 | bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index) |
| 180 | { |
| 181 | unsigned int old_pm = (exynos4210_apll_pms_table[old_index] >> 8); |
| 182 | unsigned int new_pm = (exynos4210_apll_pms_table[new_index] >> 8); |
| 183 | |
| 184 | return (old_pm == new_pm) ? 0 : 1; |
| 185 | } |
| 186 | |
| 187 | static void exynos4210_set_frequency(unsigned int old_index, |
| 188 | unsigned int new_index) |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 189 | { |
| 190 | unsigned int tmp; |
| 191 | |
| 192 | if (old_index > new_index) { |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 193 | if (!exynos4210_pms_change(old_index, new_index)) { |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 194 | /* 1. Change the system clock divider values */ |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 195 | exynos4210_set_clkdiv(new_index); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 196 | |
| 197 | /* 2. Change just s value in apll m,p,s value */ |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 198 | tmp = __raw_readl(EXYNOS4_APLL_CON0); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 199 | tmp &= ~(0x7 << 0); |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 200 | tmp |= (exynos4210_apll_pms_table[new_index] & 0x7); |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 201 | __raw_writel(tmp, EXYNOS4_APLL_CON0); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 202 | } else { |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 203 | /* Clock Configuration Procedure */ |
| 204 | /* 1. Change the system clock divider values */ |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 205 | exynos4210_set_clkdiv(new_index); |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 206 | /* 2. Change the apll m,p,s value */ |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 207 | exynos4210_set_apll(new_index); |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 208 | } |
| 209 | } else if (old_index < new_index) { |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 210 | if (!exynos4210_pms_change(old_index, new_index)) { |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 211 | /* 1. Change just s value in apll m,p,s value */ |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 212 | tmp = __raw_readl(EXYNOS4_APLL_CON0); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 213 | tmp &= ~(0x7 << 0); |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 214 | tmp |= (exynos4210_apll_pms_table[new_index] & 0x7); |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 215 | __raw_writel(tmp, EXYNOS4_APLL_CON0); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 216 | |
| 217 | /* 2. Change the system clock divider values */ |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 218 | exynos4210_set_clkdiv(new_index); |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 219 | } else { |
| 220 | /* Clock Configuration Procedure */ |
| 221 | /* 1. Change the apll m,p,s value */ |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 222 | exynos4210_set_apll(new_index); |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 223 | /* 2. Change the system clock divider values */ |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 224 | exynos4210_set_clkdiv(new_index); |
Sangwook Ju | bf5ce05 | 2010-12-22 16:49:32 +0900 | [diff] [blame] | 225 | } |
| 226 | } |
| 227 | } |
| 228 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 229 | int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 230 | { |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 231 | int i; |
| 232 | unsigned int tmp; |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 233 | unsigned long rate; |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 234 | |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 235 | cpu_clk = clk_get(NULL, "armclk"); |
| 236 | if (IS_ERR(cpu_clk)) |
| 237 | return PTR_ERR(cpu_clk); |
| 238 | |
| 239 | moutcore = clk_get(NULL, "moutcore"); |
| 240 | if (IS_ERR(moutcore)) |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 241 | goto err_moutcore; |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 242 | |
| 243 | mout_mpll = clk_get(NULL, "mout_mpll"); |
| 244 | if (IS_ERR(mout_mpll)) |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 245 | goto err_mout_mpll; |
| 246 | |
| 247 | rate = clk_get_rate(mout_mpll) / 1000; |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 248 | |
| 249 | mout_apll = clk_get(NULL, "mout_apll"); |
| 250 | if (IS_ERR(mout_apll)) |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 251 | goto err_mout_apll; |
MyungJoo Ham | 0073f53 | 2011-08-18 19:45:16 +0900 | [diff] [blame] | 252 | |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 253 | tmp = __raw_readl(EXYNOS4_CLKDIV_CPU); |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 254 | |
| 255 | for (i = L0; i < CPUFREQ_LEVEL_END; i++) { |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 256 | tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK | |
| 257 | EXYNOS4_CLKDIV_CPU0_COREM0_MASK | |
| 258 | EXYNOS4_CLKDIV_CPU0_COREM1_MASK | |
| 259 | EXYNOS4_CLKDIV_CPU0_PERIPH_MASK | |
| 260 | EXYNOS4_CLKDIV_CPU0_ATB_MASK | |
| 261 | EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK | |
| 262 | EXYNOS4_CLKDIV_CPU0_APLL_MASK); |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 263 | |
Kukjin Kim | 09cee1a | 2012-01-31 13:49:24 +0900 | [diff] [blame] | 264 | tmp |= ((clkdiv_cpu0[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) | |
| 265 | (clkdiv_cpu0[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) | |
| 266 | (clkdiv_cpu0[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) | |
| 267 | (clkdiv_cpu0[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) | |
| 268 | (clkdiv_cpu0[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) | |
| 269 | (clkdiv_cpu0[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) | |
| 270 | (clkdiv_cpu0[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)); |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 271 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 272 | exynos4210_clkdiv_table[i].clkdiv = tmp; |
Jaecheol Lee | 27f805d | 2011-12-07 11:44:09 +0900 | [diff] [blame] | 273 | } |
| 274 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 275 | info->mpll_freq_khz = rate; |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 276 | info->pll_safe_idx = L2; |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 277 | info->cpu_clk = cpu_clk; |
| 278 | info->volt_table = exynos4210_volt_table; |
| 279 | info->freq_table = exynos4210_freq_table; |
| 280 | info->set_freq = exynos4210_set_frequency; |
| 281 | info->need_apll_change = exynos4210_pms_change; |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 282 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 283 | return 0; |
| 284 | |
| 285 | err_mout_apll: |
Jonghwan Choi | 184cddd | 2012-12-23 15:51:40 -0800 | [diff] [blame^] | 286 | clk_put(mout_mpll); |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 287 | err_mout_mpll: |
Jonghwan Choi | 184cddd | 2012-12-23 15:51:40 -0800 | [diff] [blame^] | 288 | clk_put(moutcore); |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 289 | err_moutcore: |
Jonghwan Choi | 184cddd | 2012-12-23 15:51:40 -0800 | [diff] [blame^] | 290 | clk_put(cpu_clk); |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 291 | |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 292 | pr_debug("%s: failed initialization\n", __func__); |
Sunyoung Kang | f40f91f | 2010-09-16 17:59:21 +0900 | [diff] [blame] | 293 | return -EINVAL; |
| 294 | } |
Jaecheol Lee | a125a17 | 2012-01-07 20:18:35 +0900 | [diff] [blame] | 295 | EXPORT_SYMBOL(exynos4210_cpufreq_init); |