blob: 0b34a1aee9b647ae16bd1ccbf3657ac6741dd51c [file] [log] [blame]
Daniel Vetter76aaf222010-11-05 22:23:30 +01001/*
2 * Copyright © 2010 Daniel Vetter
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include "drmP.h"
26#include "drm.h"
27#include "i915_drm.h"
28#include "i915_drv.h"
29#include "i915_trace.h"
30#include "intel_drv.h"
31
32void i915_gem_restore_gtt_mappings(struct drm_device *dev)
33{
34 struct drm_i915_private *dev_priv = dev->dev_private;
35 struct drm_i915_gem_object *obj_priv;
Daniel Vetter76aaf222010-11-05 22:23:30 +010036
37 list_for_each_entry(obj_priv,
38 &dev_priv->mm.gtt_list,
39 gtt_list) {
Daniel Vetter185cbcb2010-11-06 12:12:35 +010040 if (dev_priv->mm.gtt->needs_dmar) {
41 BUG_ON(!obj_priv->sg_list);
42
43 intel_gtt_insert_sg_entries(obj_priv->sg_list,
44 obj_priv->num_sg,
45 obj_priv->gtt_space->start
46 >> PAGE_SHIFT,
47 obj_priv->agp_type);
48 } else
49 intel_gtt_insert_pages(obj_priv->gtt_space->start
50 >> PAGE_SHIFT,
51 obj_priv->base.size >> PAGE_SHIFT,
52 obj_priv->pages,
53 obj_priv->agp_type);
Daniel Vetter76aaf222010-11-05 22:23:30 +010054 }
55
56 /* Be paranoid and flush the chipset cache. */
57 intel_gtt_chipset_flush();
58}
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +010059
60int i915_gem_gtt_bind_object(struct drm_gem_object *obj)
61{
62 struct drm_device *dev = obj->dev;
Daniel Vetter185cbcb2010-11-06 12:12:35 +010063 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +010064 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Daniel Vetter185cbcb2010-11-06 12:12:35 +010065 int ret;
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +010066
Daniel Vetter185cbcb2010-11-06 12:12:35 +010067 if (dev_priv->mm.gtt->needs_dmar) {
68 ret = intel_gtt_map_memory(obj_priv->pages,
69 obj->size >> PAGE_SHIFT,
70 &obj_priv->sg_list,
71 &obj_priv->num_sg);
72 if (ret != 0)
73 return ret;
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +010074
Daniel Vetter185cbcb2010-11-06 12:12:35 +010075 intel_gtt_insert_sg_entries(obj_priv->sg_list, obj_priv->num_sg,
76 obj_priv->gtt_space->start
77 >> PAGE_SHIFT,
78 obj_priv->agp_type);
79 } else
80 intel_gtt_insert_pages(obj_priv->gtt_space->start >> PAGE_SHIFT,
81 obj->size >> PAGE_SHIFT,
82 obj_priv->pages,
83 obj_priv->agp_type);
84
85 return 0;
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +010086}
87
88void i915_gem_gtt_unbind_object(struct drm_gem_object *obj)
89{
Daniel Vetter185cbcb2010-11-06 12:12:35 +010090 struct drm_device *dev = obj->dev;
91 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +010092 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
93
Daniel Vetter185cbcb2010-11-06 12:12:35 +010094 if (dev_priv->mm.gtt->needs_dmar) {
95 intel_gtt_unmap_memory(obj_priv->sg_list, obj_priv->num_sg);
96 obj_priv->sg_list = NULL;
97 obj_priv->num_sg = 0;
98 }
99
100 intel_gtt_clear_range(obj_priv->gtt_space->start >> PAGE_SHIFT,
101 obj->size >> PAGE_SHIFT);
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +0100102}