Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 1 | #include <dt-bindings/clock/tegra30-car.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 3 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 4 | |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 5 | #include "skeleton.dtsi" |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 6 | |
| 7 | / { |
| 8 | compatible = "nvidia,tegra30"; |
| 9 | interrupt-parent = <&intc>; |
| 10 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 11 | aliases { |
| 12 | serial0 = &uarta; |
| 13 | serial1 = &uartb; |
| 14 | serial2 = &uartc; |
| 15 | serial3 = &uartd; |
| 16 | serial4 = &uarte; |
| 17 | }; |
| 18 | |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 19 | pcie-controller { |
| 20 | compatible = "nvidia,tegra30-pcie"; |
| 21 | device_type = "pci"; |
| 22 | reg = <0x00003000 0x00000800 /* PADS registers */ |
| 23 | 0x00003800 0x00000200 /* AFI registers */ |
| 24 | 0x10000000 0x10000000>; /* configuration space */ |
| 25 | reg-names = "pads", "afi", "cs"; |
| 26 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ |
| 27 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ |
| 28 | interrupt-names = "intr", "msi"; |
| 29 | |
| 30 | bus-range = <0x00 0xff>; |
| 31 | #address-cells = <3>; |
| 32 | #size-cells = <2>; |
| 33 | |
| 34 | ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ |
| 35 | 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ |
| 36 | 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ |
| 37 | 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ |
Jay Agarwal | d7283c1 | 2013-08-09 16:49:31 +0200 | [diff] [blame] | 38 | 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ |
| 39 | 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 40 | |
| 41 | clocks = <&tegra_car TEGRA30_CLK_PCIE>, |
| 42 | <&tegra_car TEGRA30_CLK_AFI>, |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 43 | <&tegra_car TEGRA30_CLK_PLL_E>, |
| 44 | <&tegra_car TEGRA30_CLK_CML0>; |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame] | 45 | clock-names = "pex", "afi", "pll_e", "cml"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 46 | resets = <&tegra_car 70>, |
| 47 | <&tegra_car 72>, |
| 48 | <&tegra_car 74>; |
| 49 | reset-names = "pex", "afi", "pcie_x"; |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 50 | status = "disabled"; |
| 51 | |
| 52 | pci@1,0 { |
| 53 | device_type = "pci"; |
| 54 | assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; |
| 55 | reg = <0x000800 0 0 0 0>; |
| 56 | status = "disabled"; |
| 57 | |
| 58 | #address-cells = <3>; |
| 59 | #size-cells = <2>; |
| 60 | ranges; |
| 61 | |
| 62 | nvidia,num-lanes = <2>; |
| 63 | }; |
| 64 | |
| 65 | pci@2,0 { |
| 66 | device_type = "pci"; |
| 67 | assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; |
| 68 | reg = <0x001000 0 0 0 0>; |
| 69 | status = "disabled"; |
| 70 | |
| 71 | #address-cells = <3>; |
| 72 | #size-cells = <2>; |
| 73 | ranges; |
| 74 | |
| 75 | nvidia,num-lanes = <2>; |
| 76 | }; |
| 77 | |
| 78 | pci@3,0 { |
| 79 | device_type = "pci"; |
| 80 | assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; |
| 81 | reg = <0x001800 0 0 0 0>; |
| 82 | status = "disabled"; |
| 83 | |
| 84 | #address-cells = <3>; |
| 85 | #size-cells = <2>; |
| 86 | ranges; |
| 87 | |
| 88 | nvidia,num-lanes = <2>; |
| 89 | }; |
| 90 | }; |
| 91 | |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 92 | host1x { |
| 93 | compatible = "nvidia,tegra30-host1x", "simple-bus"; |
| 94 | reg = <0x50000000 0x00024000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 95 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 96 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 97 | clocks = <&tegra_car TEGRA30_CLK_HOST1X>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 98 | resets = <&tegra_car 28>; |
| 99 | reset-names = "host1x"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 100 | |
| 101 | #address-cells = <1>; |
| 102 | #size-cells = <1>; |
| 103 | |
| 104 | ranges = <0x54000000 0x54000000 0x04000000>; |
| 105 | |
| 106 | mpe { |
| 107 | compatible = "nvidia,tegra30-mpe"; |
| 108 | reg = <0x54040000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 109 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 110 | clocks = <&tegra_car TEGRA30_CLK_MPE>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 111 | resets = <&tegra_car 60>; |
| 112 | reset-names = "mpe"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 113 | }; |
| 114 | |
| 115 | vi { |
| 116 | compatible = "nvidia,tegra30-vi"; |
| 117 | reg = <0x54080000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 118 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 119 | clocks = <&tegra_car TEGRA30_CLK_VI>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 120 | resets = <&tegra_car 20>; |
| 121 | reset-names = "vi"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | epp { |
| 125 | compatible = "nvidia,tegra30-epp"; |
| 126 | reg = <0x540c0000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 127 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 128 | clocks = <&tegra_car TEGRA30_CLK_EPP>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 129 | resets = <&tegra_car 19>; |
| 130 | reset-names = "epp"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | isp { |
| 134 | compatible = "nvidia,tegra30-isp"; |
| 135 | reg = <0x54100000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 136 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 137 | clocks = <&tegra_car TEGRA30_CLK_ISP>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 138 | resets = <&tegra_car 23>; |
| 139 | reset-names = "isp"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 140 | }; |
| 141 | |
| 142 | gr2d { |
| 143 | compatible = "nvidia,tegra30-gr2d"; |
| 144 | reg = <0x54140000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 145 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 146 | resets = <&tegra_car 21>; |
| 147 | reset-names = "2d"; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 148 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 149 | }; |
| 150 | |
| 151 | gr3d { |
| 152 | compatible = "nvidia,tegra30-gr3d"; |
| 153 | reg = <0x54180000 0x00040000>; |
Thierry Reding | c71d390 | 2013-10-15 17:28:02 +0200 | [diff] [blame] | 154 | clocks = <&tegra_car TEGRA30_CLK_GR3D |
| 155 | &tegra_car TEGRA30_CLK_GR3D2>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 156 | clock-names = "3d", "3d2"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 157 | resets = <&tegra_car 24>, |
| 158 | <&tegra_car 98>; |
| 159 | reset-names = "3d", "3d2"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 160 | }; |
| 161 | |
| 162 | dc@54200000 { |
Thierry Reding | 05465f4 | 2013-10-15 17:27:51 +0200 | [diff] [blame] | 163 | compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 164 | reg = <0x54200000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 165 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 166 | clocks = <&tegra_car TEGRA30_CLK_DISP1>, |
| 167 | <&tegra_car TEGRA30_CLK_PLL_P>; |
Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 168 | clock-names = "dc", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 169 | resets = <&tegra_car 27>; |
| 170 | reset-names = "dc"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 171 | |
| 172 | rgb { |
| 173 | status = "disabled"; |
| 174 | }; |
| 175 | }; |
| 176 | |
| 177 | dc@54240000 { |
| 178 | compatible = "nvidia,tegra30-dc"; |
| 179 | reg = <0x54240000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 180 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 181 | clocks = <&tegra_car TEGRA30_CLK_DISP2>, |
| 182 | <&tegra_car TEGRA30_CLK_PLL_P>; |
Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 183 | clock-names = "dc", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 184 | resets = <&tegra_car 26>; |
| 185 | reset-names = "dc"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 186 | |
| 187 | rgb { |
| 188 | status = "disabled"; |
| 189 | }; |
| 190 | }; |
| 191 | |
| 192 | hdmi { |
| 193 | compatible = "nvidia,tegra30-hdmi"; |
| 194 | reg = <0x54280000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 195 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 196 | clocks = <&tegra_car TEGRA30_CLK_HDMI>, |
| 197 | <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 198 | clock-names = "hdmi", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 199 | resets = <&tegra_car 51>; |
| 200 | reset-names = "hdmi"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 201 | status = "disabled"; |
| 202 | }; |
| 203 | |
| 204 | tvo { |
| 205 | compatible = "nvidia,tegra30-tvo"; |
| 206 | reg = <0x542c0000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 207 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 208 | clocks = <&tegra_car TEGRA30_CLK_TVO>; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 209 | status = "disabled"; |
| 210 | }; |
| 211 | |
| 212 | dsi { |
| 213 | compatible = "nvidia,tegra30-dsi"; |
| 214 | reg = <0x54300000 0x00040000>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 215 | clocks = <&tegra_car TEGRA30_CLK_DSIA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 216 | resets = <&tegra_car 48>; |
| 217 | reset-names = "dsi"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 218 | status = "disabled"; |
| 219 | }; |
| 220 | }; |
| 221 | |
Stephen Warren | 73368ba | 2012-09-19 14:17:24 -0600 | [diff] [blame] | 222 | timer@50004600 { |
| 223 | compatible = "arm,cortex-a9-twd-timer"; |
| 224 | reg = <0x50040600 0x20>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 225 | interrupts = <GIC_PPI 13 |
| 226 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 227 | clocks = <&tegra_car TEGRA30_CLK_TWD>; |
Stephen Warren | 73368ba | 2012-09-19 14:17:24 -0600 | [diff] [blame] | 228 | }; |
| 229 | |
Stephen Warren | f9eb26a | 2012-05-11 16:17:47 -0600 | [diff] [blame] | 230 | intc: interrupt-controller { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 231 | compatible = "arm,cortex-a9-gic"; |
Stephen Warren | 5ff4888 | 2012-05-11 16:26:03 -0600 | [diff] [blame] | 232 | reg = <0x50041000 0x1000 |
| 233 | 0x50040100 0x0100>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 234 | interrupt-controller; |
| 235 | #interrupt-cells = <3>; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 236 | }; |
| 237 | |
Stephen Warren | bb2c1de | 2013-01-14 10:09:16 -0700 | [diff] [blame] | 238 | cache-controller { |
| 239 | compatible = "arm,pl310-cache"; |
| 240 | reg = <0x50043000 0x1000>; |
| 241 | arm,data-latency = <6 6 2>; |
| 242 | arm,tag-latency = <5 5 2>; |
| 243 | cache-unified; |
| 244 | cache-level = <2>; |
| 245 | }; |
| 246 | |
Stephen Warren | 2f2b7fb | 2012-09-19 12:02:31 -0600 | [diff] [blame] | 247 | timer@60005000 { |
| 248 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; |
| 249 | reg = <0x60005000 0x400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 250 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 251 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 252 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 253 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 254 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 255 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 256 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; |
Stephen Warren | 2f2b7fb | 2012-09-19 12:02:31 -0600 | [diff] [blame] | 257 | }; |
| 258 | |
Prashant Gaikwad | 9598566 | 2013-01-11 13:16:23 +0530 | [diff] [blame] | 259 | tegra_car: clock { |
| 260 | compatible = "nvidia,tegra30-car"; |
| 261 | reg = <0x60006000 0x1000>; |
| 262 | #clock-cells = <1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 263 | #reset-cells = <1>; |
Prashant Gaikwad | 9598566 | 2013-01-11 13:16:23 +0530 | [diff] [blame] | 264 | }; |
| 265 | |
Stephen Warren | f9eb26a | 2012-05-11 16:17:47 -0600 | [diff] [blame] | 266 | apbdma: dma { |
Stephen Warren | 8051b75 | 2012-01-11 16:09:54 -0700 | [diff] [blame] | 267 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
| 268 | reg = <0x6000a000 0x1400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 269 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 270 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 271 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 272 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 273 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 274 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 275 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 276 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 277 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 278 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 279 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 280 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 281 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 282 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 283 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 284 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 285 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 286 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 287 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 288 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 289 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 290 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 291 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 292 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 293 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 294 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 295 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 296 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 297 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 298 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 299 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 300 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 301 | clocks = <&tegra_car TEGRA30_CLK_APBDMA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 302 | resets = <&tegra_car 34>; |
| 303 | reset-names = "dma"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 304 | #dma-cells = <1>; |
Stephen Warren | 8051b75 | 2012-01-11 16:09:54 -0700 | [diff] [blame] | 305 | }; |
| 306 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 307 | ahb: ahb { |
| 308 | compatible = "nvidia,tegra30-ahb"; |
| 309 | reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ |
| 310 | }; |
| 311 | |
| 312 | gpio: gpio { |
Laxman Dewangan | 35f210e | 2012-12-19 20:27:12 +0530 | [diff] [blame] | 313 | compatible = "nvidia,tegra30-gpio"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 314 | reg = <0x6000d000 0x1000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 315 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 316 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 317 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 318 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 319 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 320 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 321 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 322 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 323 | #gpio-cells = <2>; |
| 324 | gpio-controller; |
| 325 | #interrupt-cells = <2>; |
| 326 | interrupt-controller; |
| 327 | }; |
| 328 | |
| 329 | pinmux: pinmux { |
| 330 | compatible = "nvidia,tegra30-pinmux"; |
Pritesh Raithatha | 322337b | 2012-10-30 15:37:09 +0530 | [diff] [blame] | 331 | reg = <0x70000868 0xd4 /* Pad control registers */ |
| 332 | 0x70003000 0x3e4>; /* Mux registers */ |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 333 | }; |
| 334 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 335 | /* |
| 336 | * There are two serial driver i.e. 8250 based simple serial |
| 337 | * driver and APB DMA based serial driver for higher baudrate |
| 338 | * and performace. To enable the 8250 based driver, the compatible |
| 339 | * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable |
| 340 | * the APB DMA based serial driver, the comptible is |
| 341 | * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". |
| 342 | */ |
| 343 | uarta: serial@70006000 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 344 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 345 | reg = <0x70006000 0x40>; |
| 346 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 347 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 348 | clocks = <&tegra_car TEGRA30_CLK_UARTA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 349 | resets = <&tegra_car 6>; |
| 350 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 351 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 352 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 353 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 354 | }; |
| 355 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 356 | uartb: serial@70006040 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 357 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 358 | reg = <0x70006040 0x40>; |
| 359 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 360 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 361 | clocks = <&tegra_car TEGRA30_CLK_UARTB>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 362 | resets = <&tegra_car 7>; |
| 363 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 364 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 365 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 366 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 367 | }; |
| 368 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 369 | uartc: serial@70006200 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 370 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 371 | reg = <0x70006200 0x100>; |
| 372 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 373 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 374 | clocks = <&tegra_car TEGRA30_CLK_UARTC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 375 | resets = <&tegra_car 55>; |
| 376 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 377 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 378 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 379 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 380 | }; |
| 381 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 382 | uartd: serial@70006300 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 383 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 384 | reg = <0x70006300 0x100>; |
| 385 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 386 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 387 | clocks = <&tegra_car TEGRA30_CLK_UARTD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 388 | resets = <&tegra_car 65>; |
| 389 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 390 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 391 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 392 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 393 | }; |
| 394 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 395 | uarte: serial@70006400 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 396 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 397 | reg = <0x70006400 0x100>; |
| 398 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 399 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 400 | clocks = <&tegra_car TEGRA30_CLK_UARTE>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 401 | resets = <&tegra_car 66>; |
| 402 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 403 | dmas = <&apbdma 20>, <&apbdma 20>; |
| 404 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 405 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 406 | }; |
| 407 | |
Thierry Reding | 2b8b15d | 2012-09-20 17:06:05 +0200 | [diff] [blame] | 408 | pwm: pwm { |
Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 409 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
| 410 | reg = <0x7000a000 0x100>; |
| 411 | #pwm-cells = <2>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 412 | clocks = <&tegra_car TEGRA30_CLK_PWM>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 413 | resets = <&tegra_car 17>; |
| 414 | reset-names = "pwm"; |
Andrew Chew | b69cd98 | 2013-03-12 16:40:51 -0700 | [diff] [blame] | 415 | status = "disabled"; |
Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 416 | }; |
| 417 | |
Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 418 | rtc { |
| 419 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
| 420 | reg = <0x7000e000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 421 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 422 | clocks = <&tegra_car TEGRA30_CLK_RTC>; |
Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 423 | }; |
| 424 | |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 425 | i2c@7000c000 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 426 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 427 | reg = <0x7000c000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 428 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 429 | #address-cells = <1>; |
| 430 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 431 | clocks = <&tegra_car TEGRA30_CLK_I2C1>, |
| 432 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 433 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 434 | resets = <&tegra_car 12>; |
| 435 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 436 | dmas = <&apbdma 21>, <&apbdma 21>; |
| 437 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 438 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 439 | }; |
| 440 | |
| 441 | i2c@7000c400 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 442 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 443 | reg = <0x7000c400 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 444 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 445 | #address-cells = <1>; |
| 446 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 447 | clocks = <&tegra_car TEGRA30_CLK_I2C2>, |
| 448 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 449 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 450 | resets = <&tegra_car 54>; |
| 451 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 452 | dmas = <&apbdma 22>, <&apbdma 22>; |
| 453 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 454 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 455 | }; |
| 456 | |
| 457 | i2c@7000c500 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 458 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 459 | reg = <0x7000c500 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 460 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 461 | #address-cells = <1>; |
| 462 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 463 | clocks = <&tegra_car TEGRA30_CLK_I2C3>, |
| 464 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 465 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 466 | resets = <&tegra_car 67>; |
| 467 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 468 | dmas = <&apbdma 23>, <&apbdma 23>; |
| 469 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 470 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 471 | }; |
| 472 | |
| 473 | i2c@7000c700 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 474 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 475 | reg = <0x7000c700 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 476 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 477 | #address-cells = <1>; |
| 478 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 479 | clocks = <&tegra_car TEGRA30_CLK_I2C4>, |
| 480 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 481 | resets = <&tegra_car 103>; |
| 482 | reset-names = "i2c"; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 483 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 484 | dmas = <&apbdma 26>, <&apbdma 26>; |
| 485 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 486 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 487 | }; |
| 488 | |
| 489 | i2c@7000d000 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 490 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 491 | reg = <0x7000d000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 492 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 493 | #address-cells = <1>; |
| 494 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 495 | clocks = <&tegra_car TEGRA30_CLK_I2C5>, |
| 496 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 497 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 498 | resets = <&tegra_car 47>; |
| 499 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 500 | dmas = <&apbdma 24>, <&apbdma 24>; |
| 501 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 502 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 503 | }; |
| 504 | |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 505 | spi@7000d400 { |
| 506 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 507 | reg = <0x7000d400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 508 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 509 | #address-cells = <1>; |
| 510 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 511 | clocks = <&tegra_car TEGRA30_CLK_SBC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 512 | resets = <&tegra_car 41>; |
| 513 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 514 | dmas = <&apbdma 15>, <&apbdma 15>; |
| 515 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 516 | status = "disabled"; |
| 517 | }; |
| 518 | |
| 519 | spi@7000d600 { |
| 520 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 521 | reg = <0x7000d600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 522 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 523 | #address-cells = <1>; |
| 524 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 525 | clocks = <&tegra_car TEGRA30_CLK_SBC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 526 | resets = <&tegra_car 44>; |
| 527 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 528 | dmas = <&apbdma 16>, <&apbdma 16>; |
| 529 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 530 | status = "disabled"; |
| 531 | }; |
| 532 | |
| 533 | spi@7000d800 { |
| 534 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
Laxman Dewangan | 57471c8 | 2013-03-22 12:35:06 -0600 | [diff] [blame] | 535 | reg = <0x7000d800 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 536 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 537 | #address-cells = <1>; |
| 538 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 539 | clocks = <&tegra_car TEGRA30_CLK_SBC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 540 | resets = <&tegra_car 46>; |
| 541 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 542 | dmas = <&apbdma 17>, <&apbdma 17>; |
| 543 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 544 | status = "disabled"; |
| 545 | }; |
| 546 | |
| 547 | spi@7000da00 { |
| 548 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 549 | reg = <0x7000da00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 550 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 551 | #address-cells = <1>; |
| 552 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 553 | clocks = <&tegra_car TEGRA30_CLK_SBC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 554 | resets = <&tegra_car 68>; |
| 555 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 556 | dmas = <&apbdma 18>, <&apbdma 18>; |
| 557 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 558 | status = "disabled"; |
| 559 | }; |
| 560 | |
| 561 | spi@7000dc00 { |
| 562 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 563 | reg = <0x7000dc00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 564 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 565 | #address-cells = <1>; |
| 566 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 567 | clocks = <&tegra_car TEGRA30_CLK_SBC5>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 568 | resets = <&tegra_car 104>; |
| 569 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 570 | dmas = <&apbdma 27>, <&apbdma 27>; |
| 571 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 572 | status = "disabled"; |
| 573 | }; |
| 574 | |
| 575 | spi@7000de00 { |
| 576 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 577 | reg = <0x7000de00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 578 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 579 | #address-cells = <1>; |
| 580 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 581 | clocks = <&tegra_car TEGRA30_CLK_SBC6>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 582 | resets = <&tegra_car 106>; |
| 583 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 584 | dmas = <&apbdma 28>, <&apbdma 28>; |
| 585 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 586 | status = "disabled"; |
| 587 | }; |
| 588 | |
Laxman Dewangan | 699ed4b | 2013-01-11 19:03:03 +0530 | [diff] [blame] | 589 | kbc { |
| 590 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; |
| 591 | reg = <0x7000e200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 592 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 593 | clocks = <&tegra_car TEGRA30_CLK_KBC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 594 | resets = <&tegra_car 36>; |
| 595 | reset-names = "kbc"; |
Laxman Dewangan | 699ed4b | 2013-01-11 19:03:03 +0530 | [diff] [blame] | 596 | status = "disabled"; |
| 597 | }; |
| 598 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 599 | pmc { |
Joseph Lo | 2b84e53 | 2013-02-26 16:27:43 +0000 | [diff] [blame] | 600 | compatible = "nvidia,tegra30-pmc"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 601 | reg = <0x7000e400 0x400>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 602 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 603 | clock-names = "pclk", "clk32k_in"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 604 | }; |
| 605 | |
hdoyu@nvidia.com | a9140aa | 2012-05-16 19:47:44 +0000 | [diff] [blame] | 606 | memory-controller { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 607 | compatible = "nvidia,tegra30-mc"; |
| 608 | reg = <0x7000f000 0x010 |
| 609 | 0x7000f03c 0x1b4 |
| 610 | 0x7000f200 0x028 |
| 611 | 0x7000f284 0x17c>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 612 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 613 | }; |
| 614 | |
Hiroshi Doyu | 3fbf07d | 2013-01-29 10:30:29 +0200 | [diff] [blame] | 615 | iommu { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 616 | compatible = "nvidia,tegra30-smmu"; |
| 617 | reg = <0x7000f010 0x02c |
| 618 | 0x7000f1f0 0x010 |
| 619 | 0x7000f228 0x05c>; |
| 620 | nvidia,#asids = <4>; /* # of ASIDs */ |
| 621 | dma-window = <0 0x40000000>; /* IOVA start & length */ |
| 622 | nvidia,ahb = <&ahb>; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 623 | }; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 624 | |
| 625 | ahub { |
| 626 | compatible = "nvidia,tegra30-ahub"; |
Stephen Warren | 5ff4888 | 2012-05-11 16:26:03 -0600 | [diff] [blame] | 627 | reg = <0x70080000 0x200 |
| 628 | 0x70080200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 629 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 630 | clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame] | 631 | <&tegra_car TEGRA30_CLK_APBIF>; |
| 632 | clock-names = "d_audio", "apbif"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 633 | resets = <&tegra_car 106>, /* d_audio */ |
| 634 | <&tegra_car 107>, /* apbif */ |
| 635 | <&tegra_car 30>, /* i2s0 */ |
| 636 | <&tegra_car 11>, /* i2s1 */ |
| 637 | <&tegra_car 18>, /* i2s2 */ |
| 638 | <&tegra_car 101>, /* i2s3 */ |
| 639 | <&tegra_car 102>, /* i2s4 */ |
| 640 | <&tegra_car 108>, /* dam0 */ |
| 641 | <&tegra_car 109>, /* dam1 */ |
| 642 | <&tegra_car 110>, /* dam2 */ |
| 643 | <&tegra_car 10>; /* spdif */ |
| 644 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 645 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 646 | "spdif"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 647 | dmas = <&apbdma 1>, <&apbdma 1>, |
| 648 | <&apbdma 2>, <&apbdma 2>, |
| 649 | <&apbdma 3>, <&apbdma 3>, |
| 650 | <&apbdma 4>, <&apbdma 4>; |
| 651 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", |
| 652 | "rx3", "tx3"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 653 | ranges; |
| 654 | #address-cells = <1>; |
| 655 | #size-cells = <1>; |
| 656 | |
| 657 | tegra_i2s0: i2s@70080300 { |
| 658 | compatible = "nvidia,tegra30-i2s"; |
| 659 | reg = <0x70080300 0x100>; |
| 660 | nvidia,ahub-cif-ids = <4 4>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 661 | clocks = <&tegra_car TEGRA30_CLK_I2S0>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 662 | resets = <&tegra_car 30>; |
| 663 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 664 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 665 | }; |
| 666 | |
| 667 | tegra_i2s1: i2s@70080400 { |
| 668 | compatible = "nvidia,tegra30-i2s"; |
| 669 | reg = <0x70080400 0x100>; |
| 670 | nvidia,ahub-cif-ids = <5 5>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 671 | clocks = <&tegra_car TEGRA30_CLK_I2S1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 672 | resets = <&tegra_car 11>; |
| 673 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 674 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 675 | }; |
| 676 | |
| 677 | tegra_i2s2: i2s@70080500 { |
| 678 | compatible = "nvidia,tegra30-i2s"; |
| 679 | reg = <0x70080500 0x100>; |
| 680 | nvidia,ahub-cif-ids = <6 6>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 681 | clocks = <&tegra_car TEGRA30_CLK_I2S2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 682 | resets = <&tegra_car 18>; |
| 683 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 684 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 685 | }; |
| 686 | |
| 687 | tegra_i2s3: i2s@70080600 { |
| 688 | compatible = "nvidia,tegra30-i2s"; |
| 689 | reg = <0x70080600 0x100>; |
| 690 | nvidia,ahub-cif-ids = <7 7>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 691 | clocks = <&tegra_car TEGRA30_CLK_I2S3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 692 | resets = <&tegra_car 101>; |
| 693 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 694 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 695 | }; |
| 696 | |
| 697 | tegra_i2s4: i2s@70080700 { |
| 698 | compatible = "nvidia,tegra30-i2s"; |
| 699 | reg = <0x70080700 0x100>; |
| 700 | nvidia,ahub-cif-ids = <8 8>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 701 | clocks = <&tegra_car TEGRA30_CLK_I2S4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 702 | resets = <&tegra_car 102>; |
| 703 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 704 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 705 | }; |
| 706 | }; |
Hiroshi DOYU | 7868a9b | 2012-05-07 09:43:47 +0300 | [diff] [blame] | 707 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 708 | sdhci@78000000 { |
| 709 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 710 | reg = <0x78000000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 711 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 712 | clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 713 | resets = <&tegra_car 14>; |
| 714 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 715 | status = "disabled"; |
Hiroshi DOYU | 7868a9b | 2012-05-07 09:43:47 +0300 | [diff] [blame] | 716 | }; |
hdoyu@nvidia.com | ecf4374 | 2012-05-09 21:42:33 +0000 | [diff] [blame] | 717 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 718 | sdhci@78000200 { |
| 719 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 720 | reg = <0x78000200 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 721 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 722 | clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 723 | resets = <&tegra_car 9>; |
| 724 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 725 | status = "disabled"; |
hdoyu@nvidia.com | ecf4374 | 2012-05-09 21:42:33 +0000 | [diff] [blame] | 726 | }; |
hdoyu@nvidia.com | 54174a3 | 2012-05-09 21:50:21 +0000 | [diff] [blame] | 727 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 728 | sdhci@78000400 { |
| 729 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 730 | reg = <0x78000400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 731 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 732 | clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 733 | resets = <&tegra_car 69>; |
| 734 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 735 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 736 | }; |
| 737 | |
| 738 | sdhci@78000600 { |
| 739 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 740 | reg = <0x78000600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 741 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 742 | clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 743 | resets = <&tegra_car 15>; |
| 744 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 745 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 746 | }; |
| 747 | |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 748 | usb@7d000000 { |
| 749 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 750 | reg = <0x7d000000 0x4000>; |
| 751 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 752 | phy_type = "utmi"; |
| 753 | clocks = <&tegra_car TEGRA30_CLK_USBD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 754 | resets = <&tegra_car 22>; |
| 755 | reset-names = "usb"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 756 | nvidia,needs-double-reset; |
| 757 | nvidia,phy = <&phy1>; |
| 758 | status = "disabled"; |
| 759 | }; |
| 760 | |
| 761 | phy1: usb-phy@7d000000 { |
| 762 | compatible = "nvidia,tegra30-usb-phy"; |
| 763 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; |
| 764 | phy_type = "utmi"; |
| 765 | clocks = <&tegra_car TEGRA30_CLK_USBD>, |
| 766 | <&tegra_car TEGRA30_CLK_PLL_U>, |
| 767 | <&tegra_car TEGRA30_CLK_USBD>; |
| 768 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 769 | nvidia,hssync-start-delay = <9>; |
| 770 | nvidia,idle-wait-delay = <17>; |
| 771 | nvidia,elastic-limit = <16>; |
| 772 | nvidia,term-range-adj = <6>; |
| 773 | nvidia,xcvr-setup = <51>; |
| 774 | nvidia.xcvr-setup-use-fuses; |
| 775 | nvidia,xcvr-lsfslew = <1>; |
| 776 | nvidia,xcvr-lsrslew = <1>; |
| 777 | nvidia,xcvr-hsslew = <32>; |
| 778 | nvidia,hssquelch-level = <2>; |
| 779 | nvidia,hsdiscon-level = <5>; |
| 780 | status = "disabled"; |
| 781 | }; |
| 782 | |
| 783 | usb@7d004000 { |
| 784 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 785 | reg = <0x7d004000 0x4000>; |
| 786 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| 787 | phy_type = "ulpi"; |
| 788 | clocks = <&tegra_car TEGRA30_CLK_USB2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 789 | resets = <&tegra_car 58>; |
| 790 | reset-names = "usb"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 791 | nvidia,phy = <&phy2>; |
| 792 | status = "disabled"; |
| 793 | }; |
| 794 | |
| 795 | phy2: usb-phy@7d004000 { |
| 796 | compatible = "nvidia,tegra30-usb-phy"; |
| 797 | reg = <0x7d004000 0x4000>; |
| 798 | phy_type = "ulpi"; |
| 799 | clocks = <&tegra_car TEGRA30_CLK_USB2>, |
| 800 | <&tegra_car TEGRA30_CLK_PLL_U>, |
| 801 | <&tegra_car TEGRA30_CLK_CDEV2>; |
| 802 | clock-names = "reg", "pll_u", "ulpi-link"; |
| 803 | status = "disabled"; |
| 804 | }; |
| 805 | |
| 806 | usb@7d008000 { |
| 807 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 808 | reg = <0x7d008000 0x4000>; |
| 809 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 810 | phy_type = "utmi"; |
| 811 | clocks = <&tegra_car TEGRA30_CLK_USB3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 812 | resets = <&tegra_car 59>; |
| 813 | reset-names = "usb"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 814 | nvidia,phy = <&phy3>; |
| 815 | status = "disabled"; |
| 816 | }; |
| 817 | |
| 818 | phy3: usb-phy@7d008000 { |
| 819 | compatible = "nvidia,tegra30-usb-phy"; |
| 820 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; |
| 821 | phy_type = "utmi"; |
| 822 | clocks = <&tegra_car TEGRA30_CLK_USB3>, |
| 823 | <&tegra_car TEGRA30_CLK_PLL_U>, |
| 824 | <&tegra_car TEGRA30_CLK_USBD>; |
| 825 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 826 | nvidia,hssync-start-delay = <0>; |
| 827 | nvidia,idle-wait-delay = <17>; |
| 828 | nvidia,elastic-limit = <16>; |
| 829 | nvidia,term-range-adj = <6>; |
| 830 | nvidia,xcvr-setup = <51>; |
| 831 | nvidia.xcvr-setup-use-fuses; |
| 832 | nvidia,xcvr-lsfslew = <2>; |
| 833 | nvidia,xcvr-lsrslew = <2>; |
| 834 | nvidia,xcvr-hsslew = <32>; |
| 835 | nvidia,hssquelch-level = <2>; |
| 836 | nvidia,hsdiscon-level = <5>; |
| 837 | status = "disabled"; |
| 838 | }; |
| 839 | |
Hiroshi Doyu | 7d19a34 | 2013-01-11 15:11:54 +0200 | [diff] [blame] | 840 | cpus { |
| 841 | #address-cells = <1>; |
| 842 | #size-cells = <0>; |
| 843 | |
| 844 | cpu@0 { |
| 845 | device_type = "cpu"; |
| 846 | compatible = "arm,cortex-a9"; |
| 847 | reg = <0>; |
| 848 | }; |
| 849 | |
| 850 | cpu@1 { |
| 851 | device_type = "cpu"; |
| 852 | compatible = "arm,cortex-a9"; |
| 853 | reg = <1>; |
| 854 | }; |
| 855 | |
| 856 | cpu@2 { |
| 857 | device_type = "cpu"; |
| 858 | compatible = "arm,cortex-a9"; |
| 859 | reg = <2>; |
| 860 | }; |
| 861 | |
| 862 | cpu@3 { |
| 863 | device_type = "cpu"; |
| 864 | compatible = "arm,cortex-a9"; |
| 865 | reg = <3>; |
| 866 | }; |
| 867 | }; |
| 868 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 869 | pmu { |
| 870 | compatible = "arm,cortex-a9-pmu"; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 871 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| 872 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| 873 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| 874 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
hdoyu@nvidia.com | 54174a3 | 2012-05-09 21:50:21 +0000 | [diff] [blame] | 875 | }; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 876 | }; |