| Jean PIHET | d7ac4e2 | 2008-08-12 19:07:39 +0100 | [diff] [blame] | 1 | /** |
| 2 | * op_model_v7.h |
| 3 | * ARM v7 (Cortex A8) Event Monitor Driver |
| 4 | * |
| 5 | * Copyright 2008 Jean Pihet <jpihet@mvista.com> |
| 6 | * Copyright 2004 ARM SMP Development Team |
| 7 | * Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> |
| 8 | * Copyright 2000-2004 MontaVista Software Inc |
| 9 | * Copyright 2004 Dave Jiang <dave.jiang@intel.com> |
| 10 | * Copyright 2004 Intel Corporation |
| 11 | * Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> |
| 12 | * Copyright 2004 Oprofile Authors |
| 13 | * |
| 14 | * Read the file COPYING |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License version 2 as |
| 18 | * published by the Free Software Foundation. |
| 19 | */ |
| 20 | #ifndef OP_MODEL_V7_H |
| 21 | #define OP_MODEL_V7_H |
| 22 | |
| 23 | /* |
| 24 | * Per-CPU PMNC: config reg |
| 25 | */ |
| 26 | #define PMNC_E (1 << 0) /* Enable all counters */ |
| 27 | #define PMNC_P (1 << 1) /* Reset all counters */ |
| 28 | #define PMNC_C (1 << 2) /* Cycle counter reset */ |
| 29 | #define PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ |
| 30 | #define PMNC_X (1 << 4) /* Export to ETM */ |
| 31 | #define PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ |
| 32 | #define PMNC_MASK 0x3f /* Mask for writable bits */ |
| 33 | |
| 34 | /* |
| 35 | * Available counters |
| 36 | */ |
| 37 | #define CCNT 0 |
| 38 | #define CNT0 1 |
| 39 | #define CNT1 2 |
| 40 | #define CNT2 3 |
| 41 | #define CNT3 4 |
| 42 | #define CNTMAX 5 |
| 43 | |
| 44 | #define CPU_COUNTER(cpu, counter) ((cpu) * CNTMAX + (counter)) |
| 45 | |
| 46 | /* |
| 47 | * CNTENS: counters enable reg |
| 48 | */ |
| 49 | #define CNTENS_P0 (1 << 0) |
| 50 | #define CNTENS_P1 (1 << 1) |
| 51 | #define CNTENS_P2 (1 << 2) |
| 52 | #define CNTENS_P3 (1 << 3) |
| 53 | #define CNTENS_C (1 << 31) |
| 54 | #define CNTENS_MASK 0x8000000f /* Mask for writable bits */ |
| 55 | |
| 56 | /* |
| 57 | * CNTENC: counters disable reg |
| 58 | */ |
| 59 | #define CNTENC_P0 (1 << 0) |
| 60 | #define CNTENC_P1 (1 << 1) |
| 61 | #define CNTENC_P2 (1 << 2) |
| 62 | #define CNTENC_P3 (1 << 3) |
| 63 | #define CNTENC_C (1 << 31) |
| 64 | #define CNTENC_MASK 0x8000000f /* Mask for writable bits */ |
| 65 | |
| 66 | /* |
| 67 | * INTENS: counters overflow interrupt enable reg |
| 68 | */ |
| 69 | #define INTENS_P0 (1 << 0) |
| 70 | #define INTENS_P1 (1 << 1) |
| 71 | #define INTENS_P2 (1 << 2) |
| 72 | #define INTENS_P3 (1 << 3) |
| 73 | #define INTENS_C (1 << 31) |
| 74 | #define INTENS_MASK 0x8000000f /* Mask for writable bits */ |
| 75 | |
| 76 | /* |
| 77 | * EVTSEL: Event selection reg |
| 78 | */ |
| 79 | #define EVTSEL_MASK 0x7f /* Mask for writable bits */ |
| 80 | |
| 81 | /* |
| 82 | * SELECT: Counter selection reg |
| 83 | */ |
| 84 | #define SELECT_MASK 0x1f /* Mask for writable bits */ |
| 85 | |
| 86 | /* |
| 87 | * FLAG: counters overflow flag status reg |
| 88 | */ |
| 89 | #define FLAG_P0 (1 << 0) |
| 90 | #define FLAG_P1 (1 << 1) |
| 91 | #define FLAG_P2 (1 << 2) |
| 92 | #define FLAG_P3 (1 << 3) |
| 93 | #define FLAG_C (1 << 31) |
| 94 | #define FLAG_MASK 0x8000000f /* Mask for writable bits */ |
| 95 | |
| 96 | |
| 97 | int armv7_setup_pmu(void); |
| 98 | int armv7_start_pmu(void); |
| 99 | int armv7_stop_pmu(void); |
| 100 | int armv7_request_interrupts(int *, int); |
| 101 | void armv7_release_interrupts(int *, int); |
| 102 | |
| 103 | #endif |