blob: 097f24d8bceb9ec2ad0d1440430c302d7f0a4a35 [file] [log] [blame]
David Brownella30d46c2008-10-20 23:46:28 +02001/*
2 * twl4030-irq.c - TWL4030/TPS659x0 irq support
3 *
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
5 *
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
8 *
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
11 *
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 */
29
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/irq.h>
33#include <linux/kthread.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
David Brownella30d46c2008-10-20 23:46:28 +020035
Santosh Shilimkarb07682b2009-12-13 20:05:51 +010036#include <linux/i2c/twl.h>
David Brownella30d46c2008-10-20 23:46:28 +020037
38
39/*
40 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
41 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
42 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
43 * SIH modules are more traditional IRQ components, which support per-IRQ
44 * enable/disable and trigger controls; they do most of the work.
45 *
46 * These chips are designed to support IRQ handling from two different
47 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
48 * and mask registers in the PIH and SIH modules.
49 *
50 * We set up IRQs starting at a platform-specified base, always starting
51 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
52 * base + 0 .. base + 7 PIH
53 * base + 8 .. base + 15 SIH for PWR_INT
54 * base + 16 .. base + 33 SIH for GPIO
55 */
56
57/* PIH register offsets */
58#define REG_PIH_ISR_P1 0x01
59#define REG_PIH_ISR_P2 0x02
60#define REG_PIH_SIR 0x03 /* for testing */
61
62
63/* Linux could (eventually) use either IRQ line */
64static int irq_line;
65
66struct sih {
67 char name[8];
68 u8 module; /* module id */
69 u8 control_offset; /* for SIH_CTRL */
70 bool set_cor;
71
72 u8 bits; /* valid in isr/imr */
73 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
74
75 u8 edr_offset;
76 u8 bytes_edr; /* bytelen of EDR */
77
Ilkka Koskinen1920a612009-11-10 17:26:15 +020078 u8 irq_lines; /* number of supported irq lines */
79
David Brownella30d46c2008-10-20 23:46:28 +020080 /* SIR ignored -- set interrupt, for testing only */
81 struct irq_data {
82 u8 isr_offset;
83 u8 imr_offset;
84 } mask[2];
85 /* + 2 bytes padding */
86};
87
Ilkka Koskinen1920a612009-11-10 17:26:15 +020088static const struct sih *sih_modules;
89static int nr_sih_modules;
90
David Brownella30d46c2008-10-20 23:46:28 +020091#define SIH_INITIALIZER(modname, nbits) \
92 .module = TWL4030_MODULE_ ## modname, \
93 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
94 .bits = nbits, \
95 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
96 .edr_offset = TWL4030_ ## modname ## _EDR, \
97 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
Ilkka Koskinen1920a612009-11-10 17:26:15 +020098 .irq_lines = 2, \
David Brownella30d46c2008-10-20 23:46:28 +020099 .mask = { { \
100 .isr_offset = TWL4030_ ## modname ## _ISR1, \
101 .imr_offset = TWL4030_ ## modname ## _IMR1, \
102 }, \
103 { \
104 .isr_offset = TWL4030_ ## modname ## _ISR2, \
105 .imr_offset = TWL4030_ ## modname ## _IMR2, \
106 }, },
107
108/* register naming policies are inconsistent ... */
109#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
110#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
111#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
112
113
114/* Order in this table matches order in PIH_ISR. That is,
115 * BIT(n) in PIH_ISR is sih_modules[n].
116 */
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200117/* sih_modules_twl4030 is used both in twl4030 and twl5030 */
118static const struct sih sih_modules_twl4030[6] = {
David Brownella30d46c2008-10-20 23:46:28 +0200119 [0] = {
120 .name = "gpio",
121 .module = TWL4030_MODULE_GPIO,
122 .control_offset = REG_GPIO_SIH_CTRL,
123 .set_cor = true,
124 .bits = TWL4030_GPIO_MAX,
125 .bytes_ixr = 3,
126 /* Note: *all* of these IRQs default to no-trigger */
127 .edr_offset = REG_GPIO_EDR1,
128 .bytes_edr = 5,
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200129 .irq_lines = 2,
David Brownella30d46c2008-10-20 23:46:28 +0200130 .mask = { {
131 .isr_offset = REG_GPIO_ISR1A,
132 .imr_offset = REG_GPIO_IMR1A,
133 }, {
134 .isr_offset = REG_GPIO_ISR1B,
135 .imr_offset = REG_GPIO_IMR1B,
136 }, },
137 },
138 [1] = {
139 .name = "keypad",
140 .set_cor = true,
141 SIH_INITIALIZER(KEYPAD_KEYP, 4)
142 },
143 [2] = {
144 .name = "bci",
145 .module = TWL4030_MODULE_INTERRUPTS,
146 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
147 .bits = 12,
148 .bytes_ixr = 2,
149 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
150 /* Note: most of these IRQs default to no-trigger */
151 .bytes_edr = 3,
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200152 .irq_lines = 2,
David Brownella30d46c2008-10-20 23:46:28 +0200153 .mask = { {
154 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
155 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
156 }, {
157 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
158 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
159 }, },
160 },
161 [3] = {
162 .name = "madc",
163 SIH_INITIALIZER(MADC, 4)
164 },
165 [4] = {
166 /* USB doesn't use the same SIH organization */
167 .name = "usb",
168 },
169 [5] = {
170 .name = "power",
171 .set_cor = true,
172 SIH_INITIALIZER(INT_PWR, 8)
173 },
174 /* there are no SIH modules #6 or #7 ... */
175};
176
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200177static const struct sih sih_modules_twl5031[8] = {
178 [0] = {
179 .name = "gpio",
180 .module = TWL4030_MODULE_GPIO,
181 .control_offset = REG_GPIO_SIH_CTRL,
182 .set_cor = true,
183 .bits = TWL4030_GPIO_MAX,
184 .bytes_ixr = 3,
185 /* Note: *all* of these IRQs default to no-trigger */
186 .edr_offset = REG_GPIO_EDR1,
187 .bytes_edr = 5,
188 .irq_lines = 2,
189 .mask = { {
190 .isr_offset = REG_GPIO_ISR1A,
191 .imr_offset = REG_GPIO_IMR1A,
192 }, {
193 .isr_offset = REG_GPIO_ISR1B,
194 .imr_offset = REG_GPIO_IMR1B,
195 }, },
196 },
197 [1] = {
198 .name = "keypad",
199 .set_cor = true,
200 SIH_INITIALIZER(KEYPAD_KEYP, 4)
201 },
202 [2] = {
203 .name = "bci",
204 .module = TWL5031_MODULE_INTERRUPTS,
205 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
206 .bits = 7,
207 .bytes_ixr = 1,
208 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
209 /* Note: most of these IRQs default to no-trigger */
210 .bytes_edr = 2,
211 .irq_lines = 2,
212 .mask = { {
213 .isr_offset = TWL5031_INTERRUPTS_BCIISR1,
214 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
215 }, {
216 .isr_offset = TWL5031_INTERRUPTS_BCIISR2,
217 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
218 }, },
219 },
220 [3] = {
221 .name = "madc",
222 SIH_INITIALIZER(MADC, 4)
223 },
224 [4] = {
225 /* USB doesn't use the same SIH organization */
226 .name = "usb",
227 },
228 [5] = {
229 .name = "power",
230 .set_cor = true,
231 SIH_INITIALIZER(INT_PWR, 8)
232 },
233 [6] = {
234 /*
Ilkka Koskinen191211f2010-05-20 13:04:20 +0300235 * ECI/DBI doesn't use the same SIH organization.
236 * For example, it supports only one interrupt output line.
237 * That is, the interrupts are seen on both INT1 and INT2 lines.
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200238 */
Ilkka Koskinen191211f2010-05-20 13:04:20 +0300239 .name = "eci_dbi",
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200240 .module = TWL5031_MODULE_ACCESSORY,
241 .bits = 9,
242 .bytes_ixr = 2,
243 .irq_lines = 1,
244 .mask = { {
245 .isr_offset = TWL5031_ACIIDR_LSB,
246 .imr_offset = TWL5031_ACIIMR_LSB,
247 }, },
248
249 },
250 [7] = {
Ilkka Koskinen191211f2010-05-20 13:04:20 +0300251 /* Audio accessory */
252 .name = "audio",
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200253 .module = TWL5031_MODULE_ACCESSORY,
254 .control_offset = TWL5031_ACCSIHCTRL,
255 .bits = 2,
256 .bytes_ixr = 1,
257 .edr_offset = TWL5031_ACCEDR1,
258 /* Note: most of these IRQs default to no-trigger */
259 .bytes_edr = 1,
260 .irq_lines = 2,
261 .mask = { {
262 .isr_offset = TWL5031_ACCISR1,
263 .imr_offset = TWL5031_ACCIMR1,
264 }, {
265 .isr_offset = TWL5031_ACCISR2,
266 .imr_offset = TWL5031_ACCIMR2,
267 }, },
268 },
269};
270
David Brownella30d46c2008-10-20 23:46:28 +0200271#undef TWL4030_MODULE_KEYPAD_KEYP
272#undef TWL4030_MODULE_INT_PWR
273#undef TWL4030_INT_PWR_EDR
274
275/*----------------------------------------------------------------------*/
276
277static unsigned twl4030_irq_base;
278
279static struct completion irq_event;
280
281/*
282 * This thread processes interrupts reported by the Primary Interrupt Handler.
283 */
284static int twl4030_irq_thread(void *data)
285{
286 long irq = (long)data;
David Brownella30d46c2008-10-20 23:46:28 +0200287 static unsigned i2c_errors;
Tobias Klauser3446d4b2009-02-17 10:11:42 +0100288 static const unsigned max_i2c_errors = 100;
David Brownella30d46c2008-10-20 23:46:28 +0200289
Samuel Ortiz94964f92008-12-18 11:38:02 +0100290
David Brownella30d46c2008-10-20 23:46:28 +0200291 current->flags |= PF_NOFREEZE;
292
293 while (!kthread_should_stop()) {
294 int ret;
295 int module_irq;
296 u8 pih_isr;
297
298 /* Wait for IRQ, then read PIH irq status (also blocking) */
299 wait_for_completion_interruptible(&irq_event);
300
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100301 ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr,
David Brownella30d46c2008-10-20 23:46:28 +0200302 REG_PIH_ISR_P1);
303 if (ret) {
304 pr_warning("twl4030: I2C error %d reading PIH ISR\n",
305 ret);
306 if (++i2c_errors >= max_i2c_errors) {
307 printk(KERN_ERR "Maximum I2C error count"
308 " exceeded. Terminating %s.\n",
309 __func__);
310 break;
311 }
312 complete(&irq_event);
313 continue;
314 }
315
316 /* these handlers deal with the relevant SIH irq status */
317 local_irq_disable();
318 for (module_irq = twl4030_irq_base;
319 pih_isr;
320 pih_isr >>= 1, module_irq++) {
321 if (pih_isr & 0x1) {
Samuel Ortiz94964f92008-12-18 11:38:02 +0100322 struct irq_desc *d = irq_to_desc(module_irq);
323
324 if (!d) {
325 pr_err("twl4030: Invalid SIH IRQ: %d\n",
326 module_irq);
327 return -EINVAL;
328 }
David Brownella30d46c2008-10-20 23:46:28 +0200329
330 /* These can't be masked ... always warn
331 * if we get any surprises.
332 */
333 if (d->status & IRQ_DISABLED)
334 note_interrupt(module_irq, d,
335 IRQ_NONE);
336 else
337 d->handle_irq(module_irq, d);
338 }
339 }
340 local_irq_enable();
341
Russell King1cef8e42009-07-27 11:30:48 +0530342 enable_irq(irq);
David Brownella30d46c2008-10-20 23:46:28 +0200343 }
344
345 return 0;
346}
347
348/*
349 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
350 * This is a chained interrupt, so there is no desc->action method for it.
351 * Now we need to query the interrupt controller in the twl4030 to determine
352 * which module is generating the interrupt request. However, we can't do i2c
353 * transactions in interrupt context, so we must defer that work to a kernel
354 * thread. All we do here is acknowledge and mask the interrupt and wakeup
355 * the kernel thread.
356 */
Russell King1cef8e42009-07-27 11:30:48 +0530357static irqreturn_t handle_twl4030_pih(int irq, void *devid)
David Brownella30d46c2008-10-20 23:46:28 +0200358{
359 /* Acknowledge, clear *AND* mask the interrupt... */
Russell King1cef8e42009-07-27 11:30:48 +0530360 disable_irq_nosync(irq);
361 complete(devid);
362 return IRQ_HANDLED;
David Brownella30d46c2008-10-20 23:46:28 +0200363}
David Brownella30d46c2008-10-20 23:46:28 +0200364/*----------------------------------------------------------------------*/
365
366/*
367 * twl4030_init_sih_modules() ... start from a known state where no
368 * IRQs will be coming in, and where we can quickly enable them then
369 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
370 *
371 * NOTE: we don't touch EDR registers here; they stay with hardware
372 * defaults or whatever the last value was. Note that when both EDR
373 * bits for an IRQ are clear, that's as if its IMR bit is set...
374 */
375static int twl4030_init_sih_modules(unsigned line)
376{
377 const struct sih *sih;
378 u8 buf[4];
379 int i;
380 int status;
381
382 /* line 0 == int1_n signal; line 1 == int2_n signal */
383 if (line > 1)
384 return -EINVAL;
385
386 irq_line = line;
387
388 /* disable all interrupts on our line */
389 memset(buf, 0xff, sizeof buf);
390 sih = sih_modules;
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200391 for (i = 0; i < nr_sih_modules; i++, sih++) {
David Brownella30d46c2008-10-20 23:46:28 +0200392
393 /* skip USB -- it's funky */
394 if (!sih->bytes_ixr)
395 continue;
396
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200397 /* Not all the SIH modules support multiple interrupt lines */
398 if (sih->irq_lines <= line)
399 continue;
400
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100401 status = twl_i2c_write(sih->module, buf,
David Brownella30d46c2008-10-20 23:46:28 +0200402 sih->mask[line].imr_offset, sih->bytes_ixr);
403 if (status < 0)
404 pr_err("twl4030: err %d initializing %s %s\n",
405 status, sih->name, "IMR");
406
407 /* Maybe disable "exclusive" mode; buffer second pending irq;
408 * set Clear-On-Read (COR) bit.
409 *
410 * NOTE that sometimes COR polarity is documented as being
411 * inverted: for MADC and BCI, COR=1 means "clear on write".
412 * And for PWR_INT it's not documented...
413 */
414 if (sih->set_cor) {
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100415 status = twl_i2c_write_u8(sih->module,
David Brownella30d46c2008-10-20 23:46:28 +0200416 TWL4030_SIH_CTRL_COR_MASK,
417 sih->control_offset);
418 if (status < 0)
419 pr_err("twl4030: err %d initializing %s %s\n",
420 status, sih->name, "SIH_CTRL");
421 }
422 }
423
424 sih = sih_modules;
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200425 for (i = 0; i < nr_sih_modules; i++, sih++) {
David Brownella30d46c2008-10-20 23:46:28 +0200426 u8 rxbuf[4];
427 int j;
428
429 /* skip USB */
430 if (!sih->bytes_ixr)
431 continue;
432
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200433 /* Not all the SIH modules support multiple interrupt lines */
434 if (sih->irq_lines <= line)
435 continue;
436
David Brownella30d46c2008-10-20 23:46:28 +0200437 /* Clear pending interrupt status. Either the read was
438 * enough, or we need to write those bits. Repeat, in
439 * case an IRQ is pending (PENDDIS=0) ... that's not
440 * uncommon with PWR_INT.PWRON.
441 */
442 for (j = 0; j < 2; j++) {
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100443 status = twl_i2c_read(sih->module, rxbuf,
David Brownella30d46c2008-10-20 23:46:28 +0200444 sih->mask[line].isr_offset, sih->bytes_ixr);
445 if (status < 0)
446 pr_err("twl4030: err %d initializing %s %s\n",
447 status, sih->name, "ISR");
448
449 if (!sih->set_cor)
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100450 status = twl_i2c_write(sih->module, buf,
David Brownella30d46c2008-10-20 23:46:28 +0200451 sih->mask[line].isr_offset,
452 sih->bytes_ixr);
453 /* else COR=1 means read sufficed.
454 * (for most SIH modules...)
455 */
456 }
457 }
458
459 return 0;
460}
461
462static inline void activate_irq(int irq)
463{
464#ifdef CONFIG_ARM
465 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
466 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
467 */
468 set_irq_flags(irq, IRQF_VALID);
469#else
470 /* same effect on other architectures */
471 set_irq_noprobe(irq);
472#endif
473}
474
475/*----------------------------------------------------------------------*/
476
477static DEFINE_SPINLOCK(sih_agent_lock);
478
479static struct workqueue_struct *wq;
480
481struct sih_agent {
482 int irq_base;
483 const struct sih *sih;
484
485 u32 imr;
486 bool imr_change_pending;
487 struct work_struct mask_work;
488
489 u32 edge_change;
490 struct work_struct edge_work;
491};
492
493static void twl4030_sih_do_mask(struct work_struct *work)
494{
495 struct sih_agent *agent;
496 const struct sih *sih;
497 union {
498 u8 bytes[4];
499 u32 word;
500 } imr;
501 int status;
502
503 agent = container_of(work, struct sih_agent, mask_work);
504
505 /* see what work we have */
506 spin_lock_irq(&sih_agent_lock);
507 if (agent->imr_change_pending) {
508 sih = agent->sih;
509 /* byte[0] gets overwritten as we write ... */
510 imr.word = cpu_to_le32(agent->imr << 8);
511 agent->imr_change_pending = false;
512 } else
513 sih = NULL;
514 spin_unlock_irq(&sih_agent_lock);
515 if (!sih)
516 return;
517
518 /* write the whole mask ... simpler than subsetting it */
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100519 status = twl_i2c_write(sih->module, imr.bytes,
David Brownella30d46c2008-10-20 23:46:28 +0200520 sih->mask[irq_line].imr_offset, sih->bytes_ixr);
521 if (status)
522 pr_err("twl4030: %s, %s --> %d\n", __func__,
523 "write", status);
524}
525
526static void twl4030_sih_do_edge(struct work_struct *work)
527{
528 struct sih_agent *agent;
529 const struct sih *sih;
530 u8 bytes[6];
531 u32 edge_change;
532 int status;
533
534 agent = container_of(work, struct sih_agent, edge_work);
535
536 /* see what work we have */
537 spin_lock_irq(&sih_agent_lock);
538 edge_change = agent->edge_change;
Joe Perchesdf10d642009-06-28 09:26:30 -0700539 agent->edge_change = 0;
David Brownella30d46c2008-10-20 23:46:28 +0200540 sih = edge_change ? agent->sih : NULL;
541 spin_unlock_irq(&sih_agent_lock);
542 if (!sih)
543 return;
544
545 /* Read, reserving first byte for write scratch. Yes, this
546 * could be cached for some speedup ... but be careful about
547 * any processor on the other IRQ line, EDR registers are
548 * shared.
549 */
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100550 status = twl_i2c_read(sih->module, bytes + 1,
David Brownella30d46c2008-10-20 23:46:28 +0200551 sih->edr_offset, sih->bytes_edr);
552 if (status) {
553 pr_err("twl4030: %s, %s --> %d\n", __func__,
554 "read", status);
555 return;
556 }
557
558 /* Modify only the bits we know must change */
559 while (edge_change) {
560 int i = fls(edge_change) - 1;
Samuel Ortiz94964f92008-12-18 11:38:02 +0100561 struct irq_desc *d = irq_to_desc(i + agent->irq_base);
David Brownella30d46c2008-10-20 23:46:28 +0200562 int byte = 1 + (i >> 2);
563 int off = (i & 0x3) * 2;
564
Samuel Ortiz94964f92008-12-18 11:38:02 +0100565 if (!d) {
566 pr_err("twl4030: Invalid IRQ: %d\n",
567 i + agent->irq_base);
568 return;
569 }
570
David Brownella30d46c2008-10-20 23:46:28 +0200571 bytes[byte] &= ~(0x03 << off);
572
Linus Torvaldscd6e1252009-12-31 17:26:05 -0800573 raw_spin_lock_irq(&d->lock);
David Brownella30d46c2008-10-20 23:46:28 +0200574 if (d->status & IRQ_TYPE_EDGE_RISING)
575 bytes[byte] |= BIT(off + 1);
576 if (d->status & IRQ_TYPE_EDGE_FALLING)
577 bytes[byte] |= BIT(off + 0);
Linus Torvaldscd6e1252009-12-31 17:26:05 -0800578 raw_spin_unlock_irq(&d->lock);
David Brownella30d46c2008-10-20 23:46:28 +0200579
580 edge_change &= ~BIT(i);
581 }
582
583 /* Write */
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100584 status = twl_i2c_write(sih->module, bytes,
David Brownella30d46c2008-10-20 23:46:28 +0200585 sih->edr_offset, sih->bytes_edr);
586 if (status)
587 pr_err("twl4030: %s, %s --> %d\n", __func__,
588 "write", status);
589}
590
591/*----------------------------------------------------------------------*/
592
593/*
594 * All irq_chip methods get issued from code holding irq_desc[irq].lock,
595 * which can't perform the underlying I2C operations (because they sleep).
596 * So we must hand them off to a thread (workqueue) and cope with asynch
597 * completion, potentially including some re-ordering, of these requests.
598 */
599
600static void twl4030_sih_mask(unsigned irq)
601{
602 struct sih_agent *sih = get_irq_chip_data(irq);
603 unsigned long flags;
604
605 spin_lock_irqsave(&sih_agent_lock, flags);
606 sih->imr |= BIT(irq - sih->irq_base);
607 sih->imr_change_pending = true;
608 queue_work(wq, &sih->mask_work);
609 spin_unlock_irqrestore(&sih_agent_lock, flags);
610}
611
612static void twl4030_sih_unmask(unsigned irq)
613{
614 struct sih_agent *sih = get_irq_chip_data(irq);
615 unsigned long flags;
616
617 spin_lock_irqsave(&sih_agent_lock, flags);
618 sih->imr &= ~BIT(irq - sih->irq_base);
619 sih->imr_change_pending = true;
620 queue_work(wq, &sih->mask_work);
621 spin_unlock_irqrestore(&sih_agent_lock, flags);
622}
623
624static int twl4030_sih_set_type(unsigned irq, unsigned trigger)
625{
626 struct sih_agent *sih = get_irq_chip_data(irq);
Samuel Ortiz94964f92008-12-18 11:38:02 +0100627 struct irq_desc *desc = irq_to_desc(irq);
David Brownella30d46c2008-10-20 23:46:28 +0200628 unsigned long flags;
629
Samuel Ortiz94964f92008-12-18 11:38:02 +0100630 if (!desc) {
631 pr_err("twl4030: Invalid IRQ: %d\n", irq);
632 return -EINVAL;
633 }
634
David Brownella30d46c2008-10-20 23:46:28 +0200635 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
636 return -EINVAL;
637
638 spin_lock_irqsave(&sih_agent_lock, flags);
639 if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) {
640 desc->status &= ~IRQ_TYPE_SENSE_MASK;
641 desc->status |= trigger;
642 sih->edge_change |= BIT(irq - sih->irq_base);
643 queue_work(wq, &sih->edge_work);
644 }
645 spin_unlock_irqrestore(&sih_agent_lock, flags);
646 return 0;
647}
648
649static struct irq_chip twl4030_sih_irq_chip = {
650 .name = "twl4030",
651 .mask = twl4030_sih_mask,
652 .unmask = twl4030_sih_unmask,
653 .set_type = twl4030_sih_set_type,
654};
655
656/*----------------------------------------------------------------------*/
657
658static inline int sih_read_isr(const struct sih *sih)
659{
660 int status;
661 union {
662 u8 bytes[4];
663 u32 word;
664 } isr;
665
666 /* FIXME need retry-on-error ... */
667
668 isr.word = 0;
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100669 status = twl_i2c_read(sih->module, isr.bytes,
David Brownella30d46c2008-10-20 23:46:28 +0200670 sih->mask[irq_line].isr_offset, sih->bytes_ixr);
671
672 return (status < 0) ? status : le32_to_cpu(isr.word);
673}
674
675/*
676 * Generic handler for SIH interrupts ... we "know" this is called
677 * in task context, with IRQs enabled.
678 */
679static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc)
680{
681 struct sih_agent *agent = get_irq_data(irq);
682 const struct sih *sih = agent->sih;
683 int isr;
684
685 /* reading ISR acks the IRQs, using clear-on-read mode */
686 local_irq_enable();
687 isr = sih_read_isr(sih);
688 local_irq_disable();
689
690 if (isr < 0) {
691 pr_err("twl4030: %s SIH, read ISR error %d\n",
692 sih->name, isr);
693 /* REVISIT: recover; eventually mask it all, etc */
694 return;
695 }
696
697 while (isr) {
698 irq = fls(isr);
699 irq--;
700 isr &= ~BIT(irq);
701
702 if (irq < sih->bits)
703 generic_handle_irq(agent->irq_base + irq);
704 else
705 pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
706 sih->name, irq);
707 }
708}
709
710static unsigned twl4030_irq_next;
711
712/* returns the first IRQ used by this SIH bank,
713 * or negative errno
714 */
715int twl4030_sih_setup(int module)
716{
717 int sih_mod;
718 const struct sih *sih = NULL;
719 struct sih_agent *agent;
720 int i, irq;
721 int status = -EINVAL;
722 unsigned irq_base = twl4030_irq_next;
723
724 /* only support modules with standard clear-on-read for now */
725 for (sih_mod = 0, sih = sih_modules;
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200726 sih_mod < nr_sih_modules;
David Brownella30d46c2008-10-20 23:46:28 +0200727 sih_mod++, sih++) {
728 if (sih->module == module && sih->set_cor) {
729 if (!WARN((irq_base + sih->bits) > NR_IRQS,
730 "irq %d for %s too big\n",
731 irq_base + sih->bits,
732 sih->name))
733 status = 0;
734 break;
735 }
736 }
737 if (status < 0)
738 return status;
739
740 agent = kzalloc(sizeof *agent, GFP_KERNEL);
741 if (!agent)
742 return -ENOMEM;
743
744 status = 0;
745
746 agent->irq_base = irq_base;
747 agent->sih = sih;
748 agent->imr = ~0;
749 INIT_WORK(&agent->mask_work, twl4030_sih_do_mask);
750 INIT_WORK(&agent->edge_work, twl4030_sih_do_edge);
751
752 for (i = 0; i < sih->bits; i++) {
753 irq = irq_base + i;
754
755 set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip,
756 handle_edge_irq);
757 set_irq_chip_data(irq, agent);
758 activate_irq(irq);
759 }
760
761 status = irq_base;
762 twl4030_irq_next += i;
763
764 /* replace generic PIH handler (handle_simple_irq) */
765 irq = sih_mod + twl4030_irq_base;
766 set_irq_data(irq, agent);
767 set_irq_chained_handler(irq, handle_twl4030_sih);
768
769 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
770 irq, irq_base, twl4030_irq_next - 1);
771
772 return status;
773}
774
775/* FIXME need a call to reverse twl4030_sih_setup() ... */
776
777
778/*----------------------------------------------------------------------*/
779
780/* FIXME pass in which interrupt line we'll use ... */
781#define twl_irq_line 0
782
Balaji T Ke8deb282009-12-14 00:25:31 +0100783int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
David Brownella30d46c2008-10-20 23:46:28 +0200784{
785 static struct irq_chip twl4030_irq_chip;
786
787 int status;
788 int i;
789 struct task_struct *task;
790
791 /*
792 * Mask and clear all TWL4030 interrupts since initially we do
793 * not have any TWL4030 module interrupt handlers present
794 */
795 status = twl4030_init_sih_modules(twl_irq_line);
796 if (status < 0)
797 return status;
798
799 wq = create_singlethread_workqueue("twl4030-irqchip");
800 if (!wq) {
801 pr_err("twl4030: workqueue FAIL\n");
802 return -ESRCH;
803 }
804
805 twl4030_irq_base = irq_base;
806
807 /* install an irq handler for each of the SIH modules;
808 * clone dummy irq_chip since PIH can't *do* anything
809 */
810 twl4030_irq_chip = dummy_irq_chip;
811 twl4030_irq_chip.name = "twl4030";
812
813 twl4030_sih_irq_chip.ack = dummy_irq_chip.ack;
814
815 for (i = irq_base; i < irq_end; i++) {
816 set_irq_chip_and_handler(i, &twl4030_irq_chip,
817 handle_simple_irq);
818 activate_irq(i);
819 }
820 twl4030_irq_next = i;
821 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
822 irq_num, irq_base, twl4030_irq_next - 1);
823
824 /* ... and the PWR_INT module ... */
825 status = twl4030_sih_setup(TWL4030_MODULE_INT);
826 if (status < 0) {
827 pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
828 goto fail;
829 }
830
831 /* install an irq handler to demultiplex the TWL4030 interrupt */
Russell King1cef8e42009-07-27 11:30:48 +0530832
833
834 init_completion(&irq_event);
835
836 status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED,
837 "TWL4030-PIH", &irq_event);
838 if (status < 0) {
839 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
840 goto fail_rqirq;
David Brownella30d46c2008-10-20 23:46:28 +0200841 }
842
Alan Cox89f5f9f2009-11-17 15:48:47 +0000843 task = kthread_run(twl4030_irq_thread, (void *)(long)irq_num,
844 "twl4030-irq");
Russell King1cef8e42009-07-27 11:30:48 +0530845 if (IS_ERR(task)) {
846 pr_err("twl4030: could not create irq %d thread!\n", irq_num);
847 status = PTR_ERR(task);
848 goto fail_kthread;
849 }
David Brownella30d46c2008-10-20 23:46:28 +0200850 return status;
Russell King1cef8e42009-07-27 11:30:48 +0530851fail_kthread:
852 free_irq(irq_num, &irq_event);
853fail_rqirq:
854 /* clean up twl4030_sih_setup */
David Brownella30d46c2008-10-20 23:46:28 +0200855fail:
856 for (i = irq_base; i < irq_end; i++)
857 set_irq_chip_and_handler(i, NULL, NULL);
858 destroy_workqueue(wq);
859 wq = NULL;
860 return status;
861}
862
Balaji T Ke8deb282009-12-14 00:25:31 +0100863int twl4030_exit_irq(void)
David Brownella30d46c2008-10-20 23:46:28 +0200864{
865 /* FIXME undo twl_init_irq() */
866 if (twl4030_irq_base) {
867 pr_err("twl4030: can't yet clean up IRQs?\n");
868 return -ENOSYS;
869 }
870 return 0;
871}
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200872
Balaji T Ke8deb282009-12-14 00:25:31 +0100873int twl4030_init_chip_irq(const char *chip)
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200874{
875 if (!strcmp(chip, "twl5031")) {
876 sih_modules = sih_modules_twl5031;
877 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
878 } else {
879 sih_modules = sih_modules_twl4030;
880 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
881 }
882
883 return 0;
884}