Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include "skeleton64.dtsi" |
| 14 | #include <dt-bindings/clock/msm-clocks-8909.h> |
| 15 | #include <dt-bindings/clock/msm-clocks-a7.h> |
| 16 | |
| 17 | / { |
| 18 | model = "Qualcomm Technologies, Inc. MSM8909"; |
| 19 | compatible = "qcom,msm8909"; |
| 20 | qcom,msm-id = <245 0>, |
| 21 | <258 0>, |
| 22 | <265 0>, |
| 23 | <275 0>; |
Raja Mallik | 3e4c958 | 2018-04-18 10:59:14 +0530 | [diff] [blame] | 24 | interrupt-parent = <&wakegic>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 25 | |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 26 | aliases { |
| 27 | /* smdtty devices */ |
| 28 | smd1 = &smdtty_apps_fm; |
| 29 | smd2 = &smdtty_apps_riva_bt_acl; |
| 30 | smd3 = &smdtty_apps_riva_bt_cmd; |
| 31 | smd5 = &smdtty_apps_riva_ant_cmd; |
| 32 | smd6 = &smdtty_apps_riva_ant_data; |
| 33 | smd7 = &smdtty_data1; |
| 34 | smd8 = &smdtty_data4; |
| 35 | smd11 = &smdtty_data11; |
| 36 | smd21 = &smdtty_data21; |
| 37 | smd36 = &smdtty_loopback; |
| 38 | |
| 39 | sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ |
| 40 | sdhc2 = &sdhc_2; /* SDC2 SD card slot */ |
| 41 | spi0 = &spi_0; /* SPI0 controller device */ |
| 42 | spi2 = &spi_2; |
| 43 | spi4 = &spi_4; |
| 44 | i2c5 = &i2c_5; /* I2c5 cntroller device */ |
| 45 | i2c3 = &i2c_3; /* I2C3 controller */ |
| 46 | i2c1 = &i2c_1; /* I2C1 controller */ |
| 47 | i2c2 = &i2c_2; /* I2C2 NFC qup2 device */ |
| 48 | i2c4 = &i2c_4; /* I2C4 controller device */ |
| 49 | qpic_nand1 = &qnand_1; /* qpic nand controller */ |
| 50 | }; |
| 51 | |
| 52 | cpus { |
| 53 | #address-cells = <1>; |
| 54 | #size-cells = <0>; |
| 55 | |
| 56 | cpu-map { |
| 57 | cluster0 { |
| 58 | core0 { |
| 59 | cpu = <&CPU0>; |
| 60 | }; |
| 61 | core1 { |
| 62 | cpu = <&CPU1>; |
| 63 | }; |
| 64 | core2 { |
| 65 | cpu = <&CPU2>; |
| 66 | }; |
| 67 | core3 { |
| 68 | cpu = <&CPU3>; |
| 69 | }; |
| 70 | }; |
| 71 | }; |
| 72 | |
| 73 | CPU0: cpu@0 { |
| 74 | device_type = "cpu"; |
| 75 | compatible = "arm,cortex-a7"; |
| 76 | reg = <0x0>; |
Lingutla Chandrasekhar | ee6522a4 | 2018-03-13 16:12:03 +0530 | [diff] [blame] | 77 | efficiency = <1024>; |
| 78 | sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 79 | qcom,sleep-status = <&cpu0_slp_sts>; |
Chinkit Kumar,Kirti Kumar Parmar | d9253d8 | 2018-06-08 13:36:28 +0530 | [diff] [blame] | 80 | #cooling-cells = <2>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 81 | }; |
| 82 | |
| 83 | CPU1: cpu@1 { |
| 84 | device_type = "cpu"; |
| 85 | compatible = "arm,cortex-a7"; |
| 86 | reg = <0x1>; |
Lingutla Chandrasekhar | ee6522a4 | 2018-03-13 16:12:03 +0530 | [diff] [blame] | 87 | efficiency = <1024>; |
| 88 | sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 89 | qcom,sleep-status = <&cpu1_slp_sts>; |
Chinkit Kumar,Kirti Kumar Parmar | d9253d8 | 2018-06-08 13:36:28 +0530 | [diff] [blame] | 90 | #cooling-cells = <2>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 91 | }; |
| 92 | |
| 93 | CPU2: cpu@2 { |
| 94 | device_type = "cpu"; |
| 95 | compatible = "arm,cortex-a7"; |
| 96 | reg = <0x2>; |
Lingutla Chandrasekhar | ee6522a4 | 2018-03-13 16:12:03 +0530 | [diff] [blame] | 97 | efficiency = <1024>; |
| 98 | sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 99 | qcom,sleep-status = <&cpu2_slp_sts>; |
Chinkit Kumar,Kirti Kumar Parmar | d9253d8 | 2018-06-08 13:36:28 +0530 | [diff] [blame] | 100 | #cooling-cells = <2>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 101 | }; |
| 102 | |
| 103 | CPU3: cpu@3 { |
| 104 | device_type = "cpu"; |
| 105 | compatible = "arm,cortex-a7"; |
| 106 | reg = <0x3>; |
Lingutla Chandrasekhar | ee6522a4 | 2018-03-13 16:12:03 +0530 | [diff] [blame] | 107 | efficiency = <1024>; |
| 108 | sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 109 | qcom,sleep-status = <&cpu3_slp_sts>; |
Chinkit Kumar,Kirti Kumar Parmar | d9253d8 | 2018-06-08 13:36:28 +0530 | [diff] [blame] | 110 | #cooling-cells = <2>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 111 | }; |
| 112 | }; |
| 113 | |
Lingutla Chandrasekhar | ee6522a4 | 2018-03-13 16:12:03 +0530 | [diff] [blame] | 114 | energy_costs: energy-costs { |
| 115 | compatible = "sched-energy"; |
| 116 | |
| 117 | CPU_COST_0: core-cost0 { |
| 118 | busy-cost-data = < |
| 119 | 400000 82 |
| 120 | 800000 164 |
| 121 | 1094400 290 |
| 122 | >; |
| 123 | idle-cost-data = < |
| 124 | 40 20 12 8 |
| 125 | >; |
| 126 | }; |
| 127 | CLUSTER_COST_0: cluster-cost0 { |
| 128 | busy-cost-data = < |
| 129 | 400000 23 |
| 130 | 800000 48 |
| 131 | 1094400 87 |
| 132 | >; |
| 133 | idle-cost-data = < |
| 134 | 4 3 2 1 |
| 135 | >; |
| 136 | }; |
| 137 | }; |
| 138 | |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 139 | firmware: firmware { |
| 140 | android { |
| 141 | compatible = "android,firmware"; |
| 142 | fstab { |
| 143 | compatible = "android,fstab"; |
| 144 | vendor_fstab: vendor { |
| 145 | compatible = "android,vendor"; |
| 146 | dev = |
| 147 | "/dev/block/platform/soc/7824900.sdhci/by-name/vendor"; |
| 148 | type = "ext4"; |
| 149 | mnt_flags = "ro,barrier=1,discard"; |
| 150 | fsmgr_flags = "wait,verify"; |
| 151 | status = "ok"; |
| 152 | }; |
| 153 | system_fstab: system { |
| 154 | compatible = "android,system"; |
| 155 | dev = |
| 156 | "/dev/block/platform/soc/7824900.sdhci/by-name/system"; |
| 157 | type = "ext4"; |
| 158 | mnt_flags = "ro,barrier=1,discard"; |
| 159 | fsmgr_flags = "wait,verify"; |
| 160 | status = "ok"; |
| 161 | }; |
| 162 | }; |
| 163 | }; |
| 164 | }; |
| 165 | |
| 166 | reserved-memory { |
| 167 | #address-cells = <2>; |
| 168 | #size-cells = <2>; |
| 169 | ranges; |
| 170 | |
| 171 | external_image_mem: external_image__region@0 { |
| 172 | reg = <0x0 0x87a00000 0x0 0x0600000>; |
| 173 | compatible = "removed-dma-pool"; |
| 174 | no-map; |
| 175 | }; |
| 176 | |
| 177 | modem_adsp_mem: modem_adsp_region@0 { |
| 178 | reg = <0x0 0x88000000 0x0 0x05500000>; |
| 179 | compatible = "removed-dma-pool"; |
| 180 | no-map; |
| 181 | }; |
| 182 | |
| 183 | peripheral_mem: pheripheral_region@0 { |
| 184 | reg = <0x0 0x8d500000 0x0 0x0700000>; |
| 185 | compatible = "removed-dma-pool"; |
| 186 | no-map; |
| 187 | }; |
| 188 | |
| 189 | venus_qseecom_mem: venus_qseecom_region@0 { |
| 190 | compatible = "shared-dma-pool"; |
| 191 | reusable; |
| 192 | alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; |
| 193 | alignment = <0 0x400000>; |
| 194 | size = <0 0x0800000>; |
| 195 | }; |
| 196 | |
Ramesh Yadav Javadi | 92bb99a | 2018-03-31 13:19:54 +0530 | [diff] [blame] | 197 | qseecom_ta_mem: qseecom_ta_region { |
| 198 | compatible = "shared-dma-pool"; |
| 199 | alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| 200 | reusable; |
| 201 | alignment = <0 0x400000>; |
| 202 | size = <0 0x400000>; |
| 203 | }; |
| 204 | |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 205 | audio_mem: audio_region@0 { |
| 206 | compatible = "shared-dma-pool"; |
| 207 | reusable; |
| 208 | alignment = <0 0x400000>; |
| 209 | size = <0 0x400000>; |
| 210 | }; |
| 211 | |
| 212 | adsp_mem: adsp_region@0 { |
| 213 | compatible = "shared-dma-pool"; |
| 214 | reusable; |
| 215 | alignment = <0 0x400000>; |
| 216 | size = <0 0x400000>; |
| 217 | }; |
| 218 | |
| 219 | cont_splash_mem: splash_region@83000000 { |
| 220 | reg = <0x0 0x83000000 0x0 0xc00000>; |
| 221 | }; |
Sundara Vinayagam | c317902 | 2018-03-23 20:41:57 +0530 | [diff] [blame] | 222 | |
| 223 | dump_mem: mem_dump_region { |
| 224 | compatible = "shared-dma-pool"; |
| 225 | reusable; |
| 226 | size = <0 0x100000>; |
| 227 | }; |
| 228 | |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 229 | }; |
| 230 | |
| 231 | soc: soc { }; |
| 232 | }; |
| 233 | |
| 234 | #include "msm8909-ion.dtsi" |
| 235 | #include "msm8909-smp2p.dtsi" |
| 236 | #include "msm8909-ipcrouter.dtsi" |
| 237 | #include "msm-gdsc-8916.dtsi" |
Maria Yu | 4c9890f | 2018-04-13 15:34:17 +0800 | [diff] [blame] | 238 | #include "msm-arm-smmu-8909.dtsi" |
Satish Kumar Kurada | bbc2f00 | 2018-03-20 11:18:01 +0530 | [diff] [blame] | 239 | #include "msm8909-gpu.dtsi" |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 240 | #include "msm8909-coresight.dtsi" |
| 241 | #include "msm8909-bus.dtsi" |
Arun kumar | caadcd5 | 2018-05-14 15:11:10 +0530 | [diff] [blame] | 242 | #include "msm8909-vidc.dtsi" |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 243 | #include "msm8909-mdss.dtsi" |
| 244 | #include "msm8909-mdss-pll.dtsi" |
| 245 | |
| 246 | &soc { |
| 247 | #address-cells = <1>; |
| 248 | #size-cells = <1>; |
| 249 | ranges = <0 0 0 0xffffffff>; |
| 250 | compatible = "simple-bus"; |
| 251 | |
| 252 | intc: interrupt-controller@b000000 { |
| 253 | compatible = "qcom,msm-qgic2"; |
| 254 | interrupt-controller; |
Raja Mallik | 3e4c958 | 2018-04-18 10:59:14 +0530 | [diff] [blame] | 255 | interrupt-parent = <&intc>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 256 | #interrupt-cells = <3>; |
| 257 | reg = <0x0b000000 0x1000>, |
| 258 | <0x0b002000 0x1000>; |
| 259 | }; |
| 260 | |
Raja Mallik | 3e4c958 | 2018-04-18 10:59:14 +0530 | [diff] [blame] | 261 | wakegic: wake-gic@601d0 { |
| 262 | compatible = "qcom,mpm-gic-msm8909", "qcom,mpm-gic"; |
| 263 | interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>; |
| 264 | reg = <0x601d0 0x1000>, |
| 265 | <0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ |
| 266 | reg-names = "vmpm", "ipc"; |
| 267 | interrupt-controller; |
| 268 | interrupt-parent = <&intc>; |
| 269 | #interrupt-cells = <3>; |
| 270 | }; |
| 271 | |
| 272 | wakegpio: wake-gpio { |
| 273 | compatible = "qcom,mpm-gpio-msm8909", "qcom,mpm-gpio"; |
| 274 | interrupt-controller; |
| 275 | interrupt-parent = <&intc>; |
| 276 | #interrupt-cells = <2>; |
| 277 | }; |
| 278 | |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 279 | restart@4ab000 { |
| 280 | compatible = "qcom,pshold"; |
| 281 | reg = <0x4ab000 0x4>, |
| 282 | <0x193d100 0x4>; |
| 283 | reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| 284 | }; |
| 285 | |
| 286 | timer { |
| 287 | compatible = "arm,armv7-timer"; |
| 288 | interrupts = <1 2 0xf08>, |
| 289 | <1 3 0xf08>, |
| 290 | <1 4 0xf08>, |
| 291 | <1 1 0xf08>; |
| 292 | clock-frequency = <19200000>; |
| 293 | }; |
| 294 | |
| 295 | timer@b020000 { |
| 296 | #address-cells = <1>; |
| 297 | #size-cells = <1>; |
| 298 | ranges; |
| 299 | compatible = "arm,armv7-timer-mem"; |
| 300 | reg = <0xb020000 0x1000>; |
| 301 | clock-frequency = <19200000>; |
| 302 | |
| 303 | frame@b021000 { |
| 304 | frame-number = <0>; |
| 305 | interrupts = <0 8 0x4>, |
| 306 | <0 7 0x4>; |
| 307 | reg = <0xb021000 0x1000>, |
| 308 | <0xb022000 0x1000>; |
| 309 | }; |
| 310 | frame@b023000 { |
| 311 | frame-number = <1>; |
| 312 | interrupts = <0 9 0x4>; |
| 313 | reg = <0xb023000 0x1000>; |
| 314 | status = "disabled"; |
| 315 | }; |
| 316 | frame@b024000 { |
| 317 | frame-number = <2>; |
| 318 | interrupts = <0 10 0x4>; |
| 319 | reg = <0xb024000 0x1000>; |
| 320 | status = "disabled"; |
| 321 | }; |
| 322 | frame@b025000 { |
| 323 | frame-number = <3>; |
| 324 | interrupts = <0 11 0x4>; |
| 325 | reg = <0xb025000 0x1000>; |
| 326 | status = "disabled"; |
| 327 | }; |
| 328 | frame@b026000 { |
| 329 | frame-number = <4>; |
| 330 | interrupts = <0 12 0x4>; |
| 331 | reg = <0xb026000 0x1000>; |
| 332 | status = "disabled"; |
| 333 | }; |
| 334 | frame@b027000 { |
| 335 | frame-number = <5>; |
| 336 | interrupts = <0 13 0x4>; |
| 337 | reg = <0xb027000 0x1000>; |
| 338 | status = "disabled"; |
| 339 | }; |
| 340 | frame@b028000 { |
| 341 | frame-number = <6>; |
| 342 | interrupts = <0 14 0x4>; |
| 343 | reg = <0xb028000 0x1000>; |
| 344 | status = "disabled"; |
| 345 | }; |
| 346 | }; |
| 347 | |
| 348 | clock_rpm: qcom,rpmcc@1800000 { |
| 349 | compatible = "qcom,rpmcc-8909"; |
| 350 | reg = <0x1800000 0x80000>; |
| 351 | reg-names = "cc_base"; |
| 352 | #clock-cells = <1>; |
| 353 | }; |
| 354 | |
| 355 | clock_gcc: qcom,gcc@1800000 { |
| 356 | compatible = "qcom,gcc-8909"; |
| 357 | reg = <0x1800000 0x80000>, |
| 358 | <0xb016000 0x00040>; |
| 359 | reg-names = "cc_base", "apcs_base"; |
Amit Nischal | dc89dbe | 2018-06-20 13:24:41 +0530 | [diff] [blame] | 360 | qcom,gfx3d_clk_src-opp-store-vcorner = <&msm_gpu>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 361 | vdd_dig-supply = <&pm8909_s1_corner>; |
| 362 | vdd_sr2_dig-supply = <&pm8909_s1_corner_ao>; |
| 363 | vdd_sr2_pll-supply = <&pm8909_l7_ao>; |
| 364 | clocks = <&clock_rpm clk_xo_clk_src>, |
| 365 | <&clock_rpm clk_xo_a_clk_src>; |
| 366 | clock-names = "xo", "xo_a"; |
| 367 | #clock-cells = <1>; |
Sundara Vinayagam | a00c2ae | 2018-03-05 12:16:16 +0530 | [diff] [blame] | 368 | #reset-cells = <1>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 369 | }; |
| 370 | |
| 371 | clock_gcc_mdss: qcom,gcc-mdss@1ac8300 { |
| 372 | compatible = "qcom,gcc-mdss-8909"; |
| 373 | clocks = <&mdss_dsi0_pll clk_dsi_pll0_pixel_clk_src>, |
| 374 | <&mdss_dsi0_pll clk_dsi_pll0_byte_clk_src>; |
Arun kumar | 1ca0394 | 2018-03-27 12:22:54 +0530 | [diff] [blame] | 375 | clock-names = "pclk0_src", "byte0_src"; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 376 | #clock-cells = <1>; |
| 377 | }; |
| 378 | |
| 379 | clock_debug: qcom,cc-debug@1874000 { |
| 380 | compatible = "qcom,cc-debug-8909"; |
| 381 | reg = <0x1874000 0x4>, |
| 382 | <0xb01101c 0x8>; |
| 383 | reg-names = "cc_base", "meas"; |
| 384 | clocks = <&clock_rpm clk_rpm_debug_mux>; |
| 385 | clock-names = "rpm_debug_mux"; |
| 386 | #clock-cells = <1>; |
| 387 | }; |
| 388 | |
| 389 | clock_cpu: qcom,clock-a7@0b011050 { |
| 390 | compatible = "qcom,clock-a53-8916"; |
| 391 | reg = <0x0b011050 0x8>, |
| 392 | <0x0005c00c 0x8>; |
| 393 | reg-names = "rcg-base", "efuse"; |
| 394 | qcom,safe-freq = < 400000000 >; |
| 395 | cpu-vdd-supply = <&pm8909_s1_corner_ao>; |
Taniya Das | a4af320 | 2018-03-20 08:59:11 +0530 | [diff] [blame] | 396 | qcom,enable-opp; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 397 | clocks = <&clock_gcc clk_gpll0_ao_clk_src>, |
| 398 | <&clock_gcc clk_a7sspll>; |
| 399 | clock-names = "clk-4", "clk-5"; |
| 400 | qcom,speed0-bin-v0 = |
| 401 | < 0 0>, |
| 402 | < 400000000 4>, |
| 403 | < 800000000 5>, |
| 404 | < 1267200000 7>; |
| 405 | qcom,speed2-bin-v0 = |
| 406 | < 0 0>, |
| 407 | < 400000000 4>, |
| 408 | < 800000000 5>, |
| 409 | < 1094400000 7>; |
| 410 | #clock-cells = <1>; |
| 411 | }; |
| 412 | |
| 413 | cpubw: qcom,cpubw { |
| 414 | compatible = "qcom,devbw"; |
| 415 | governor = "cpufreq"; |
| 416 | qcom,src-dst-ports = <1 512>; |
| 417 | qcom,active-only; |
| 418 | qcom,bw-tbl = |
| 419 | < 762 /* 100 MHz */>, |
| 420 | < 1525 /* 200 MHz */>, |
| 421 | < 3051 /* 400 MHz */>, |
| 422 | < 4066 /* 533 MHz */>; |
| 423 | }; |
| 424 | |
| 425 | devfreq-cpufreq { |
| 426 | cpubw-cpufreq { |
| 427 | target-dev = <&cpubw>; |
| 428 | cpu-to-dev-map = |
| 429 | < 400000 762>, |
| 430 | < 800000 1525>, |
| 431 | < 998400 3051>, |
| 432 | < 1094400 4066>; |
| 433 | }; |
| 434 | }; |
| 435 | |
| 436 | qcom,cpu-bwmon { |
| 437 | compatible = "qcom,bimc-bwmon2"; |
| 438 | reg = <0x408000 0x300>, <0x401000 0x200>; |
| 439 | reg-names = "base", "global_base"; |
| 440 | interrupts = <0 183 4>; |
| 441 | qcom,mport = <0>; |
| 442 | qcom,target-dev = <&cpubw>; |
| 443 | }; |
| 444 | |
| 445 | qcom,msm-cpufreq { |
| 446 | reg = <0 4>; |
| 447 | compatible = "qcom,msm-cpufreq"; |
| 448 | clocks = <&clock_cpu clk_a7ssmux>, |
| 449 | <&clock_cpu clk_a7ssmux>, |
| 450 | <&clock_cpu clk_a7ssmux>, |
| 451 | <&clock_cpu clk_a7ssmux>; |
| 452 | clock-names = "cpu0_clk", "cpu1_clk", |
| 453 | "cpu2_clk", "cpu3_clk"; |
| 454 | qcom,cpufreq-table = |
| 455 | < 200000 >, |
| 456 | < 400000 >, |
| 457 | < 533330 >, |
| 458 | < 800000 >, |
| 459 | < 998400 >, |
| 460 | < 1094400 >, |
| 461 | < 1190400 >, |
| 462 | < 1248000 >, |
| 463 | < 1267200 >; |
| 464 | }; |
| 465 | |
| 466 | |
| 467 | blsp1_uart1: serial@78af000 { |
| 468 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uart"; |
| 469 | reg = <0x78af000 0x200>; |
| 470 | interrupts = <0 107 0>; |
| 471 | status = "disabled"; |
| 472 | clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, |
| 473 | <&clock_gcc clk_gcc_blsp1_ahb_clk>; |
| 474 | clock-names = "core", "iface"; |
| 475 | }; |
| 476 | |
| 477 | blsp1_uart2_hs: uart@78b0000 { /*BLSP1 UART2*/ |
| 478 | compatible = "qcom,msm-hsuart-v14"; |
| 479 | reg = <0x78b0000 0x200>, |
| 480 | <0x7884000 0x1f000>; |
| 481 | reg-names = "core_mem", "bam_mem"; |
| 482 | interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; |
| 483 | #address-cells = <0>; |
| 484 | interrupt-parent = <&blsp1_uart2_hs>; |
| 485 | interrupts = <0 1 2>; |
| 486 | #interrupt-cells = <1>; |
| 487 | interrupt-map-mask = <0xffffffff>; |
| 488 | interrupt-map = <0 &intc 0 108 0 |
| 489 | 1 &intc 0 238 0 |
| 490 | 2 &msm_gpio 21 0>; |
| 491 | qcom,inject-rx-on-wakeup; |
| 492 | qcom,rx-char-to-inject = <0xfd>; |
| 493 | qcom,master-id = <86>; |
| 494 | clock-names = "core_clk", "iface_clk"; |
| 495 | clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, |
| 496 | <&clock_gcc clk_gcc_blsp1_ahb_clk>; |
| 497 | pinctrl-names = "sleep", "default"; |
| 498 | pinctrl-0 = <&blsp1_uart2_tx_sleep>, <&blsp1_uart2_rxcts_sleep>, |
| 499 | <&blsp1_uart2_rfr_sleep>; |
| 500 | pinctrl-1 = <&blsp1_uart2_tx_active>, |
| 501 | <&blsp1_uart2_rxcts_active>, <&blsp1_uart2_rfr_active>; |
| 502 | |
| 503 | qcom,bam-tx-ep-pipe-index = <2>; |
| 504 | qcom,bam-rx-ep-pipe-index = <3>; |
| 505 | qcom,msm-bus,name = "blsp1_uart2_hs"; |
| 506 | qcom,msm-bus,num-cases = <2>; |
| 507 | qcom,msm-bus,num-paths = <1>; |
| 508 | qcom,msm-bus,vectors-KBps = |
| 509 | <86 512 0 0>, |
| 510 | <86 512 500 800>; |
| 511 | status = "disabled"; |
| 512 | }; |
| 513 | |
| 514 | qcom,sps { |
| 515 | compatible = "qcom,msm_sps_4k"; |
| 516 | qcom,device-type = <3>; |
| 517 | qcom,pipe-attr-ee; |
| 518 | }; |
| 519 | |
| 520 | thermal_zones: thermal-zones {}; |
| 521 | |
Sundara Vinayagam | c317902 | 2018-03-23 20:41:57 +0530 | [diff] [blame] | 522 | mem_dump { |
| 523 | compatible = "qcom,mem-dump"; |
| 524 | memory-region = <&dump_mem>; |
| 525 | |
| 526 | rpm_sw_dump { |
| 527 | qcom,dump-size = <0x28000>; |
| 528 | qcom,dump-id = <0xea>; |
| 529 | }; |
| 530 | |
| 531 | pmic_dump { |
| 532 | qcom,dump-size = <0x10000>; |
| 533 | qcom,dump-id = <0xe4>; |
| 534 | }; |
| 535 | |
| 536 | vsense_dump { |
| 537 | qcom,dump-size = <0x1000>; |
| 538 | qcom,dump-id = <0xe9>; |
| 539 | }; |
| 540 | |
| 541 | tmc_etf_dump { |
| 542 | qcom,dump-size = <0x10000>; |
| 543 | qcom,dump-id = <0xf0>; |
| 544 | }; |
| 545 | |
| 546 | tmc_etr_reg_dump { |
| 547 | qcom,dump-size = <0x1000>; |
| 548 | qcom,dump-id = <0x100>; |
| 549 | }; |
| 550 | |
| 551 | tmc_etf_reg_dump { |
| 552 | qcom,dump-size = <0x1000>; |
| 553 | qcom,dump-id = <0x101>; |
| 554 | }; |
| 555 | |
| 556 | misc_data_dump { |
| 557 | qcom,dump-size = <0x1000>; |
| 558 | qcom,dump-id = <0xe8>; |
| 559 | }; |
| 560 | |
| 561 | }; |
| 562 | |
Chinkit Kumar,Kirti Kumar Parmar | 45662ff | 2018-06-01 19:24:08 +0530 | [diff] [blame] | 563 | tsens0: tsens@4a8000 { |
| 564 | compatible = "qcom,msm8909-tsens"; |
| 565 | reg = <0x4a8000 0x1000>, |
| 566 | <0x4a9000 0x1000>, |
| 567 | <0x5c000 0x1000>; |
| 568 | reg-names = "tsens_srot_physical", |
| 569 | "tsens_tm_physical", "tsens_eeprom_physical"; |
| 570 | interrupts = <0 184 0>; |
| 571 | interrupt-names = "tsens-upper-lower"; |
| 572 | #thermal-sensor-cells = <1>; |
| 573 | }; |
| 574 | |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 575 | qcom,ipc-spinlock@1905000 { |
| 576 | compatible = "qcom,ipc-spinlock-sfpb"; |
| 577 | reg = <0x1905000 0x8000>; |
| 578 | qcom,num-locks = <8>; |
| 579 | }; |
| 580 | |
| 581 | qcom,smem@87d00000 { |
| 582 | compatible = "qcom,smem"; |
| 583 | reg = <0x87d00000 0x100000>, |
| 584 | <0x0b011008 0x4>, |
| 585 | <0x60000 0x8000>, |
| 586 | <0x193D000 0x8>; |
| 587 | reg-names = "smem", "irq-reg-base", |
| 588 | "aux-mem1", "smem_targ_info_reg"; |
| 589 | qcom,mpu-enabled; |
| 590 | |
| 591 | qcom,smd-modem { |
| 592 | compatible = "qcom,smd"; |
| 593 | qcom,smd-edge = <0>; |
| 594 | qcom,smd-irq-offset = <0x0>; |
| 595 | qcom,smd-irq-bitmask = <0x1000>; |
| 596 | interrupts = <0 25 1>; |
| 597 | label = "modem"; |
| 598 | qcom,not-loadable; |
| 599 | }; |
| 600 | |
| 601 | qcom,smsm-modem { |
| 602 | compatible = "qcom,smsm"; |
| 603 | qcom,smsm-edge = <0>; |
| 604 | qcom,smsm-irq-offset = <0x0>; |
| 605 | qcom,smsm-irq-bitmask = <0x2000>; |
| 606 | interrupts = <0 26 1>; |
| 607 | }; |
| 608 | |
| 609 | qcom,smd-wcnss { |
| 610 | compatible = "qcom,smd"; |
| 611 | qcom,smd-edge = <6>; |
| 612 | qcom,smd-irq-offset = <0x0>; |
| 613 | qcom,smd-irq-bitmask = <0x20000>; |
| 614 | interrupts = <0 142 1>; |
| 615 | label = "wcnss"; |
| 616 | }; |
| 617 | |
| 618 | qcom,smsm-wcnss { |
| 619 | compatible = "qcom,smsm"; |
| 620 | qcom,smsm-edge = <6>; |
| 621 | qcom,smsm-irq-offset = <0x0>; |
| 622 | qcom,smsm-irq-bitmask = <0x80000>; |
| 623 | interrupts = <0 144 1>; |
| 624 | }; |
| 625 | |
| 626 | qcom,smd-rpm { |
| 627 | compatible = "qcom,smd"; |
| 628 | qcom,smd-edge = <15>; |
| 629 | qcom,smd-irq-offset = <0x0>; |
| 630 | qcom,smd-irq-bitmask = <0x1>; |
| 631 | interrupts = <0 168 1>; |
| 632 | label = "rpm"; |
| 633 | qcom,irq-no-suspend; |
| 634 | qcom,not-loadable; |
| 635 | }; |
| 636 | }; |
| 637 | |
| 638 | rpm_bus: qcom,rpm-smd { |
| 639 | compatible = "qcom,rpm-smd"; |
| 640 | rpm-channel-name = "rpm_requests"; |
| 641 | rpm-channel-type = <15>; /* SMD_APPS_RPM */ |
| 642 | }; |
| 643 | |
Sundara Vinayagam | a230edb | 2018-04-25 15:44:40 +0530 | [diff] [blame] | 644 | qcom,bam_dmux@4044000 { |
| 645 | compatible = "qcom,bam_dmux"; |
| 646 | reg = <0x4044000 0x19000>; |
| 647 | interrupts = <0 29 1>; |
| 648 | qcom,rx-ring-size = <32>; |
| 649 | qcom,max-rx-mtu = <4096>; |
| 650 | qcom,fast-shutdown; |
| 651 | qcom,no-cpu-affinity; |
| 652 | }; |
| 653 | |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 654 | qcom,smdtty { |
| 655 | compatible = "qcom,smdtty"; |
| 656 | |
| 657 | smdtty_apps_fm: qcom,smdtty-apps-fm { |
| 658 | qcom,smdtty-remote = "wcnss"; |
| 659 | qcom,smdtty-port-name = "APPS_FM"; |
| 660 | }; |
| 661 | |
| 662 | smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl { |
| 663 | qcom,smdtty-remote = "wcnss"; |
| 664 | qcom,smdtty-port-name = "APPS_RIVA_BT_ACL"; |
| 665 | }; |
| 666 | |
| 667 | smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd { |
| 668 | qcom,smdtty-remote = "wcnss"; |
| 669 | qcom,smdtty-port-name = "APPS_RIVA_BT_CMD"; |
| 670 | }; |
| 671 | |
| 672 | smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd { |
| 673 | qcom,smdtty-remote = "wcnss"; |
| 674 | qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD"; |
| 675 | }; |
| 676 | |
| 677 | smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data { |
| 678 | qcom,smdtty-remote = "wcnss"; |
| 679 | qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA"; |
| 680 | }; |
| 681 | |
| 682 | smdtty_data1: qcom,smdtty-data1 { |
| 683 | qcom,smdtty-remote = "modem"; |
| 684 | qcom,smdtty-port-name = "DATA1"; |
| 685 | }; |
| 686 | |
| 687 | smdtty_data4: qcom,smdtty-data4 { |
| 688 | qcom,smdtty-remote = "modem"; |
| 689 | qcom,smdtty-port-name = "DATA4"; |
| 690 | }; |
| 691 | |
| 692 | smdtty_data11: qcom,smdtty-data11 { |
| 693 | qcom,smdtty-remote = "modem"; |
| 694 | qcom,smdtty-port-name = "DATA11"; |
| 695 | }; |
| 696 | |
| 697 | smdtty_data21: qcom,smdtty-data21 { |
| 698 | qcom,smdtty-remote = "modem"; |
| 699 | qcom,smdtty-port-name = "DATA21"; |
| 700 | }; |
| 701 | |
| 702 | smdtty_loopback: smdtty-loopback { |
| 703 | qcom,smdtty-remote = "modem"; |
| 704 | qcom,smdtty-port-name = "LOOPBACK"; |
| 705 | qcom,smdtty-dev-name = "LOOPBACK_TTY"; |
| 706 | }; |
| 707 | }; |
| 708 | |
| 709 | qcom,smdpkt { |
| 710 | compatible = "qcom,smdpkt"; |
| 711 | |
| 712 | qcom,smdpkt-data5-cntl { |
| 713 | qcom,smdpkt-remote = "modem"; |
| 714 | qcom,smdpkt-port-name = "DATA5_CNTL"; |
| 715 | qcom,smdpkt-dev-name = "smdcntl0"; |
| 716 | }; |
| 717 | |
| 718 | qcom,smdpkt-data22 { |
| 719 | qcom,smdpkt-remote = "modem"; |
| 720 | qcom,smdpkt-port-name = "DATA22"; |
| 721 | qcom,smdpkt-dev-name = "smd22"; |
| 722 | }; |
| 723 | |
| 724 | qcom,smdpkt-data40-cntl { |
| 725 | qcom,smdpkt-remote = "modem"; |
| 726 | qcom,smdpkt-port-name = "DATA40_CNTL"; |
| 727 | qcom,smdpkt-dev-name = "smdcntl8"; |
| 728 | }; |
| 729 | |
| 730 | qcom,smdpkt-apr-apps2 { |
| 731 | qcom,smdpkt-remote = "modem"; |
| 732 | qcom,smdpkt-port-name = "apr_apps2"; |
| 733 | qcom,smdpkt-dev-name = "apr_apps2"; |
| 734 | }; |
| 735 | |
| 736 | qcom,smdpkt-loopback { |
| 737 | qcom,smdpkt-remote = "modem"; |
| 738 | qcom,smdpkt-port-name = "LOOPBACK"; |
| 739 | qcom,smdpkt-dev-name = "smd_pkt_loopback"; |
| 740 | }; |
| 741 | }; |
| 742 | |
| 743 | wcnss: qcom,wcnss-wlan@a000000 { |
| 744 | compatible = "qcom,wcnss_wlan"; |
| 745 | reg = <0x0a000000 0x280000>, |
| 746 | <0xb011008 0x04>, |
| 747 | <0x0a21b000 0x3000>, |
| 748 | <0x03204000 0x00000100>, |
| 749 | <0x03200800 0x00000200>, |
| 750 | <0x0A100400 0x00000200>, |
| 751 | <0x0A205050 0x00000200>, |
| 752 | <0x0A219000 0x00000020>, |
| 753 | <0x0A080488 0x00000008>, |
| 754 | <0x0A080fb0 0x00000008>, |
| 755 | <0x0A08040c 0x00000008>, |
| 756 | <0x0A0120a8 0x00000008>, |
| 757 | <0x0A012448 0x00000008>, |
| 758 | <0x0A080c00 0x00000001>, |
| 759 | <0x0005E000 0x00000064>; |
| 760 | |
| 761 | reg-names = "wcnss_mmio", "wcnss_fiq", |
| 762 | "pronto_phy_base", "riva_phy_base", |
| 763 | "riva_ccu_base", "pronto_a2xb_base", |
| 764 | "pronto_ccpu_base", "pronto_saw2_base", |
| 765 | "wlan_tx_phy_aborts","wlan_brdg_err_source", |
| 766 | "wlan_tx_status", "alarms_txctl", |
| 767 | "alarms_tactl", "pronto_mcu_base", |
| 768 | "pronto_qfuse"; |
| 769 | |
| 770 | interrupts = <0 145 0 0 146 0>; |
| 771 | interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; |
| 772 | |
| 773 | qcom,pronto-vddmx-supply = <&pm8909_l3_corner_ao>; |
| 774 | qcom,pronto-vddcx-supply = <&pm8909_s1_corner>; |
| 775 | qcom,pronto-vddpx-supply = <&pm8909_l7>; |
| 776 | qcom,iris-vddxo-supply = <&pm8909_l7>; |
| 777 | qcom,iris-vddrfa-supply = <&pm8909_l10>; |
| 778 | qcom,iris-vddpa-supply = <&pm8909_l9>; |
| 779 | qcom,iris-vdddig-supply = <&pm8909_l5>; |
| 780 | |
| 781 | qcom,iris-vddxo-voltage-level = <1800000 0 1800000>; |
| 782 | qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>; |
| 783 | qcom,iris-vddpa-voltage-level = <3300000 0 3300000>; |
| 784 | qcom,iris-vdddig-voltage-level = <1800000 0 1800000>; |
| 785 | |
| 786 | qcom,vddmx-voltage-level = <5 1 7>; |
| 787 | qcom,vddcx-voltage-level = <5 1 7>; |
| 788 | qcom,vddpx-voltage-level = <1800000 0 1800000>; |
| 789 | |
| 790 | qcom,iris-vddxo-current = <10000>; |
| 791 | qcom,iris-vddrfa-current = <100000>; |
| 792 | qcom,iris-vddpa-current = <515000>; |
| 793 | qcom,iris-vdddig-current = <10000>; |
| 794 | |
| 795 | qcom,pronto-vddmx-current = <0>; |
| 796 | qcom,pronto-vddcx-current = <0>; |
| 797 | qcom,pronto-vddpx-current = <0>; |
| 798 | |
| 799 | pinctrl-names = "wcnss_default", "wcnss_sleep", |
| 800 | "wcnss_gpio_default"; |
| 801 | pinctrl-0 = <&wcnss_default>; |
| 802 | pinctrl-1 = <&wcnss_sleep>; |
| 803 | pinctrl-2 = <&wcnss_gpio_default>; |
| 804 | |
| 805 | gpios = <&msm_gpio 40 0>, <&msm_gpio 41 0>, <&msm_gpio 42 0>, |
| 806 | <&msm_gpio 43 0>, <&msm_gpio 44 0>; |
| 807 | |
| 808 | clocks = <&clock_rpm clk_xo_wlan_clk>, |
| 809 | <&clock_rpm clk_rf_clk2>, |
| 810 | <&clock_debug clk_gcc_debug_mux>, |
| 811 | <&clock_gcc clk_wcnss_m_clk>; |
| 812 | clock-names = "xo", "rf_clk", "measure", "wcnss_debug"; |
| 813 | |
| 814 | qcom,wlan-rx-buff-count = <512>; |
| 815 | qcom,has-autodetect-xo; |
| 816 | qcom,is-pronto-v3; |
| 817 | qcom,is-dual-band-disabled; |
| 818 | qcom,is-pronto-vadc; |
| 819 | qcom,has-pronto-hw; |
| 820 | qcom,wcnss-adc_tm = <&pm8909_adc_tm>; |
| 821 | }; |
| 822 | |
| 823 | usb_otg: usb@78d9000 { |
| 824 | compatible = "qcom,hsusb-otg"; |
| 825 | reg = <0x78d9000 0x400>, <0x6c000 0x200>; |
| 826 | reg-names = "core", "phy_csr"; |
| 827 | |
| 828 | interrupts = <0 134 0>,<0 140 0>; |
| 829 | interrupt-names = "core_irq", "async_irq"; |
| 830 | |
| 831 | hsusb_vdd_dig-supply = <&pm8909_l2>; |
| 832 | HSUSB_1p8-supply = <&pm8909_l7>; |
| 833 | HSUSB_3p3-supply = <&pm8909_l13>; |
| 834 | qcom,vdd-voltage-level = <0 1200000 1200000>; |
| 835 | |
| 836 | qcom,hsusb-otg-phy-init-seq = <0x73 0x80 0xffffffff>; |
| 837 | qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */ |
| 838 | qcom,hsusb-otg-mode = <1>; /* DEVICE only */ |
| 839 | qcom,hsusb-otg-otg-control = <2>; /* PMIC */ |
| 840 | qcom,dp-manual-pullup; |
| 841 | qcom,phy-dvdd-always-on; |
Ajay Agarwal | e6d1c85 | 2018-07-03 15:48:45 +0530 | [diff] [blame] | 842 | qcom,hsusb-otg-delay-lpm; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 843 | qcom,hsusb-otg-mpm-dpsehv-int = <49>; |
| 844 | qcom,hsusb-otg-mpm-dmsehv-int = <58>; |
| 845 | |
| 846 | qcom,msm-bus,name = "usb2"; |
| 847 | qcom,msm-bus,num-cases = <3>; |
| 848 | qcom,msm-bus,num-paths = <1>; |
| 849 | qcom,msm-bus,vectors-KBps = |
| 850 | <87 512 0 0>, |
| 851 | <87 512 80000 0>, |
| 852 | <87 512 6000 6000>; |
| 853 | clocks = <&clock_gcc clk_gcc_usb_hs_ahb_clk>, |
| 854 | <&clock_gcc clk_gcc_usb_hs_system_clk>, |
| 855 | <&clock_gcc clk_gcc_usb2a_phy_sleep_clk>, |
| 856 | <&clock_rpm clk_bimc_usb_a_clk>, |
| 857 | <&clock_rpm clk_snoc_usb_a_clk>, |
| 858 | <&clock_rpm clk_pcnoc_usb_a_clk>, |
| 859 | <&clock_gcc clk_gcc_qusb2_phy_clk>, |
| 860 | <&clock_gcc clk_gcc_usb2_hs_phy_only_clk>, |
| 861 | <&clock_gcc clk_gcc_usb_hs_phy_cfg_ahb_clk>, |
| 862 | <&clock_rpm clk_xo_otg_clk>; |
| 863 | clock-names = "iface_clk", "core_clk", "sleep_clk", |
| 864 | "bimc_clk", "snoc_clk", "pcnoc_clk", |
| 865 | "phy_reset_clk", "phy_por_clk", "phy_csr_clk", |
| 866 | "xo"; |
| 867 | qcom,bus-clk-rate = <400000000 200000000 100000000>; |
| 868 | qcom,max-nominal-sysclk-rate = <100000000>; |
| 869 | qcom,boost-sysclk-with-streaming; |
Sundara Vinayagam | a00c2ae | 2018-03-05 12:16:16 +0530 | [diff] [blame] | 870 | resets = <&clock_gcc GCC_USB_HS_BCR>, |
| 871 | <&clock_gcc GCC_QUSB2_PHY_BCR>, |
| 872 | <&clock_gcc GCC_USB2_HS_PHY_ONLY_BCR>; |
| 873 | reset-names = "core_reset", "phy_reset", "phy_por_reset"; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 874 | }; |
| 875 | |
| 876 | android_usb: android_usb@086000c8 { |
| 877 | compatible = "qcom,android-usb"; |
| 878 | reg = <0x086000c8 0xc8>; |
| 879 | qcom,pm-qos-latency = <2 1001 12701>; |
| 880 | }; |
| 881 | |
| 882 | qcom,usbbam@78c4000 { |
| 883 | compatible = "qcom,usb-bam-msm"; |
| 884 | reg = <0x78c4000 0x15000>; |
| 885 | reg-names = "hsusb"; |
| 886 | interrupts = <0 135 0>; |
| 887 | interrupt-names = "hsusb"; |
| 888 | qcom,bam-type = <1>; |
| 889 | qcom,usb-bam-num-pipes = <2>; |
| 890 | qcom,usb-bam-fifo-baseaddr = <0x08603800>; |
| 891 | qcom,ignore-core-reset-ack; |
| 892 | qcom,disable-clk-gating; |
| 893 | qcom,reset-bam-on-disconnect; |
| 894 | |
| 895 | qcom,pipe0 { |
| 896 | label = "hsusb-qdss-in-0"; |
| 897 | qcom,usb-bam-mem-type = <2>; |
| 898 | qcom,dir = <1>; |
| 899 | qcom,pipe-num = <0>; |
| 900 | qcom,peer-bam = <0>; |
| 901 | qcom,peer-bam-physical-address = <0x884000>; |
| 902 | qcom,src-bam-pipe-index = <0>; |
| 903 | qcom,dst-bam-pipe-index = <0>; |
| 904 | qcom,data-fifo-offset = <0x0>; |
| 905 | qcom,data-fifo-size = <0x600>; |
| 906 | qcom,descriptor-fifo-offset = <0x600>; |
| 907 | qcom,descriptor-fifo-size = <0x200>; |
| 908 | }; |
| 909 | }; |
| 910 | |
| 911 | spmi_bus: qcom,spmi@200f000 { |
| 912 | compatible = "qcom,spmi-pmic-arb"; |
| 913 | reg = <0x200f000 0x1000>, |
| 914 | <0x2400000 0x400000>, |
| 915 | <0x2c00000 0x400000>, |
| 916 | <0x3800000 0x200000>, |
| 917 | <0x200a000 0x2100>; |
| 918 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| 919 | interrupt-names = "periph_irq"; |
| 920 | interrupts = <0 190 0>; |
| 921 | qcom,ee = <0>; |
| 922 | qcom,channel = <0>; |
| 923 | #address-cells = <1>; |
| 924 | #size-cells = <1>; |
| 925 | #interrupt-cells = <4>; |
| 926 | interrupt-controller; |
| 927 | cell-index = <0>; |
| 928 | }; |
| 929 | |
| 930 | qcom,rmtfs_sharedmem@87c00000 { |
| 931 | |
| 932 | compatible = "qcom,sharedmem-uio"; |
| 933 | reg = <0x87c00000 0xe0000>; |
| 934 | reg-names = "rmtfs"; |
| 935 | qcom,client-id = <0x00000001>; |
| 936 | }; |
| 937 | |
| 938 | qcom,dsp_sharedmem@87ce0000 { |
| 939 | compatible = "qcom,sharedmem-uio"; |
| 940 | reg = <0x87ce0000 0x10000>; |
| 941 | reg-names = "rfsa_dsp"; |
| 942 | qcom,client-id = <0x011013ec>; |
| 943 | }; |
| 944 | |
| 945 | qcom,mdm_sharedmem@87cf0000 { |
| 946 | compatible = "qcom,sharedmem-uio"; |
| 947 | reg = <0x87cf0000 0x10000>; |
| 948 | reg-names = "rfsa_mdm"; |
| 949 | qcom,client-id = <0x011013ed>; |
| 950 | }; |
| 951 | |
| 952 | cpu-pmu { |
| 953 | compatible = "arm,cortex-a7-pmu"; |
| 954 | qcom,irq-is-percpu; |
| 955 | interrupts = <1 7 0xf00>; |
| 956 | }; |
| 957 | |
| 958 | jtag_fuse: jtagfuse@5e01c { |
| 959 | compatible = "qcom,jtag-fuse-v2"; |
| 960 | reg = <0x5e01c 0x8>; |
| 961 | reg-names = "fuse-base"; |
| 962 | }; |
| 963 | |
| 964 | jtag_mm0: jtagmm@84c000 { |
| 965 | compatible = "qcom,jtag-mm"; |
| 966 | reg = <0x84c000 0x1000>, |
| 967 | <0x840000 0x1000>; |
| 968 | reg-names = "etm-base","debug-base"; |
| 969 | |
| 970 | clocks = <&clock_rpm clk_qdss_clk>, |
| 971 | <&clock_rpm clk_qdss_a_clk>; |
| 972 | clock-names = "core_clk", "core_a_clk"; |
| 973 | |
| 974 | qcom,coresight-jtagmm-cpu = <&CPU0>; |
| 975 | }; |
| 976 | |
| 977 | jtag_mm1: jtagmm@84d000 { |
| 978 | compatible = "qcom,jtag-mm"; |
| 979 | reg = <0x84d000 0x1000>, |
| 980 | <0x842000 0x1000>; |
| 981 | reg-names = "etm-base","debug-base"; |
| 982 | |
| 983 | clocks = <&clock_rpm clk_qdss_clk>, |
| 984 | <&clock_rpm clk_qdss_a_clk>; |
| 985 | clock-names = "core_clk", "core_a_clk"; |
| 986 | |
| 987 | qcom,coresight-jtagmm-cpu = <&CPU1>; |
| 988 | }; |
| 989 | |
| 990 | jtag_mm2: jtagmm@84e000 { |
| 991 | compatible = "qcom,jtag-mm"; |
| 992 | reg = <0x84e000 0x1000>, |
| 993 | <0x844000 0x1000>; |
| 994 | reg-names = "etm-base","debug-base"; |
| 995 | |
| 996 | clocks = <&clock_rpm clk_qdss_clk>, |
| 997 | <&clock_rpm clk_qdss_a_clk>; |
| 998 | clock-names = "core_clk", "core_a_clk"; |
| 999 | |
| 1000 | qcom,coresight-jtagmm-cpu = <&CPU2>; |
| 1001 | }; |
| 1002 | |
| 1003 | jtag_mm3: jtagmm@84f000 { |
| 1004 | compatible = "qcom,jtag-mm"; |
| 1005 | reg = <0x84f000 0x1000>, |
| 1006 | <0x846000 0x1000>; |
| 1007 | reg-names = "etm-base","debug-base"; |
| 1008 | |
| 1009 | clocks = <&clock_rpm clk_qdss_clk>, |
| 1010 | <&clock_rpm clk_qdss_a_clk>; |
| 1011 | clock-names = "core_clk", "core_a_clk"; |
| 1012 | |
| 1013 | qcom,coresight-jtagmm-cpu = <&CPU3>; |
| 1014 | }; |
| 1015 | |
| 1016 | qnand_1: nand@7980000 { |
| 1017 | compatible = "qcom,msm-nand"; |
| 1018 | reg = <0x7980000 0x1000>, |
| 1019 | <0x7984000 0x1a000>, |
| 1020 | <0x5e02c 0x4>; |
| 1021 | reg-names = "nand_phys", |
| 1022 | "bam_phys", "boot_cfg"; |
| 1023 | qcom,reg-adjustment-offset = <0>; |
| 1024 | interrupts = <0 132 0>; |
| 1025 | interrupt-names = "bam_irq"; |
| 1026 | |
| 1027 | qcom,msm-bus,name = "qpic_nand"; |
| 1028 | qcom,msm-bus,num-cases = <2>; |
| 1029 | qcom,msm-bus,num-paths = <1>; |
| 1030 | qcom,msm-bus,vectors-KBps = |
| 1031 | <91 512 0 0>, |
| 1032 | /* Voting for max b/w on PNOC bus for now */ |
| 1033 | <91 512 400000 800000>; |
| 1034 | |
| 1035 | clock-names = "core_clk"; |
| 1036 | clocks = <&clock_rpm clk_qpic_clk>; |
| 1037 | status = "disabled"; |
| 1038 | }; |
| 1039 | |
| 1040 | sdhc_1: sdhci@7824000 { |
| 1041 | compatible = "qcom,sdhci-msm"; |
| 1042 | reg = <0x07824900 0x11c>, <0x07824000 0x800>; |
| 1043 | reg-names = "hc_mem", "core_mem"; |
| 1044 | |
| 1045 | interrupts = <0 123 0>, <0 138 0>; |
| 1046 | interrupt-names = "hc_irq", "pwr_irq"; |
| 1047 | |
| 1048 | qcom,bus-width = <8>; |
| 1049 | |
| 1050 | qcom,pm-qos-irq-type = "affine_irq"; |
| 1051 | qcom,pm-qos-irq-latency = <2 250>; |
| 1052 | |
| 1053 | qcom,msm-bus,name = "sdhc1"; |
| 1054 | qcom,msm-bus,num-cases = <8>; |
| 1055 | qcom,msm-bus,num-paths = <1>; |
| 1056 | qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ |
| 1057 | <78 512 1046 3200>, /* 400 KB/s*/ |
| 1058 | <78 512 52286 160000>, /* 20 MB/s */ |
| 1059 | <78 512 65360 200000>, /* 25 MB/s */ |
| 1060 | <78 512 130718 400000>, /* 50 MB/s */ |
| 1061 | <78 512 261438 800000>, /* 100 MB/s */ |
| 1062 | <78 512 261438 800000>, /* 200 MB/s */ |
| 1063 | <78 512 1338562 4096000>; /* Max. bandwidth */ |
| 1064 | qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 |
| 1065 | 100000000 200000000 4294967295>; |
| 1066 | |
| 1067 | |
| 1068 | clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>, |
| 1069 | <&clock_gcc clk_gcc_sdcc1_apps_clk>; |
| 1070 | clock-names = "iface_clk", "core_clk"; |
| 1071 | qcom,clk-rates = <400000 25000000 50000000 100000000 177770000>; |
| 1072 | qcom,devfreq,freq-table = <50000000 177770000>; |
| 1073 | |
| 1074 | status = "disabled"; |
| 1075 | }; |
| 1076 | |
| 1077 | sdhc_2: sdhci@07864000 { |
| 1078 | compatible = "qcom,sdhci-msm"; |
| 1079 | reg = <0x07864900 0x11c>, <0x07864000 0x800>; |
| 1080 | reg-names = "hc_mem", "core_mem"; |
| 1081 | |
| 1082 | interrupts = <0 125 0>, <0 221 0>; |
| 1083 | interrupt-names = "hc_irq", "pwr_irq"; |
| 1084 | |
| 1085 | qcom,bus-width = <4>; |
| 1086 | |
| 1087 | qcom,pm-qos-irq-type = "affine_irq"; |
| 1088 | qcom,pm-qos-irq-latency = <2 250>; |
| 1089 | |
| 1090 | qcom,msm-bus,name = "sdhc2"; |
| 1091 | qcom,msm-bus,num-cases = <8>; |
| 1092 | qcom,msm-bus,num-paths = <1>; |
| 1093 | qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ |
| 1094 | <81 512 1046 3200>, /* 400 KB/s*/ |
| 1095 | <81 512 52286 160000>, /* 20 MB/s */ |
| 1096 | <81 512 65360 200000>, /* 25 MB/s */ |
| 1097 | <81 512 130718 400000>, /* 50 MB/s */ |
| 1098 | <81 512 261438 800000>, /* 100 MB/s */ |
| 1099 | <81 512 261438 800000>, /* 200 MB/s */ |
| 1100 | <81 512 1338562 4096000>; /* Max. bandwidth */ |
| 1101 | qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 |
| 1102 | 100000000 200000000 4294967295>; |
| 1103 | |
| 1104 | clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, |
| 1105 | <&clock_gcc clk_gcc_sdcc2_apps_clk>; |
| 1106 | clock-names = "iface_clk", "core_clk"; |
| 1107 | |
| 1108 | qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; |
| 1109 | qcom,devfreq,freq-table = <50000000 200000000>; |
| 1110 | |
| 1111 | status = "disabled"; |
| 1112 | }; |
| 1113 | |
| 1114 | qcom,wdt@b017000 { |
| 1115 | compatible = "qcom,msm-watchdog"; |
| 1116 | reg = <0xb017000 0x1000>; |
| 1117 | reg-names = "wdt-base"; |
| 1118 | interrupts = <0 3 0>, <0 4 0>; |
| 1119 | qcom,bark-time = <11000>; |
| 1120 | qcom,pet-time = <10000>; |
| 1121 | qcom,ipi-ping; |
| 1122 | }; |
| 1123 | |
| 1124 | qcom,msm-rtb { |
| 1125 | compatible = "qcom,msm-rtb"; |
| 1126 | qcom,rtb-size = <0x100000>; /* 1M EBI1 buffer */ |
| 1127 | }; |
| 1128 | |
| 1129 | qcom,msm-imem@8600000 { |
| 1130 | compatible = "qcom,msm-imem"; |
| 1131 | reg = <0x08600000 0x1000>; /* Address and size of IMEM */ |
| 1132 | ranges = <0x0 0x08600000 0x1000>; |
| 1133 | #address-cells = <1>; |
| 1134 | #size-cells = <1>; |
| 1135 | |
| 1136 | mem_dump_table@10 { |
| 1137 | compatible = "qcom,msm-imem-mem_dump_table"; |
| 1138 | reg = <0x10 8>; |
| 1139 | }; |
| 1140 | |
| 1141 | boot_stats@6b0 { |
| 1142 | compatible = "qcom,msm-imem-boot_stats"; |
| 1143 | reg = <0x6b0 32>; |
| 1144 | }; |
| 1145 | |
| 1146 | pil@94c { |
| 1147 | compatible = "qcom,msm-imem-pil"; |
| 1148 | reg = <0x94c 200>; |
| 1149 | }; |
| 1150 | |
| 1151 | restart_reason@65c { |
| 1152 | compatible = "qcom,msm-imem-restart_reason"; |
| 1153 | reg = <0x65c 4>; |
| 1154 | }; |
| 1155 | }; |
| 1156 | |
| 1157 | qcom,mpm2-sleep-counter@4a3000 { |
| 1158 | compatible = "qcom,mpm2-sleep-counter"; |
| 1159 | reg = <0x4a3000 0x1000>; |
| 1160 | clock-frequency = <32768>; |
| 1161 | }; |
| 1162 | |
| 1163 | spi_0: spi@78ba000 { /* BLSP1 QUP6 */ |
| 1164 | compatible = "qcom,spi-qup-v2"; |
| 1165 | #address-cells = <1>; |
| 1166 | #size-cells = <0>; |
| 1167 | reg-names = "spi_physical", "spi_bam_physical"; |
| 1168 | reg = <0x78ba000 0x600>, |
| 1169 | <0x7884000 0x23000>; |
| 1170 | interrupt-names = "spi_irq", "spi_bam_irq"; |
| 1171 | interrupts = <0 100 0>, <0 238 0>; |
| 1172 | spi-max-frequency = <19200000>; |
| 1173 | pinctrl-names = "spi_default", "spi_sleep"; |
| 1174 | pinctrl-0 = <&spi0_default &spi0_cs0_active>; |
| 1175 | pinctrl-1 = <&spi0_sleep &spi0_cs0_sleep>; |
| 1176 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 1177 | <&clock_gcc clk_gcc_blsp1_qup6_spi_apps_clk>; |
| 1178 | clock-names = "iface_clk", "core_clk"; |
| 1179 | qcom,infinite-mode = <0>; |
| 1180 | qcom,use-bam; |
| 1181 | qcom,use-pinctrl; |
| 1182 | qcom,ver-reg-exists; |
| 1183 | qcom,bam-consumer-pipe-index = <14>; |
| 1184 | qcom,bam-producer-pipe-index = <15>; |
| 1185 | qcom,master-id = <86>; |
| 1186 | }; |
| 1187 | |
| 1188 | spi_2: spi@78b6000 { /* BLSP1 QUP2 */ |
| 1189 | compatible = "qcom,spi-qup-v2"; |
| 1190 | #address-cells = <1>; |
| 1191 | #size-cells = <0>; |
| 1192 | reg-names = "spi_physical", "spi_bam_physical"; |
| 1193 | reg = <0x78b6000 0x600>, |
| 1194 | <0x7884000 0x23000>; |
| 1195 | interrupt-names = "spi_irq", "spi_bam_irq"; |
| 1196 | interrupts = <0 96 0>, <0 238 0>; |
| 1197 | spi-max-frequency = <50000000>; |
| 1198 | pinctrl-names = "spi_default", "spi_sleep"; |
| 1199 | pinctrl-0 = <&spi2_default &spi2_cs0_active>; |
| 1200 | pinctrl-1 = <&spi2_sleep &spi2_cs0_sleep>; |
| 1201 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 1202 | <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>; |
| 1203 | clock-names = "iface_clk", "core_clk"; |
| 1204 | qcom,infinite-mode = <0>; |
| 1205 | qcom,use-bam; |
| 1206 | qcom,use-pinctrl; |
| 1207 | qcom,ver-reg-exists; |
| 1208 | qcom,bam-consumer-pipe-index = <6>; |
| 1209 | qcom,bam-producer-pipe-index = <7>; |
| 1210 | qcom,master-id = <86>; |
| 1211 | status = "disabled"; |
| 1212 | }; |
| 1213 | |
| 1214 | spi_4: spi@78B8000{ /* BLSP1 QUP4 */ |
| 1215 | compatible = "qcom,spi-qup-v2"; |
| 1216 | #address-cells = <1>; |
| 1217 | #size-cells = <0>; |
| 1218 | reg-names = "spi_physical", "spi_bam_physical"; |
| 1219 | reg = <0x78b8000 0x600>, |
| 1220 | <0x7884000 0x23000>; |
| 1221 | interrupt-names = "spi_irq", "spi_bam_irq"; |
| 1222 | interrupts = <0 98 0>, <0 238 0>; |
| 1223 | spi-max-frequency = <50000000>; |
| 1224 | pinctrl-names = "spi_default", "spi_sleep"; |
| 1225 | pinctrl-0 = <&spi4_default &spi4_cs0_active>; |
| 1226 | pinctrl-1 = <&spi4_sleep &spi4_cs0_sleep>; |
| 1227 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 1228 | <&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>; |
| 1229 | clock-names = "iface_clk", "core_clk"; |
| 1230 | qcom,infinite-mode = <0>; |
| 1231 | qcom,use-bam; |
| 1232 | qcom,use-pinctrl; |
| 1233 | qcom,ver-reg-exists; |
| 1234 | qcom,bam-consumer-pipe-index = <10>; |
| 1235 | qcom,bam-producer-pipe-index = <11>; |
| 1236 | qcom,master-id = <86>; |
| 1237 | status = "disabled"; |
| 1238 | }; |
| 1239 | |
| 1240 | dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */ |
| 1241 | #dma-cells = <4>; |
| 1242 | compatible = "qcom,sps-dma"; |
| 1243 | reg = <0x7884000 0x23000>; |
| 1244 | interrupts = <0 238 0>; |
| 1245 | qcom,summing-threshold = <10>; |
| 1246 | }; |
| 1247 | |
| 1248 | i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */ |
| 1249 | compatible = "qcom,i2c-msm-v2"; |
| 1250 | #address-cells = <1>; |
| 1251 | #size-cells = <0>; |
| 1252 | reg-names = "qup_phys_addr"; |
| 1253 | reg = <0x78b6000 0x1000>; |
| 1254 | interrupt-names = "qup_irq"; |
| 1255 | interrupts = <0 96 0>; |
| 1256 | qcom,clk-freq-out = <400000>; |
| 1257 | qcom,clk-freq-in = <19200000>; |
| 1258 | clock-names = "iface_clk", "core_clk"; |
| 1259 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 1260 | <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>; |
| 1261 | |
| 1262 | pinctrl-names = "i2c_active", "i2c_sleep"; |
| 1263 | pinctrl-0 = <&i2c_2_active>; |
| 1264 | pinctrl-1 = <&i2c_2_sleep>; |
| 1265 | qcom,noise-rjct-scl = <0>; |
| 1266 | qcom,noise-rjct-sda = <0>; |
| 1267 | dmas = <&dma_blsp1 6 64 0x20000020 0x20>, |
| 1268 | <&dma_blsp1 7 32 0x20000020 0x20>; |
| 1269 | dma-names = "tx", "rx"; |
| 1270 | qcom,master-id = <86>; |
| 1271 | }; |
| 1272 | |
| 1273 | i2c_4: i2c@78b8000 { /* BLSP1 QUP4 */ |
| 1274 | compatible = "qcom,i2c-msm-v2"; |
| 1275 | #address-cells = <1>; |
| 1276 | #size-cells = <0>; |
| 1277 | reg-names = "qup_phys_addr"; |
| 1278 | reg = <0x78b8000 0x1000>; |
| 1279 | interrupt-names = "qup_irq"; |
| 1280 | interrupts = <0 98 0>; |
| 1281 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 1282 | <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>; |
| 1283 | clock-names = "iface_clk", "core_clk"; |
| 1284 | qcom,clk-freq-out = <400000>; |
| 1285 | qcom,clk-freq-in = <19200000>; |
| 1286 | pinctrl-names = "i2c_active", "i2c_sleep"; |
| 1287 | pinctrl-0 = <&i2c_4_active>; |
| 1288 | pinctrl-1 = <&i2c_4_sleep>; |
| 1289 | qcom,noise-rjct-scl = <0>; |
| 1290 | qcom,noise-rjct-sda = <0>; |
| 1291 | dmas = <&dma_blsp1 10 64 0x20000020 0x20>, |
| 1292 | <&dma_blsp1 11 32 0x20000020 0x20>; |
| 1293 | dma-names = "tx", "rx"; |
| 1294 | qcom,master-id = <86>; |
| 1295 | }; |
| 1296 | |
| 1297 | i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */ |
| 1298 | compatible = "qcom,i2c-msm-v2"; |
| 1299 | #address-cells = <1>; |
| 1300 | #size-cells = <0>; |
| 1301 | reg-names = "qup_phys_addr"; |
| 1302 | reg = <0x78b9000 0x1000>; |
| 1303 | interrupt-names = "qup_irq"; |
| 1304 | interrupts = <0 99 0>; |
| 1305 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 1306 | <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>; |
| 1307 | clock-names = "iface_clk", "core_clk"; |
| 1308 | qcom,clk-freq-out = <100000>; |
| 1309 | qcom,clk-freq-in = <19200000>; |
| 1310 | pinctrl-names = "i2c_active", "i2c_sleep"; |
| 1311 | pinctrl-0 = <&i2c_5_active>; |
| 1312 | pinctrl-1 = <&i2c_5_sleep>; |
| 1313 | qcom,noise-rjct-scl = <0>; |
| 1314 | qcom,noise-rjct-sda = <0>; |
| 1315 | dmas = <&dma_blsp1 12 64 0x20000020 0x20>, |
| 1316 | <&dma_blsp1 13 32 0x20000020 0x20>; |
| 1317 | dma-names = "tx", "rx"; |
| 1318 | qcom,master-id = <86>; |
| 1319 | }; |
| 1320 | |
| 1321 | i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */ |
| 1322 | compatible = "qcom,i2c-msm-v2"; |
| 1323 | #address-cells = <1>; |
| 1324 | #size-cells = <0>; |
| 1325 | reg-names = "qup_phys_addr"; |
| 1326 | reg = <0x78b7000 0x1000>; |
| 1327 | interrupt-names = "qup_irq"; |
| 1328 | interrupts = <0 97 0>; |
| 1329 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 1330 | <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; |
| 1331 | clock-names = "iface_clk", "core_clk"; |
| 1332 | qcom,clk-freq-out = <100000>; |
| 1333 | qcom,clk-freq-in = <19200000>; |
| 1334 | pinctrl-names = "i2c_active", "i2c_sleep"; |
| 1335 | pinctrl-0 = <&i2c_3_active>; |
| 1336 | pinctrl-1 = <&i2c_3_sleep>; |
| 1337 | qcom,noise-rjct-scl = <0>; |
| 1338 | qcom,noise-rjct-sda = <0>; |
| 1339 | dmas = <&dma_blsp1 8 64 0x20000020 0x20>, |
| 1340 | <&dma_blsp1 9 32 0x20000020 0x20>; |
| 1341 | dma-names = "tx", "rx"; |
| 1342 | qcom,master-id = <86>; |
| 1343 | }; |
| 1344 | |
| 1345 | i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */ |
| 1346 | compatible = "qcom,i2c-msm-v2"; |
| 1347 | #address-cells = <1>; |
| 1348 | #size-cells = <0>; |
| 1349 | reg-names = "qup_phys_addr"; |
| 1350 | reg = <0x78b5000 0x1000>; |
| 1351 | interrupt-names = "qup_irq"; |
| 1352 | interrupts = <0 95 0>; |
| 1353 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 1354 | <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>; |
| 1355 | clock-names = "iface_clk", "core_clk"; |
zhaochen | 024979a | 2018-06-14 10:33:45 +0800 | [diff] [blame] | 1356 | qcom,clk-freq-out = <400000>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 1357 | qcom,clk-freq-in = <19200000>; |
| 1358 | pinctrl-names = "i2c_active", "i2c_sleep"; |
| 1359 | pinctrl-0 = <&i2c_1_active>; |
| 1360 | pinctrl-1 = <&i2c_1_sleep>; |
| 1361 | qcom,noise-rjct-scl = <0>; |
| 1362 | qcom,noise-rjct-sda = <0>; |
| 1363 | dmas = <&dma_blsp1 4 64 0x20000020 0x20>, |
| 1364 | <&dma_blsp1 5 32 0x20000020 0x20>; |
| 1365 | dma-names = "tx", "rx"; |
| 1366 | qcom,master-id = <86>; |
| 1367 | }; |
| 1368 | |
| 1369 | qcom,venus@1de0000 { |
| 1370 | compatible = "qcom,pil-tz-generic"; |
| 1371 | reg = <0x1de0000 0x4000>; |
| 1372 | |
| 1373 | vdd-supply = <&gdsc_venus>; |
| 1374 | qcom,proxy-reg-names = "vdd"; |
| 1375 | |
| 1376 | clocks = <&clock_gcc clk_gcc_venus0_vcodec0_clk>, |
| 1377 | <&clock_gcc clk_gcc_venus0_ahb_clk>, |
| 1378 | <&clock_gcc clk_gcc_venus0_axi_clk>, |
| 1379 | <&clock_gcc clk_gcc_crypto_clk>, |
| 1380 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 1381 | <&clock_gcc clk_gcc_crypto_axi_clk>, |
| 1382 | <&clock_gcc clk_crypto_clk_src>; |
| 1383 | |
| 1384 | clock-names = "core_clk", "iface_clk", "bus_clk", |
| 1385 | "scm_core_clk", "scm_iface_clk", |
| 1386 | "scm_bus_clk", "scm_core_clk_src"; |
| 1387 | |
| 1388 | qcom,proxy-clock-names = "core_clk", "iface_clk", |
| 1389 | "bus_clk", "scm_core_clk", |
| 1390 | "scm_iface_clk", "scm_bus_clk", |
| 1391 | "scm_core_clk_src"; |
| 1392 | qcom,scm_core_clk_src-freq = <80000000>; |
| 1393 | |
| 1394 | qcom,pas-id = <9>; |
Ramesh Yadav Javadi | c12bbb1 | 2018-03-27 15:00:05 +0530 | [diff] [blame] | 1395 | qcom,mas-crypto = <&mas_crypto>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 1396 | qcom,proxy-timeout-ms = <100>; |
| 1397 | qcom,firmware-name = "venus"; |
| 1398 | memory-region = <&venus_qseecom_mem>; |
| 1399 | }; |
| 1400 | |
| 1401 | pcm0: qcom,msm-pcm { |
| 1402 | compatible = "qcom,msm-pcm-dsp"; |
| 1403 | qcom,msm-pcm-dsp-id = <0>; |
| 1404 | }; |
| 1405 | |
| 1406 | routing: qcom,msm-pcm-routing { |
| 1407 | compatible = "qcom,msm-pcm-routing"; |
| 1408 | }; |
| 1409 | |
| 1410 | pcm1: qcom,msm-pcm-low-latency { |
| 1411 | compatible = "qcom,msm-pcm-dsp"; |
| 1412 | qcom,msm-pcm-dsp-id = <1>; |
| 1413 | qcom,msm-pcm-low-latency; |
| 1414 | qcom,latency-level = "regular"; |
| 1415 | }; |
| 1416 | |
| 1417 | pcm2: qcom,msm-ultra-low-latency { |
| 1418 | compatible = "qcom,msm-pcm-dsp"; |
| 1419 | qcom,msm-pcm-dsp-id = <2>; |
| 1420 | qcom,msm-pcm-low-latency; |
| 1421 | qcom,latency-level = "ultra"; |
| 1422 | }; |
| 1423 | |
| 1424 | lpa: qcom,msm-pcm-lpa { |
| 1425 | compatible = "qcom,msm-pcm-lpa"; |
| 1426 | }; |
| 1427 | |
| 1428 | compress: qcom,msm-compress-dsp { |
| 1429 | compatible = "qcom,msm-compress-dsp"; |
| 1430 | }; |
| 1431 | |
| 1432 | voip: qcom,msm-voip-dsp { |
| 1433 | compatible = "qcom,msm-voip-dsp"; |
| 1434 | }; |
| 1435 | |
| 1436 | voice: qcom,msm-pcm-voice { |
| 1437 | compatible = "qcom,msm-pcm-voice"; |
| 1438 | qcom,destroy-cvd; |
| 1439 | qcom,vote-bms; |
| 1440 | }; |
| 1441 | |
| 1442 | stub_codec: qcom,msm-stub-codec { |
| 1443 | compatible = "qcom,msm-stub-codec"; |
| 1444 | }; |
| 1445 | |
| 1446 | qcom,msm-dai-fe { |
| 1447 | compatible = "qcom,msm-dai-fe"; |
| 1448 | }; |
| 1449 | |
| 1450 | afe: qcom,msm-pcm-afe { |
| 1451 | compatible = "qcom,msm-pcm-afe"; |
| 1452 | }; |
| 1453 | |
| 1454 | voice_svc: qcom,msm-voice-svc { |
| 1455 | compatible = "qcom,msm-voice-svc"; |
| 1456 | }; |
| 1457 | |
| 1458 | loopback: qcom,msm-pcm-loopback { |
| 1459 | compatible = "qcom,msm-pcm-loopback"; |
| 1460 | }; |
| 1461 | |
| 1462 | qcom,msm-dai-mi2s { |
| 1463 | compatible = "qcom,msm-dai-mi2s"; |
| 1464 | dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { |
| 1465 | compatible = "qcom,msm-dai-q6-mi2s"; |
| 1466 | qcom,msm-dai-q6-mi2s-dev-id = <0>; |
| 1467 | qcom,msm-mi2s-rx-lines = <3>; |
| 1468 | qcom,msm-mi2s-tx-lines = <0>; |
| 1469 | }; |
| 1470 | |
| 1471 | dai_mi2s1: qcom,msm-dai-q6-mi2s-sec { |
| 1472 | compatible = "qcom,msm-dai-q6-mi2s"; |
| 1473 | qcom,msm-dai-q6-mi2s-dev-id = <1>; |
| 1474 | qcom,msm-mi2s-rx-lines = <1>; |
| 1475 | qcom,msm-mi2s-tx-lines = <0>; |
| 1476 | }; |
| 1477 | |
| 1478 | dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { |
| 1479 | compatible = "qcom,msm-dai-q6-mi2s"; |
| 1480 | qcom,msm-dai-q6-mi2s-dev-id = <3>; |
| 1481 | qcom,msm-mi2s-rx-lines = <0>; |
| 1482 | qcom,msm-mi2s-tx-lines = <3>; |
| 1483 | }; |
| 1484 | |
| 1485 | dai_mi2s5: qcom,msm-dai-q6-mi2s-quin { |
| 1486 | compatible = "qcom,msm-dai-q6-mi2s"; |
| 1487 | qcom,msm-dai-q6-mi2s-dev-id = <5>; |
| 1488 | qcom,msm-mi2s-rx-lines = <1>; |
| 1489 | qcom,msm-mi2s-tx-lines = <2>; |
| 1490 | }; |
| 1491 | |
| 1492 | dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { |
| 1493 | compatible = "qcom,msm-dai-q6-mi2s"; |
| 1494 | qcom,msm-dai-q6-mi2s-dev-id = <2>; |
| 1495 | qcom,msm-mi2s-rx-lines = <0>; |
| 1496 | qcom,msm-mi2s-tx-lines = <3>; |
| 1497 | }; |
| 1498 | |
| 1499 | dai_mi2s6: qcom,msm-dai-q6-mi2s-senary { |
| 1500 | compatible = "qcom,msm-dai-q6-mi2s"; |
| 1501 | qcom,msm-dai-q6-mi2s-dev-id = <6>; |
| 1502 | qcom,msm-mi2s-rx-lines = <0>; |
| 1503 | qcom,msm-mi2s-tx-lines = <3>; |
| 1504 | }; |
| 1505 | }; |
| 1506 | |
| 1507 | dai_hdmi: qcom,msm-dai-q6-hdmi { |
| 1508 | compatible = "qcom,msm-dai-q6-hdmi"; |
| 1509 | qcom,msm-dai-q6-dev-id = <8>; |
| 1510 | }; |
| 1511 | |
| 1512 | lsm: qcom,msm-lsm-client { |
| 1513 | compatible = "qcom,msm-lsm-client"; |
| 1514 | }; |
| 1515 | |
| 1516 | qcom,msm-dai-q6 { |
| 1517 | compatible = "qcom,msm-dai-q6"; |
| 1518 | sb_0_rx: qcom,msm-dai-q6-sb-0-rx { |
| 1519 | compatible = "qcom,msm-dai-q6-dev"; |
| 1520 | qcom,msm-dai-q6-dev-id = <16384>; |
| 1521 | }; |
| 1522 | |
| 1523 | sb_0_tx: qcom,msm-dai-q6-sb-0-tx { |
| 1524 | compatible = "qcom,msm-dai-q6-dev"; |
| 1525 | qcom,msm-dai-q6-dev-id = <16385>; |
| 1526 | }; |
| 1527 | |
| 1528 | sb_1_rx: qcom,msm-dai-q6-sb-1-rx { |
| 1529 | compatible = "qcom,msm-dai-q6-dev"; |
| 1530 | qcom,msm-dai-q6-dev-id = <16386>; |
| 1531 | }; |
| 1532 | |
| 1533 | sb_1_tx: qcom,msm-dai-q6-sb-1-tx { |
| 1534 | compatible = "qcom,msm-dai-q6-dev"; |
| 1535 | qcom,msm-dai-q6-dev-id = <16387>; |
| 1536 | }; |
| 1537 | |
| 1538 | sb_3_rx: qcom,msm-dai-q6-sb-3-rx { |
| 1539 | compatible = "qcom,msm-dai-q6-dev"; |
| 1540 | qcom,msm-dai-q6-dev-id = <16390>; |
| 1541 | }; |
| 1542 | |
| 1543 | sb_3_tx: qcom,msm-dai-q6-sb-3-tx { |
| 1544 | compatible = "qcom,msm-dai-q6-dev"; |
| 1545 | qcom,msm-dai-q6-dev-id = <16391>; |
| 1546 | }; |
| 1547 | |
| 1548 | sb_4_rx: qcom,msm-dai-q6-sb-4-rx { |
| 1549 | compatible = "qcom,msm-dai-q6-dev"; |
| 1550 | qcom,msm-dai-q6-dev-id = <16392>; |
| 1551 | }; |
| 1552 | |
| 1553 | sb_4_tx: qcom,msm-dai-q6-sb-4-tx { |
| 1554 | compatible = "qcom,msm-dai-q6-dev"; |
| 1555 | qcom,msm-dai-q6-dev-id = <16393>; |
| 1556 | }; |
| 1557 | |
| 1558 | bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx { |
| 1559 | compatible = "qcom,msm-dai-q6-dev"; |
| 1560 | qcom,msm-dai-q6-dev-id = <12288>; |
| 1561 | }; |
| 1562 | |
| 1563 | bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx { |
| 1564 | compatible = "qcom,msm-dai-q6-dev"; |
| 1565 | qcom,msm-dai-q6-dev-id = <12289>; |
| 1566 | }; |
| 1567 | |
| 1568 | bt_a2dp_rx: qcom,msm-dai-q6-bt-a2dp-rx { |
| 1569 | compatible = "qcom,msm-dai-q6-dev"; |
| 1570 | qcom,msm-dai-q6-dev-id = <12290>; |
| 1571 | }; |
| 1572 | |
| 1573 | int_fm_rx: qcom,msm-dai-q6-int-fm-rx { |
| 1574 | compatible = "qcom,msm-dai-q6-dev"; |
| 1575 | qcom,msm-dai-q6-dev-id = <12292>; |
| 1576 | }; |
| 1577 | |
| 1578 | int_fm_tx: qcom,msm-dai-q6-int-fm-tx { |
| 1579 | compatible = "qcom,msm-dai-q6-dev"; |
| 1580 | qcom,msm-dai-q6-dev-id = <12293>; |
| 1581 | }; |
| 1582 | |
| 1583 | afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx { |
| 1584 | compatible = "qcom,msm-dai-q6-dev"; |
| 1585 | qcom,msm-dai-q6-dev-id = <224>; |
| 1586 | }; |
| 1587 | |
| 1588 | afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx { |
| 1589 | compatible = "qcom,msm-dai-q6-dev"; |
| 1590 | qcom,msm-dai-q6-dev-id = <225>; |
| 1591 | }; |
| 1592 | |
| 1593 | afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx { |
| 1594 | compatible = "qcom,msm-dai-q6-dev"; |
| 1595 | qcom,msm-dai-q6-dev-id = <241>; |
| 1596 | }; |
| 1597 | |
| 1598 | afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx { |
| 1599 | compatible = "qcom,msm-dai-q6-dev"; |
| 1600 | qcom,msm-dai-q6-dev-id = <240>; |
| 1601 | }; |
| 1602 | |
| 1603 | afe_loopback_tx: qcom,msm-dai-q6-afe-loopback-tx { |
| 1604 | compatible = "qcom,msm-dai-q6-dev"; |
| 1605 | qcom,msm-dai-q6-dev-id = <24577>; |
| 1606 | }; |
| 1607 | |
| 1608 | incall_record_rx: qcom,msm-dai-q6-incall-record-rx { |
| 1609 | compatible = "qcom,msm-dai-q6-dev"; |
| 1610 | qcom,msm-dai-q6-dev-id = <32771>; |
| 1611 | }; |
| 1612 | |
| 1613 | incall_record_tx: qcom,msm-dai-q6-incall-record-tx { |
| 1614 | compatible = "qcom,msm-dai-q6-dev"; |
| 1615 | qcom,msm-dai-q6-dev-id = <32772>; |
| 1616 | }; |
| 1617 | |
| 1618 | incall_music_rx: qcom,msm-dai-q6-incall-music-rx { |
| 1619 | compatible = "qcom,msm-dai-q6-dev"; |
| 1620 | qcom,msm-dai-q6-dev-id = <32773>; |
| 1621 | }; |
| 1622 | |
| 1623 | incall_music_2_rx: qcom,msm-dai-q6-incall-music-2-rx { |
| 1624 | compatible = "qcom,msm-dai-q6-dev"; |
| 1625 | qcom,msm-dai-q6-dev-id = <32770>; |
| 1626 | }; |
| 1627 | }; |
| 1628 | |
| 1629 | hostless: qcom,msm-pcm-hostless { |
| 1630 | compatible = "qcom,msm-pcm-hostless"; |
| 1631 | }; |
| 1632 | |
| 1633 | dai_pri_auxpcm: qcom,msm-pri-auxpcm { |
| 1634 | compatible = "qcom,msm-auxpcm-dev"; |
| 1635 | qcom,msm-cpudai-auxpcm-mode = <0>, <0>; |
| 1636 | qcom,msm-cpudai-auxpcm-sync = <1>, <1>; |
| 1637 | qcom,msm-cpudai-auxpcm-frame = <5>, <4>; |
| 1638 | qcom,msm-cpudai-auxpcm-quant = <2>, <2>; |
| 1639 | qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; |
| 1640 | qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; |
| 1641 | qcom,msm-cpudai-auxpcm-data = <0>, <0>; |
| 1642 | qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; |
| 1643 | qcom,msm-auxpcm-interface = "primary"; |
| 1644 | }; |
| 1645 | |
| 1646 | qcom,msm-audio-ion { |
| 1647 | compatible = "qcom,msm-audio-ion"; |
| 1648 | }; |
| 1649 | |
| 1650 | qcom,mdsprpc-mem { |
| 1651 | compatible = "qcom,msm-mdsprpc-mem-region"; |
| 1652 | memory-region = <&adsp_mem>; |
| 1653 | }; |
| 1654 | |
Tharun Kumar Merugu | d444799 | 2018-03-29 00:23:37 +0530 | [diff] [blame] | 1655 | qcom,msm-adsprpc-mem { |
| 1656 | compatible = "qcom,msm-adsprpc-mem-region"; |
| 1657 | memory-region = <&adsp_mem>; |
| 1658 | restrict-access; |
| 1659 | }; |
| 1660 | |
| 1661 | qcom,msm_fastrpc { |
| 1662 | compatible = "qcom,msm-fastrpc-legacy-compute"; |
| 1663 | }; |
| 1664 | |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 1665 | qcom,msm-adsp-loader { |
| 1666 | compatible = "qcom,adsp-loader"; |
| 1667 | qcom,adsp-state = <0>; |
| 1668 | qcom,proc-img-to-load = "modem"; |
| 1669 | }; |
| 1670 | |
| 1671 | qcom,avtimer@770600c { |
| 1672 | compatible = "qcom,avtimer"; |
| 1673 | reg = <0x0770600C 0x4>, |
| 1674 | <0x07706010 0x4>; |
| 1675 | reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; |
| 1676 | qcom,clk-div = <27>; |
| 1677 | }; |
| 1678 | |
| 1679 | qcom,memshare { |
| 1680 | compatible = "qcom,memshare"; |
| 1681 | |
| 1682 | qcom,client_1 { |
| 1683 | compatible = "qcom,memshare-peripheral"; |
| 1684 | qcom,peripheral-size = <0x200000>; |
| 1685 | qcom,client-id = <0>; |
| 1686 | qcom,allocate-boot-time; |
| 1687 | label = "modem"; |
| 1688 | }; |
| 1689 | |
| 1690 | qcom,client_2 { |
| 1691 | compatible = "qcom,memshare-peripheral"; |
| 1692 | qcom,peripheral-size = <0x300000>; |
| 1693 | qcom,client-id = <2>; |
| 1694 | label = "modem"; |
| 1695 | }; |
| 1696 | |
| 1697 | qcom,client_3 { |
| 1698 | compatible = "qcom,memshare-peripheral"; |
| 1699 | qcom,peripheral-size = <0>; |
| 1700 | qcom,client-id = <1>; |
| 1701 | label = "modem"; |
| 1702 | }; |
| 1703 | }; |
| 1704 | |
| 1705 | |
| 1706 | qcom_tzlog: tz-log@8600720 { |
| 1707 | compatible = "qcom,tz-log"; |
| 1708 | reg = <0x08600720 0x1000>; |
| 1709 | status = "disabled"; |
| 1710 | }; |
| 1711 | |
| 1712 | qcom_rng: qrng@22000 { |
| 1713 | compatible = "qcom,msm-rng"; |
| 1714 | reg = <0x22000 0x200>; |
| 1715 | qcom,msm-rng-iface-clk; |
| 1716 | qcom,msm-bus,name = "msm-rng-noc"; |
| 1717 | qcom,msm-bus,num-cases = <2>; |
| 1718 | qcom,msm-bus,num-paths = <1>; |
| 1719 | qcom,msm-bus,vectors-KBps = |
| 1720 | <1 618 0 0>, /* No vote */ |
| 1721 | <1 618 0 800>; /* 100 MB/s */ |
| 1722 | clocks = <&clock_gcc clk_gcc_prng_ahb_clk>; |
| 1723 | clock-names = "iface_clk"; |
| 1724 | status = "disabled"; |
| 1725 | }; |
| 1726 | |
| 1727 | qcom_crypto: qcrypto@720000 { |
| 1728 | compatible = "qcom,qcrypto"; |
| 1729 | reg = <0x720000 0x20000>, |
| 1730 | <0x704000 0x20000>; |
| 1731 | reg-names = "crypto-base","crypto-bam-base"; |
| 1732 | interrupts = <0 207 0>; |
| 1733 | qcom,bam-pipe-pair = <2>; |
| 1734 | qcom,ce-hw-instance = <0>; |
| 1735 | qcom,ce-device = <0>; |
| 1736 | qcom,clk-mgmt-sus-res; |
| 1737 | qcom,msm-bus,name = "qcrypto-noc"; |
| 1738 | qcom,msm-bus,num-cases = <2>; |
| 1739 | qcom,msm-bus,num-paths = <1>; |
| 1740 | qcom,msm-bus,vectors-KBps = |
| 1741 | <55 512 0 0>, |
| 1742 | <55 512 393600 800000>; /* 49.2MHz & 100MHz */ |
| 1743 | clocks = <&clock_gcc clk_crypto_clk_src>, |
| 1744 | <&clock_gcc clk_gcc_crypto_clk>, |
| 1745 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 1746 | <&clock_gcc clk_gcc_crypto_axi_clk>; |
| 1747 | clock-names = "core_clk_src", "core_clk", |
| 1748 | "iface_clk", "bus_clk"; |
| 1749 | qcom,use-sw-aes-cbc-ecb-ctr-algo; |
| 1750 | qcom,use-sw-aes-xts-algo; |
| 1751 | qcom,use-sw-ahash-algo; |
| 1752 | status = "disabled"; |
| 1753 | qcom,ce-opp-freq = <100000000>; |
| 1754 | }; |
| 1755 | |
| 1756 | qcom_cedev: qcedev@720000 { |
| 1757 | compatible = "qcom,qcedev"; |
| 1758 | reg = <0x720000 0x20000>, |
| 1759 | <0x704000 0x20000>; |
| 1760 | reg-names = "crypto-base","crypto-bam-base"; |
| 1761 | interrupts = <0 207 0>; |
| 1762 | qcom,bam-pipe-pair = <1>; |
| 1763 | qcom,ce-hw-instance = <0>; |
| 1764 | qcom,ce-device = <0>; |
| 1765 | qcom,ce-hw-shared; |
| 1766 | qcom,msm-bus,name = "qcedev-noc"; |
| 1767 | qcom,msm-bus,num-cases = <2>; |
| 1768 | qcom,msm-bus,num-paths = <1>; |
| 1769 | qcom,msm-bus,vectors-KBps = |
| 1770 | <55 512 0 0>, |
| 1771 | <55 512 3936000 393600>; |
| 1772 | clocks = <&clock_gcc clk_crypto_clk_src>, |
| 1773 | <&clock_gcc clk_gcc_crypto_clk>, |
| 1774 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 1775 | <&clock_gcc clk_gcc_crypto_axi_clk>; |
| 1776 | clock-names = "core_clk_src", "core_clk", |
| 1777 | "iface_clk", "bus_clk"; |
| 1778 | status = "disabled"; |
| 1779 | qcom,ce-opp-freq = <100000000>; |
| 1780 | }; |
| 1781 | |
| 1782 | qcom_seecom: qseecom@87a00000 { |
| 1783 | compatible = "qcom,qseecom"; |
| 1784 | reg = <0x87a00000 0x200000>; |
| 1785 | reg-names = "secapp-region"; |
| 1786 | qcom,disk-encrypt-pipe-pair = <2>; |
| 1787 | qcom,hlos-ce-hw-instance = <0>; |
| 1788 | qcom,qsee-ce-hw-instance = <0>; |
| 1789 | qcom,msm-bus,name = "qseecom-noc"; |
| 1790 | qcom,msm-bus,num-cases = <4>; |
| 1791 | qcom,msm-bus,num-paths = <1>; |
| 1792 | qcom,support-bus-scaling; |
| 1793 | qcom,support-fde; |
| 1794 | qcom,msm-bus,vectors-KBps = |
| 1795 | <55 512 0 0>, |
| 1796 | <55 512 0 0>, |
| 1797 | <55 512 120000 1200000>, |
| 1798 | <55 512 393600 3936000>; |
| 1799 | clocks = <&clock_gcc clk_crypto_clk_src>, |
| 1800 | <&clock_gcc clk_gcc_crypto_clk>, |
| 1801 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 1802 | <&clock_gcc clk_gcc_crypto_axi_clk>; |
| 1803 | clock-names = "core_clk_src", "core_clk", |
| 1804 | "iface_clk", "bus_clk"; |
| 1805 | status = "disabled"; |
| 1806 | qcom,ce-opp-freq = <100000000>; |
| 1807 | }; |
| 1808 | |
| 1809 | qcom,pronto@a21b000 { |
| 1810 | compatible = "qcom,pil-tz-generic"; |
| 1811 | reg = <0x0a21b000 0x3000>; |
| 1812 | interrupts = <0 149 1>; |
| 1813 | |
| 1814 | vdd_pronto_pll-supply = <&pm8909_l7>; |
| 1815 | proxy-reg-names = "vdd_pronto_pll"; |
| 1816 | vdd_pronto_pll-uV-uA = <1800000 18000>; |
| 1817 | clocks = <&clock_rpm clk_xo_pil_pronto_clk>, |
| 1818 | <&clock_gcc clk_gcc_crypto_clk>, |
| 1819 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 1820 | <&clock_gcc clk_gcc_crypto_axi_clk>, |
| 1821 | <&clock_gcc clk_crypto_clk_src>; |
| 1822 | |
| 1823 | clock-names = "xo", "scm_core_clk", "scm_iface_clk", |
| 1824 | "scm_bus_clk", "scm_core_clk_src"; |
| 1825 | qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", |
| 1826 | "scm_bus_clk", "scm_core_clk_src"; |
| 1827 | qcom,scm_core_clk_src = <80000000>; |
| 1828 | |
| 1829 | qcom,pas-id = <6>; |
| 1830 | qcom,proxy-timeout-ms = <10000>; |
| 1831 | qcom,smem-id = <422>; |
| 1832 | qcom,sysmon-id = <6>; |
| 1833 | qcom,ssctl-instance-id = <0x13>; |
| 1834 | qcom,firmware-name = "wcnss"; |
Ramesh Yadav Javadi | c12bbb1 | 2018-03-27 15:00:05 +0530 | [diff] [blame] | 1835 | qcom,mas-crypto = <&mas_crypto>; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 1836 | |
| 1837 | /* GPIO inputs from wcnss */ |
| 1838 | qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>; |
| 1839 | qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>; |
| 1840 | qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>; |
| 1841 | qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_4_in 3 0>; |
| 1842 | |
| 1843 | /* GPIO output to wcnss */ |
| 1844 | qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>; |
| 1845 | memory-region = <&peripheral_mem>; |
| 1846 | }; |
| 1847 | |
| 1848 | qcom,mss@4080000 { |
| 1849 | compatible = "qcom,pil-q6v55-mss"; |
| 1850 | reg = <0x04080000 0x100>, |
| 1851 | <0x0194f000 0x010>, |
| 1852 | <0x01950000 0x008>, |
| 1853 | <0x01951000 0x008>, |
| 1854 | <0x04020000 0x040>, |
| 1855 | <0x0183e000 0x004>; |
| 1856 | reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", |
| 1857 | "rmb_base", "restart_reg"; |
| 1858 | |
| 1859 | interrupts = <0 24 1>; |
| 1860 | vdd_cx-supply = <&pm8909_s1_corner>; |
| 1861 | vdd_cx-voltage = <7>; |
| 1862 | vdd_mx-supply = <&pm8909_l3_corner_ao>; |
| 1863 | vdd_mx-uV = <3>; |
| 1864 | vdd_pll-supply = <&pm8909_l7>; |
| 1865 | qcom,vdd_pll = <1800000>; |
| 1866 | |
| 1867 | clocks = <&clock_rpm clk_xo_pil_mss_clk>, |
| 1868 | <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, |
| 1869 | <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, |
| 1870 | <&clock_gcc clk_gcc_boot_rom_ahb_clk>; |
| 1871 | clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; |
| 1872 | qcom,proxy-clock-names = "xo"; |
| 1873 | qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; |
| 1874 | |
| 1875 | qcom,firmware-name = "modem"; |
| 1876 | qcom,pil-self-auth; |
| 1877 | qcom,sysmon-id = <0>; |
| 1878 | qcom,ssctl-instance-id = <0x12>; |
Ramesh Yadav Javadi | 8801aa5 | 2018-03-27 15:11:18 +0530 | [diff] [blame] | 1879 | qcom,reset-clk; |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 1880 | |
| 1881 | /* GPIO inputs from mss */ |
| 1882 | qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; |
| 1883 | qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; |
| 1884 | qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; |
| 1885 | qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; |
| 1886 | |
| 1887 | /* GPIO output to mss */ |
| 1888 | qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; |
| 1889 | memory-region = <&modem_adsp_mem>; |
| 1890 | }; |
| 1891 | |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 1892 | cpu0_slp_sts: cpu-sleep-status@b088008 { |
| 1893 | reg = <0xb088008 0x100>; |
| 1894 | qcom,sleep-status-mask= <0x80000>; |
| 1895 | }; |
| 1896 | |
| 1897 | cpu1_slp_sts: cpu-sleep-status@b098008 { |
| 1898 | reg = <0xb098008 0x100>; |
| 1899 | qcom,sleep-status-mask= <0x80000>; |
| 1900 | }; |
| 1901 | |
| 1902 | cpu2_slp_sts: cpu-sleep-status@b0a8008 { |
| 1903 | reg = <0xb0a8008 0x100>; |
| 1904 | qcom,sleep-status-mask= <0x80000>; |
| 1905 | }; |
| 1906 | |
| 1907 | cpu3_slp_sts: cpu-sleep-status@b0b8008 { |
| 1908 | reg = <0xb0b8008 0x100>; |
| 1909 | qcom,sleep-status-mask= <0x80000>; |
| 1910 | }; |
| 1911 | }; |
| 1912 | |
| 1913 | &gdsc_venus { |
| 1914 | clock-names = "bus_clk", "core_clk"; |
| 1915 | clocks = <&clock_gcc clk_gcc_venus0_axi_clk>, |
| 1916 | <&clock_gcc clk_gcc_venus0_vcodec0_clk>; |
| 1917 | status = "okay"; |
| 1918 | }; |
| 1919 | |
| 1920 | &gdsc_venus_core0 { |
| 1921 | qcom,support-hw-trigger; |
| 1922 | clock-names = "core0_clk"; |
| 1923 | clocks = <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>; |
| 1924 | status = "okay"; |
| 1925 | }; |
| 1926 | |
| 1927 | &gdsc_mdss { |
| 1928 | clock-names = "core_clk", "bus_clk"; |
| 1929 | clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, |
| 1930 | <&clock_gcc clk_gcc_mdss_axi_clk>; |
| 1931 | status = "okay"; |
| 1932 | }; |
| 1933 | |
| 1934 | &gdsc_vfe { |
| 1935 | clock-names = "core_clk", "bus_clk", "csi_clk"; |
| 1936 | clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>, |
| 1937 | <&clock_gcc clk_gcc_camss_vfe_axi_clk>, |
| 1938 | <&clock_gcc clk_gcc_camss_csi_vfe0_clk>; |
| 1939 | status = "okay"; |
| 1940 | }; |
| 1941 | |
| 1942 | &gdsc_oxili_gx { |
| 1943 | clock-names = "core_clk"; |
| 1944 | clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>; |
| 1945 | status = "okay"; |
| 1946 | }; |
Chinkit Kumar,Kirti Kumar Parmar | 9e97ded | 2018-06-01 22:44:58 +0530 | [diff] [blame] | 1947 | #include "msm8909-thermal.dtsi" |