blob: 206e782e2daaf5c9bfc0964169a408a3ed92aed1 [file] [log] [blame]
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __PINCTRL_MSM_H__
14#define __PINCTRL_MSM_H__
15
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/machine.h>
20
21/**
22 * struct msm_function - a pinmux function
23 * @name: Name of the pinmux function.
24 * @groups: List of pingroups for this function.
25 * @ngroups: Number of entries in @groups.
26 */
27struct msm_function {
28 const char *name;
29 const char * const *groups;
30 unsigned ngroups;
31};
32
33/**
34 * struct msm_pingroup - Qualcomm pingroup definition
35 * @name: Name of the pingroup.
36 * @pins: A list of pins assigned to this pingroup.
37 * @npins: Number of entries in @pins.
38 * @funcs: A list of pinmux functions that can be selected for
39 * this group. The index of the selected function is used
40 * for programming the function selector.
41 * Entries should be indices into the groups list of the
42 * struct msm_pinctrl_soc_data.
43 * @ctl_reg: Offset of the register holding control bits for this group.
44 * @io_reg: Offset of the register holding input/output bits for this group.
45 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
46 * @intr_status_reg: Offset of the register holding the status bits for this group.
47 * @intr_target_reg: Offset of the register specifying routing of the interrupts
48 * from this group.
49 * @mux_bit: Offset in @ctl_reg for the pinmux function selection.
50 * @pull_bit: Offset in @ctl_reg for the bias configuration.
51 * @drv_bit: Offset in @ctl_reg for the drive strength configuration.
52 * @oe_bit: Offset in @ctl_reg for controlling output enable.
53 * @in_bit: Offset in @io_reg for the input bit value.
54 * @out_bit: Offset in @io_reg for the output bit value.
55 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
56 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
57 * status.
58 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
59 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
60 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
61 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
62 * @intr_detection_width: Number of bits used for specifying interrupt type,
63 * Should be 2 for SoCs that can detect both edges in hardware,
64 * otherwise 1.
65 */
66struct msm_pingroup {
67 const char *name;
68 const unsigned *pins;
69 unsigned npins;
70
71 unsigned funcs[8];
72
73 s16 ctl_reg;
74 s16 io_reg;
75 s16 intr_cfg_reg;
76 s16 intr_status_reg;
77 s16 intr_target_reg;
78
79 unsigned mux_bit:5;
80
81 unsigned pull_bit:5;
82 unsigned drv_bit:5;
83
84 unsigned oe_bit:5;
85 unsigned in_bit:5;
86 unsigned out_bit:5;
87
88 unsigned intr_enable_bit:5;
89 unsigned intr_status_bit:5;
90
91 unsigned intr_target_bit:5;
92 unsigned intr_raw_status_bit:5;
93 unsigned intr_polarity_bit:5;
94 unsigned intr_detection_bit:5;
95 unsigned intr_detection_width:5;
96};
97
98/**
99 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
100 * @pins: An array describing all pins the pin controller affects.
101 * @npins: The number of entries in @pins.
102 * @functions: An array describing all mux functions the SoC supports.
103 * @nfunctions: The number of entries in @functions.
104 * @groups: An array describing all pin groups the pin SoC supports.
105 * @ngroups: The numbmer of entries in @groups.
106 * @ngpio: The number of pingroups the driver should expose as GPIOs.
107 */
108struct msm_pinctrl_soc_data {
109 const struct pinctrl_pin_desc *pins;
110 unsigned npins;
111 const struct msm_function *functions;
112 unsigned nfunctions;
113 const struct msm_pingroup *groups;
114 unsigned ngroups;
115 unsigned ngpios;
116};
117
118int msm_pinctrl_probe(struct platform_device *pdev,
119 const struct msm_pinctrl_soc_data *soc_data);
120int msm_pinctrl_remove(struct platform_device *pdev);
121
122#endif