Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Maxime Ripard |
| 3 | * |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 5 | * |
Maxime Ripard | 6c3ba72 | 2014-09-02 19:25:26 +0200 | [diff] [blame] | 6 | * This file is dual-licensed: you can use it either under the terms |
| 7 | * of the GPL or the X11 license, at your option. Note that this dual |
| 8 | * licensing only applies to this file, and not this project as a |
| 9 | * whole. |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 10 | * |
Maxime Ripard | 5186d83 | 2014-10-17 11:38:23 +0200 | [diff] [blame] | 11 | * a) This file is free software; you can redistribute it and/or |
Maxime Ripard | 6c3ba72 | 2014-09-02 19:25:26 +0200 | [diff] [blame] | 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of the |
| 14 | * License, or (at your option) any later version. |
| 15 | * |
Maxime Ripard | 5186d83 | 2014-10-17 11:38:23 +0200 | [diff] [blame] | 16 | * This file is distributed in the hope that it will be useful, |
Maxime Ripard | 6c3ba72 | 2014-09-02 19:25:26 +0200 | [diff] [blame] | 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public |
Maxime Ripard | 5186d83 | 2014-10-17 11:38:23 +0200 | [diff] [blame] | 22 | * License along with this file; if not, write to the Free |
Maxime Ripard | 6c3ba72 | 2014-09-02 19:25:26 +0200 | [diff] [blame] | 23 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 24 | * MA 02110-1301 USA |
| 25 | * |
| 26 | * Or, alternatively, |
| 27 | * |
| 28 | * b) Permission is hereby granted, free of charge, to any person |
| 29 | * obtaining a copy of this software and associated documentation |
| 30 | * files (the "Software"), to deal in the Software without |
| 31 | * restriction, including without limitation the rights to use, |
| 32 | * copy, modify, merge, publish, distribute, sublicense, and/or |
| 33 | * sell copies of the Software, and to permit persons to whom the |
| 34 | * Software is furnished to do so, subject to the following |
| 35 | * conditions: |
| 36 | * |
| 37 | * The above copyright notice and this permission notice shall be |
| 38 | * included in all copies or substantial portions of the Software. |
| 39 | * |
| 40 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| 42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| 44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| 45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 47 | * OTHER DEALINGS IN THE SOFTWARE. |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 48 | */ |
| 49 | |
Maxime Ripard | 7145570 | 2014-12-16 22:59:54 +0100 | [diff] [blame] | 50 | #include "skeleton.dtsi" |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 51 | |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 52 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 53 | |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 54 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
| 55 | |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 56 | / { |
| 57 | interrupt-parent = <&gic>; |
| 58 | |
Maxime Ripard | 54428d4 | 2014-01-02 22:05:04 +0100 | [diff] [blame] | 59 | aliases { |
| 60 | serial0 = &uart0; |
| 61 | serial1 = &uart1; |
| 62 | serial2 = &uart2; |
| 63 | serial3 = &uart3; |
| 64 | serial4 = &uart4; |
| 65 | serial5 = &uart5; |
Chen-Yu Tsai | e5073fd | 2014-07-16 01:15:46 +0800 | [diff] [blame] | 66 | ethernet0 = &gmac; |
Maxime Ripard | 54428d4 | 2014-01-02 22:05:04 +0100 | [diff] [blame] | 67 | }; |
| 68 | |
Hans de Goede | e53a8b2 | 2014-11-14 16:34:36 +0100 | [diff] [blame] | 69 | chosen { |
| 70 | #address-cells = <1>; |
| 71 | #size-cells = <1>; |
| 72 | ranges; |
| 73 | |
Hans de Goede | a9f8cda | 2014-11-18 12:07:13 +0100 | [diff] [blame] | 74 | framebuffer@0 { |
| 75 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; |
| 76 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
Hans de Goede | 678e75d | 2014-11-16 17:09:32 +0100 | [diff] [blame] | 77 | clocks = <&pll6 0>; |
Hans de Goede | e53a8b2 | 2014-11-14 16:34:36 +0100 | [diff] [blame] | 78 | status = "disabled"; |
| 79 | }; |
| 80 | }; |
Maxime Ripard | 54428d4 | 2014-01-02 22:05:04 +0100 | [diff] [blame] | 81 | |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 82 | cpus { |
Maxime Ripard | ce78e35 | 2014-04-18 21:01:52 +0200 | [diff] [blame] | 83 | enable-method = "allwinner,sun6i-a31"; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 84 | #address-cells = <1>; |
| 85 | #size-cells = <0>; |
| 86 | |
| 87 | cpu@0 { |
| 88 | compatible = "arm,cortex-a7"; |
| 89 | device_type = "cpu"; |
| 90 | reg = <0>; |
| 91 | }; |
| 92 | |
| 93 | cpu@1 { |
| 94 | compatible = "arm,cortex-a7"; |
| 95 | device_type = "cpu"; |
| 96 | reg = <1>; |
| 97 | }; |
| 98 | |
| 99 | cpu@2 { |
| 100 | compatible = "arm,cortex-a7"; |
| 101 | device_type = "cpu"; |
| 102 | reg = <2>; |
| 103 | }; |
| 104 | |
| 105 | cpu@3 { |
| 106 | compatible = "arm,cortex-a7"; |
| 107 | device_type = "cpu"; |
| 108 | reg = <3>; |
| 109 | }; |
| 110 | }; |
| 111 | |
| 112 | memory { |
| 113 | reg = <0x40000000 0x80000000>; |
| 114 | }; |
| 115 | |
Maxime Ripard | b5a10b7 | 2014-04-17 21:54:41 +0200 | [diff] [blame] | 116 | pmu { |
| 117 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 118 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| 119 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 120 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
| 121 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | b5a10b7 | 2014-04-17 21:54:41 +0200 | [diff] [blame] | 122 | }; |
| 123 | |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 124 | clocks { |
| 125 | #address-cells = <1>; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 126 | #size-cells = <1>; |
| 127 | ranges; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 128 | |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 129 | osc24M: osc24M { |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 130 | #clock-cells = <0>; |
| 131 | compatible = "fixed-clock"; |
| 132 | clock-frequency = <24000000>; |
| 133 | }; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 134 | |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 135 | osc32k: clk@0 { |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 136 | #clock-cells = <0>; |
| 137 | compatible = "fixed-clock"; |
| 138 | clock-frequency = <32768>; |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 139 | clock-output-names = "osc32k"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 140 | }; |
| 141 | |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 142 | pll1: clk@01c20000 { |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 143 | #clock-cells = <0>; |
| 144 | compatible = "allwinner,sun6i-a31-pll1-clk"; |
| 145 | reg = <0x01c20000 0x4>; |
| 146 | clocks = <&osc24M>; |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 147 | clock-output-names = "pll1"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 148 | }; |
| 149 | |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 150 | pll6: clk@01c20028 { |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 151 | #clock-cells = <1>; |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 152 | compatible = "allwinner,sun6i-a31-pll6-clk"; |
| 153 | reg = <0x01c20028 0x4>; |
| 154 | clocks = <&osc24M>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 155 | clock-output-names = "pll6", "pll6x2"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 156 | }; |
| 157 | |
| 158 | cpu: cpu@01c20050 { |
| 159 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 160 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 161 | reg = <0x01c20050 0x4>; |
| 162 | |
| 163 | /* |
| 164 | * PLL1 is listed twice here. |
| 165 | * While it looks suspicious, it's actually documented |
| 166 | * that way both in the datasheet and in the code from |
| 167 | * Allwinner. |
| 168 | */ |
| 169 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 170 | clock-output-names = "cpu"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | axi: axi@01c20050 { |
| 174 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 175 | compatible = "allwinner,sun4i-a10-axi-clk"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 176 | reg = <0x01c20050 0x4>; |
| 177 | clocks = <&cpu>; |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 178 | clock-output-names = "axi"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 179 | }; |
| 180 | |
| 181 | ahb1_mux: ahb1_mux@01c20054 { |
| 182 | #clock-cells = <0>; |
| 183 | compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; |
| 184 | reg = <0x01c20054 0x4>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 185 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 186 | clock-output-names = "ahb1_mux"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 187 | }; |
| 188 | |
| 189 | ahb1: ahb1@01c20054 { |
| 190 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 191 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 192 | reg = <0x01c20054 0x4>; |
| 193 | clocks = <&ahb1_mux>; |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 194 | clock-output-names = "ahb1"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 195 | }; |
| 196 | |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 197 | ahb1_gates: clk@01c20060 { |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 198 | #clock-cells = <1>; |
| 199 | compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; |
| 200 | reg = <0x01c20060 0x8>; |
| 201 | clocks = <&ahb1>; |
| 202 | clock-output-names = "ahb1_mipidsi", "ahb1_ss", |
| 203 | "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", |
| 204 | "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", |
| 205 | "ahb1_nand0", "ahb1_sdram", |
| 206 | "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", |
| 207 | "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", |
| 208 | "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", |
| 209 | "ahb1_ehci1", "ahb1_ohci0", |
| 210 | "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", |
| 211 | "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", |
| 212 | "ahb1_hdmi", "ahb1_de0", "ahb1_de1", |
| 213 | "ahb1_fe0", "ahb1_fe1", "ahb1_mp", |
| 214 | "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", |
| 215 | "ahb1_drc0", "ahb1_drc1"; |
| 216 | }; |
| 217 | |
| 218 | apb1: apb1@01c20054 { |
| 219 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 220 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 221 | reg = <0x01c20054 0x4>; |
| 222 | clocks = <&ahb1>; |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 223 | clock-output-names = "apb1"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 224 | }; |
| 225 | |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 226 | apb1_gates: clk@01c20068 { |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 227 | #clock-cells = <1>; |
| 228 | compatible = "allwinner,sun6i-a31-apb1-gates-clk"; |
| 229 | reg = <0x01c20068 0x4>; |
| 230 | clocks = <&apb1>; |
| 231 | clock-output-names = "apb1_codec", "apb1_digital_mic", |
| 232 | "apb1_pio", "apb1_daudio0", |
| 233 | "apb1_daudio1"; |
| 234 | }; |
| 235 | |
Chen-Yu Tsai | 74c947a | 2014-11-06 11:40:31 +0800 | [diff] [blame] | 236 | apb2: clk@01c20058 { |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 237 | #clock-cells = <0>; |
Chen-Yu Tsai | 74c947a | 2014-11-06 11:40:31 +0800 | [diff] [blame] | 238 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 239 | reg = <0x01c20058 0x4>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 240 | clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 241 | clock-output-names = "apb2"; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 242 | }; |
| 243 | |
Chen-Yu Tsai | 7b5b290 | 2014-02-03 09:51:43 +0800 | [diff] [blame] | 244 | apb2_gates: clk@01c2006c { |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 245 | #clock-cells = <1>; |
| 246 | compatible = "allwinner,sun6i-a31-apb2-gates-clk"; |
Maxime Ripard | 439d9f5 | 2013-09-24 16:30:05 +0300 | [diff] [blame] | 247 | reg = <0x01c2006c 0x4>; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 248 | clocks = <&apb2>; |
| 249 | clock-output-names = "apb2_i2c0", "apb2_i2c1", |
| 250 | "apb2_i2c2", "apb2_i2c3", "apb2_uart0", |
| 251 | "apb2_uart1", "apb2_uart2", "apb2_uart3", |
| 252 | "apb2_uart4", "apb2_uart5"; |
| 253 | }; |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 254 | |
Hans de Goede | adc54c8 | 2014-05-02 17:57:23 +0200 | [diff] [blame] | 255 | mmc0_clk: clk@01c20088 { |
| 256 | #clock-cells = <0>; |
| 257 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 258 | reg = <0x01c20088 0x4>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 259 | clocks = <&osc24M>, <&pll6 0>; |
Hans de Goede | adc54c8 | 2014-05-02 17:57:23 +0200 | [diff] [blame] | 260 | clock-output-names = "mmc0"; |
| 261 | }; |
| 262 | |
| 263 | mmc1_clk: clk@01c2008c { |
| 264 | #clock-cells = <0>; |
| 265 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 266 | reg = <0x01c2008c 0x4>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 267 | clocks = <&osc24M>, <&pll6 0>; |
Hans de Goede | adc54c8 | 2014-05-02 17:57:23 +0200 | [diff] [blame] | 268 | clock-output-names = "mmc1"; |
| 269 | }; |
| 270 | |
| 271 | mmc2_clk: clk@01c20090 { |
| 272 | #clock-cells = <0>; |
| 273 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 274 | reg = <0x01c20090 0x4>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 275 | clocks = <&osc24M>, <&pll6 0>; |
Hans de Goede | adc54c8 | 2014-05-02 17:57:23 +0200 | [diff] [blame] | 276 | clock-output-names = "mmc2"; |
| 277 | }; |
| 278 | |
| 279 | mmc3_clk: clk@01c20094 { |
| 280 | #clock-cells = <0>; |
| 281 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 282 | reg = <0x01c20094 0x4>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 283 | clocks = <&osc24M>, <&pll6 0>; |
Hans de Goede | adc54c8 | 2014-05-02 17:57:23 +0200 | [diff] [blame] | 284 | clock-output-names = "mmc3"; |
| 285 | }; |
| 286 | |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 287 | spi0_clk: clk@01c200a0 { |
| 288 | #clock-cells = <0>; |
Maxime Ripard | 225b021 | 2014-02-24 17:29:06 +0100 | [diff] [blame] | 289 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 290 | reg = <0x01c200a0 0x4>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 291 | clocks = <&osc24M>, <&pll6 0>; |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 292 | clock-output-names = "spi0"; |
| 293 | }; |
| 294 | |
| 295 | spi1_clk: clk@01c200a4 { |
| 296 | #clock-cells = <0>; |
Maxime Ripard | 225b021 | 2014-02-24 17:29:06 +0100 | [diff] [blame] | 297 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 298 | reg = <0x01c200a4 0x4>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 299 | clocks = <&osc24M>, <&pll6 0>; |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 300 | clock-output-names = "spi1"; |
| 301 | }; |
| 302 | |
| 303 | spi2_clk: clk@01c200a8 { |
| 304 | #clock-cells = <0>; |
Maxime Ripard | 225b021 | 2014-02-24 17:29:06 +0100 | [diff] [blame] | 305 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 306 | reg = <0x01c200a8 0x4>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 307 | clocks = <&osc24M>, <&pll6 0>; |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 308 | clock-output-names = "spi2"; |
| 309 | }; |
| 310 | |
| 311 | spi3_clk: clk@01c200ac { |
| 312 | #clock-cells = <0>; |
Maxime Ripard | 225b021 | 2014-02-24 17:29:06 +0100 | [diff] [blame] | 313 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 314 | reg = <0x01c200ac 0x4>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 315 | clocks = <&osc24M>, <&pll6 0>; |
Maxime Ripard | b0a09c7 | 2014-02-05 14:05:04 +0100 | [diff] [blame] | 316 | clock-output-names = "spi3"; |
| 317 | }; |
Maxime Ripard | 94a1cd1 | 2014-05-13 17:44:16 +0200 | [diff] [blame] | 318 | |
| 319 | usb_clk: clk@01c200cc { |
| 320 | #clock-cells = <1>; |
| 321 | #reset-cells = <1>; |
| 322 | compatible = "allwinner,sun6i-a31-usb-clk"; |
| 323 | reg = <0x01c200cc 0x4>; |
| 324 | clocks = <&osc24M>; |
| 325 | clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", |
| 326 | "usb_ohci0", "usb_ohci1", |
| 327 | "usb_ohci2"; |
| 328 | }; |
Chen-Yu Tsai | ed29861 | 2014-07-16 01:15:44 +0800 | [diff] [blame] | 329 | |
| 330 | /* |
| 331 | * The following two are dummy clocks, placeholders used in the gmac_tx |
| 332 | * clock. The gmac driver will choose one parent depending on the PHY |
| 333 | * interface mode, using clk_set_rate auto-reparenting. |
| 334 | * The actual TX clock rate is not controlled by the gmac_tx clock. |
| 335 | */ |
| 336 | mii_phy_tx_clk: clk@1 { |
| 337 | #clock-cells = <0>; |
| 338 | compatible = "fixed-clock"; |
| 339 | clock-frequency = <25000000>; |
| 340 | clock-output-names = "mii_phy_tx"; |
| 341 | }; |
| 342 | |
| 343 | gmac_int_tx_clk: clk@2 { |
| 344 | #clock-cells = <0>; |
| 345 | compatible = "fixed-clock"; |
| 346 | clock-frequency = <125000000>; |
| 347 | clock-output-names = "gmac_int_tx"; |
| 348 | }; |
| 349 | |
| 350 | gmac_tx_clk: clk@01c200d0 { |
| 351 | #clock-cells = <0>; |
| 352 | compatible = "allwinner,sun7i-a20-gmac-clk"; |
| 353 | reg = <0x01c200d0 0x4>; |
| 354 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; |
| 355 | clock-output-names = "gmac_tx"; |
| 356 | }; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 357 | }; |
| 358 | |
| 359 | soc@01c00000 { |
| 360 | compatible = "simple-bus"; |
| 361 | #address-cells = <1>; |
| 362 | #size-cells = <1>; |
| 363 | ranges; |
| 364 | |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 365 | dma: dma-controller@01c02000 { |
| 366 | compatible = "allwinner,sun6i-a31-dma"; |
| 367 | reg = <0x01c02000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 368 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 369 | clocks = <&ahb1_gates 6>; |
| 370 | resets = <&ahb1_rst 6>; |
| 371 | #dma-cells = <1>; |
Chen-Yu Tsai | 532425a | 2014-11-06 19:56:49 +0800 | [diff] [blame] | 372 | |
| 373 | /* DMA controller requires AHB1 clocked from PLL6 */ |
| 374 | assigned-clocks = <&ahb1_mux>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 375 | assigned-clock-parents = <&pll6 0>; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 376 | }; |
| 377 | |
Hans de Goede | 5b753f0 | 2014-05-02 17:57:24 +0200 | [diff] [blame] | 378 | mmc0: mmc@01c0f000 { |
| 379 | compatible = "allwinner,sun5i-a13-mmc"; |
| 380 | reg = <0x01c0f000 0x1000>; |
| 381 | clocks = <&ahb1_gates 8>, <&mmc0_clk>; |
| 382 | clock-names = "ahb", "mmc"; |
| 383 | resets = <&ahb1_rst 8>; |
| 384 | reset-names = "ahb"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 385 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | 5b753f0 | 2014-05-02 17:57:24 +0200 | [diff] [blame] | 386 | status = "disabled"; |
| 387 | }; |
| 388 | |
| 389 | mmc1: mmc@01c10000 { |
| 390 | compatible = "allwinner,sun5i-a13-mmc"; |
| 391 | reg = <0x01c10000 0x1000>; |
| 392 | clocks = <&ahb1_gates 9>, <&mmc1_clk>; |
| 393 | clock-names = "ahb", "mmc"; |
| 394 | resets = <&ahb1_rst 9>; |
| 395 | reset-names = "ahb"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 396 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | 5b753f0 | 2014-05-02 17:57:24 +0200 | [diff] [blame] | 397 | status = "disabled"; |
| 398 | }; |
| 399 | |
| 400 | mmc2: mmc@01c11000 { |
| 401 | compatible = "allwinner,sun5i-a13-mmc"; |
| 402 | reg = <0x01c11000 0x1000>; |
| 403 | clocks = <&ahb1_gates 10>, <&mmc2_clk>; |
| 404 | clock-names = "ahb", "mmc"; |
| 405 | resets = <&ahb1_rst 10>; |
| 406 | reset-names = "ahb"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 407 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | 5b753f0 | 2014-05-02 17:57:24 +0200 | [diff] [blame] | 408 | status = "disabled"; |
| 409 | }; |
| 410 | |
| 411 | mmc3: mmc@01c12000 { |
| 412 | compatible = "allwinner,sun5i-a13-mmc"; |
| 413 | reg = <0x01c12000 0x1000>; |
| 414 | clocks = <&ahb1_gates 11>, <&mmc3_clk>; |
| 415 | clock-names = "ahb", "mmc"; |
| 416 | resets = <&ahb1_rst 11>; |
| 417 | reset-names = "ahb"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 418 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | 5b753f0 | 2014-05-02 17:57:24 +0200 | [diff] [blame] | 419 | status = "disabled"; |
| 420 | }; |
| 421 | |
Maxime Ripard | ef96408 | 2014-05-13 17:44:21 +0200 | [diff] [blame] | 422 | usbphy: phy@01c19400 { |
| 423 | compatible = "allwinner,sun6i-a31-usb-phy"; |
| 424 | reg = <0x01c19400 0x10>, |
| 425 | <0x01c1a800 0x4>, |
| 426 | <0x01c1b800 0x4>; |
| 427 | reg-names = "phy_ctrl", |
| 428 | "pmu1", |
| 429 | "pmu2"; |
| 430 | clocks = <&usb_clk 8>, |
| 431 | <&usb_clk 9>, |
| 432 | <&usb_clk 10>; |
| 433 | clock-names = "usb0_phy", |
| 434 | "usb1_phy", |
| 435 | "usb2_phy"; |
| 436 | resets = <&usb_clk 0>, |
| 437 | <&usb_clk 1>, |
| 438 | <&usb_clk 2>; |
| 439 | reset-names = "usb0_reset", |
| 440 | "usb1_reset", |
| 441 | "usb2_reset"; |
| 442 | status = "disabled"; |
| 443 | #phy-cells = <1>; |
| 444 | }; |
| 445 | |
| 446 | ehci0: usb@01c1a000 { |
| 447 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; |
| 448 | reg = <0x01c1a000 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 449 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | ef96408 | 2014-05-13 17:44:21 +0200 | [diff] [blame] | 450 | clocks = <&ahb1_gates 26>; |
| 451 | resets = <&ahb1_rst 26>; |
| 452 | phys = <&usbphy 1>; |
| 453 | phy-names = "usb"; |
| 454 | status = "disabled"; |
| 455 | }; |
| 456 | |
| 457 | ohci0: usb@01c1a400 { |
| 458 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; |
| 459 | reg = <0x01c1a400 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 460 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | ef96408 | 2014-05-13 17:44:21 +0200 | [diff] [blame] | 461 | clocks = <&ahb1_gates 29>, <&usb_clk 16>; |
| 462 | resets = <&ahb1_rst 29>; |
| 463 | phys = <&usbphy 1>; |
| 464 | phy-names = "usb"; |
| 465 | status = "disabled"; |
| 466 | }; |
| 467 | |
| 468 | ehci1: usb@01c1b000 { |
| 469 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; |
| 470 | reg = <0x01c1b000 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 471 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | ef96408 | 2014-05-13 17:44:21 +0200 | [diff] [blame] | 472 | clocks = <&ahb1_gates 27>; |
| 473 | resets = <&ahb1_rst 27>; |
| 474 | phys = <&usbphy 2>; |
| 475 | phy-names = "usb"; |
| 476 | status = "disabled"; |
| 477 | }; |
| 478 | |
| 479 | ohci1: usb@01c1b400 { |
| 480 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; |
| 481 | reg = <0x01c1b400 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 482 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | ef96408 | 2014-05-13 17:44:21 +0200 | [diff] [blame] | 483 | clocks = <&ahb1_gates 30>, <&usb_clk 17>; |
| 484 | resets = <&ahb1_rst 30>; |
| 485 | phys = <&usbphy 2>; |
| 486 | phy-names = "usb"; |
| 487 | status = "disabled"; |
| 488 | }; |
| 489 | |
Maxime Ripard | b294ebb | 2014-05-20 13:59:58 +0200 | [diff] [blame] | 490 | ohci2: usb@01c1c400 { |
Maxime Ripard | ef96408 | 2014-05-13 17:44:21 +0200 | [diff] [blame] | 491 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; |
| 492 | reg = <0x01c1c400 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 493 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | ef96408 | 2014-05-13 17:44:21 +0200 | [diff] [blame] | 494 | clocks = <&ahb1_gates 31>, <&usb_clk 18>; |
| 495 | resets = <&ahb1_rst 31>; |
| 496 | status = "disabled"; |
| 497 | }; |
| 498 | |
Maxime Ripard | 140e172 | 2013-03-12 22:16:05 +0100 | [diff] [blame] | 499 | pio: pinctrl@01c20800 { |
| 500 | compatible = "allwinner,sun6i-a31-pinctrl"; |
| 501 | reg = <0x01c20800 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 502 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| 503 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| 504 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| 505 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 506 | clocks = <&apb1_gates 5>; |
Maxime Ripard | 140e172 | 2013-03-12 22:16:05 +0100 | [diff] [blame] | 507 | gpio-controller; |
| 508 | interrupt-controller; |
Chen-Yu Tsai | 7d4ff96 | 2014-06-30 23:57:51 +0200 | [diff] [blame] | 509 | #interrupt-cells = <2>; |
Maxime Ripard | 140e172 | 2013-03-12 22:16:05 +0100 | [diff] [blame] | 510 | #size-cells = <0>; |
| 511 | #gpio-cells = <3>; |
Maxime Ripard | ab4238c | 2013-06-22 23:56:40 +0200 | [diff] [blame] | 512 | |
| 513 | uart0_pins_a: uart0@0 { |
| 514 | allwinner,pins = "PH20", "PH21"; |
| 515 | allwinner,function = "uart0"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 516 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 517 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | ab4238c | 2013-06-22 23:56:40 +0200 | [diff] [blame] | 518 | }; |
Maxime Ripard | 8be188b | 2014-03-04 17:28:40 +0100 | [diff] [blame] | 519 | |
| 520 | i2c0_pins_a: i2c0@0 { |
| 521 | allwinner,pins = "PH14", "PH15"; |
| 522 | allwinner,function = "i2c0"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 523 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 524 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | 8be188b | 2014-03-04 17:28:40 +0100 | [diff] [blame] | 525 | }; |
| 526 | |
| 527 | i2c1_pins_a: i2c1@0 { |
| 528 | allwinner,pins = "PH16", "PH17"; |
| 529 | allwinner,function = "i2c1"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 530 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 531 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | 8be188b | 2014-03-04 17:28:40 +0100 | [diff] [blame] | 532 | }; |
| 533 | |
| 534 | i2c2_pins_a: i2c2@0 { |
| 535 | allwinner,pins = "PH18", "PH19"; |
| 536 | allwinner,function = "i2c2"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 537 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 538 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | 8be188b | 2014-03-04 17:28:40 +0100 | [diff] [blame] | 539 | }; |
Hans de Goede | 9797eb8 | 2014-04-26 12:16:16 +0200 | [diff] [blame] | 540 | |
| 541 | mmc0_pins_a: mmc0@0 { |
| 542 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; |
| 543 | allwinner,function = "mmc0"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 544 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 545 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Hans de Goede | 9797eb8 | 2014-04-26 12:16:16 +0200 | [diff] [blame] | 546 | }; |
Chen-Yu Tsai | ee39a3e | 2014-07-16 01:15:43 +0800 | [diff] [blame] | 547 | |
| 548 | gmac_pins_mii_a: gmac_mii@0 { |
| 549 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", |
| 550 | "PA8", "PA9", "PA11", |
| 551 | "PA12", "PA13", "PA14", "PA19", |
| 552 | "PA20", "PA21", "PA22", "PA23", |
| 553 | "PA24", "PA26", "PA27"; |
| 554 | allwinner,function = "gmac"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 555 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 556 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Chen-Yu Tsai | ee39a3e | 2014-07-16 01:15:43 +0800 | [diff] [blame] | 557 | }; |
| 558 | |
| 559 | gmac_pins_gmii_a: gmac_gmii@0 { |
| 560 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", |
| 561 | "PA4", "PA5", "PA6", "PA7", |
| 562 | "PA8", "PA9", "PA10", "PA11", |
| 563 | "PA12", "PA13", "PA14", "PA15", |
| 564 | "PA16", "PA17", "PA18", "PA19", |
| 565 | "PA20", "PA21", "PA22", "PA23", |
| 566 | "PA24", "PA25", "PA26", "PA27"; |
| 567 | allwinner,function = "gmac"; |
| 568 | /* |
| 569 | * data lines in GMII mode run at 125MHz and |
| 570 | * might need a higher signal drive strength |
| 571 | */ |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 572 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 573 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Chen-Yu Tsai | ee39a3e | 2014-07-16 01:15:43 +0800 | [diff] [blame] | 574 | }; |
| 575 | |
| 576 | gmac_pins_rgmii_a: gmac_rgmii@0 { |
| 577 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", |
| 578 | "PA9", "PA10", "PA11", |
| 579 | "PA12", "PA13", "PA14", "PA19", |
| 580 | "PA20", "PA25", "PA26", "PA27"; |
| 581 | allwinner,function = "gmac"; |
| 582 | /* |
| 583 | * data lines in RGMII mode use DDR mode |
| 584 | * and need a higher signal drive strength |
| 585 | */ |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 586 | allwinner,drive = <SUN4I_PINCTRL_40_MA>; |
| 587 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Chen-Yu Tsai | ee39a3e | 2014-07-16 01:15:43 +0800 | [diff] [blame] | 588 | }; |
Maxime Ripard | 140e172 | 2013-03-12 22:16:05 +0100 | [diff] [blame] | 589 | }; |
| 590 | |
Maxime Ripard | 24a661e9 | 2013-09-24 11:10:41 +0300 | [diff] [blame] | 591 | ahb1_rst: reset@01c202c0 { |
| 592 | #reset-cells = <1>; |
| 593 | compatible = "allwinner,sun6i-a31-ahb1-reset"; |
| 594 | reg = <0x01c202c0 0xc>; |
| 595 | }; |
| 596 | |
| 597 | apb1_rst: reset@01c202d0 { |
| 598 | #reset-cells = <1>; |
| 599 | compatible = "allwinner,sun6i-a31-clock-reset"; |
| 600 | reg = <0x01c202d0 0x4>; |
| 601 | }; |
| 602 | |
| 603 | apb2_rst: reset@01c202d8 { |
| 604 | #reset-cells = <1>; |
| 605 | compatible = "allwinner,sun6i-a31-clock-reset"; |
| 606 | reg = <0x01c202d8 0x4>; |
| 607 | }; |
| 608 | |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 609 | timer@01c20c00 { |
Maxime Ripard | b4f2644 | 2014-02-06 10:40:32 +0100 | [diff] [blame] | 610 | compatible = "allwinner,sun4i-a10-timer"; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 611 | reg = <0x01c20c00 0xa0>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 612 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
| 613 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
| 614 | <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, |
| 615 | <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| 616 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 617 | clocks = <&osc24M>; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 618 | }; |
| 619 | |
| 620 | wdt1: watchdog@01c20ca0 { |
Maxime Ripard | ca5d04d | 2014-02-07 22:29:26 +0100 | [diff] [blame] | 621 | compatible = "allwinner,sun6i-a31-wdt"; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 622 | reg = <0x01c20ca0 0x20>; |
| 623 | }; |
| 624 | |
| 625 | uart0: serial@01c28000 { |
| 626 | compatible = "snps,dw-apb-uart"; |
| 627 | reg = <0x01c28000 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 628 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 629 | reg-shift = <2>; |
| 630 | reg-io-width = <4>; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 631 | clocks = <&apb2_gates 16>; |
Maxime Ripard | 24a661e9 | 2013-09-24 11:10:41 +0300 | [diff] [blame] | 632 | resets = <&apb2_rst 16>; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 633 | dmas = <&dma 6>, <&dma 6>; |
| 634 | dma-names = "rx", "tx"; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 635 | status = "disabled"; |
| 636 | }; |
| 637 | |
| 638 | uart1: serial@01c28400 { |
| 639 | compatible = "snps,dw-apb-uart"; |
| 640 | reg = <0x01c28400 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 641 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 642 | reg-shift = <2>; |
| 643 | reg-io-width = <4>; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 644 | clocks = <&apb2_gates 17>; |
Maxime Ripard | 24a661e9 | 2013-09-24 11:10:41 +0300 | [diff] [blame] | 645 | resets = <&apb2_rst 17>; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 646 | dmas = <&dma 7>, <&dma 7>; |
| 647 | dma-names = "rx", "tx"; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 648 | status = "disabled"; |
| 649 | }; |
| 650 | |
| 651 | uart2: serial@01c28800 { |
| 652 | compatible = "snps,dw-apb-uart"; |
| 653 | reg = <0x01c28800 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 654 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 655 | reg-shift = <2>; |
| 656 | reg-io-width = <4>; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 657 | clocks = <&apb2_gates 18>; |
Maxime Ripard | 24a661e9 | 2013-09-24 11:10:41 +0300 | [diff] [blame] | 658 | resets = <&apb2_rst 18>; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 659 | dmas = <&dma 8>, <&dma 8>; |
| 660 | dma-names = "rx", "tx"; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 661 | status = "disabled"; |
| 662 | }; |
| 663 | |
| 664 | uart3: serial@01c28c00 { |
| 665 | compatible = "snps,dw-apb-uart"; |
| 666 | reg = <0x01c28c00 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 667 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 668 | reg-shift = <2>; |
| 669 | reg-io-width = <4>; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 670 | clocks = <&apb2_gates 19>; |
Maxime Ripard | 24a661e9 | 2013-09-24 11:10:41 +0300 | [diff] [blame] | 671 | resets = <&apb2_rst 19>; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 672 | dmas = <&dma 9>, <&dma 9>; |
| 673 | dma-names = "rx", "tx"; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 674 | status = "disabled"; |
| 675 | }; |
| 676 | |
| 677 | uart4: serial@01c29000 { |
| 678 | compatible = "snps,dw-apb-uart"; |
| 679 | reg = <0x01c29000 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 680 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 681 | reg-shift = <2>; |
| 682 | reg-io-width = <4>; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 683 | clocks = <&apb2_gates 20>; |
Maxime Ripard | 24a661e9 | 2013-09-24 11:10:41 +0300 | [diff] [blame] | 684 | resets = <&apb2_rst 20>; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 685 | dmas = <&dma 10>, <&dma 10>; |
| 686 | dma-names = "rx", "tx"; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 687 | status = "disabled"; |
| 688 | }; |
| 689 | |
| 690 | uart5: serial@01c29400 { |
| 691 | compatible = "snps,dw-apb-uart"; |
| 692 | reg = <0x01c29400 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 693 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 694 | reg-shift = <2>; |
| 695 | reg-io-width = <4>; |
Maxime Ripard | 9809656 | 2013-07-23 23:54:19 +0200 | [diff] [blame] | 696 | clocks = <&apb2_gates 21>; |
Maxime Ripard | 24a661e9 | 2013-09-24 11:10:41 +0300 | [diff] [blame] | 697 | resets = <&apb2_rst 21>; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 698 | dmas = <&dma 22>, <&dma 22>; |
| 699 | dma-names = "rx", "tx"; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 700 | status = "disabled"; |
| 701 | }; |
| 702 | |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 703 | i2c0: i2c@01c2ac00 { |
| 704 | compatible = "allwinner,sun6i-a31-i2c"; |
| 705 | reg = <0x01c2ac00 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 706 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 707 | clocks = <&apb2_gates 0>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 708 | resets = <&apb2_rst 0>; |
| 709 | status = "disabled"; |
Chen-Yu Tsai | 495bccf | 2014-07-21 22:54:27 +0800 | [diff] [blame] | 710 | #address-cells = <1>; |
| 711 | #size-cells = <0>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 712 | }; |
| 713 | |
| 714 | i2c1: i2c@01c2b000 { |
| 715 | compatible = "allwinner,sun6i-a31-i2c"; |
| 716 | reg = <0x01c2b000 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 717 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 718 | clocks = <&apb2_gates 1>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 719 | resets = <&apb2_rst 1>; |
| 720 | status = "disabled"; |
Chen-Yu Tsai | 495bccf | 2014-07-21 22:54:27 +0800 | [diff] [blame] | 721 | #address-cells = <1>; |
| 722 | #size-cells = <0>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 723 | }; |
| 724 | |
| 725 | i2c2: i2c@01c2b400 { |
| 726 | compatible = "allwinner,sun6i-a31-i2c"; |
| 727 | reg = <0x01c2b400 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 728 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 729 | clocks = <&apb2_gates 2>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 730 | resets = <&apb2_rst 2>; |
| 731 | status = "disabled"; |
Chen-Yu Tsai | 495bccf | 2014-07-21 22:54:27 +0800 | [diff] [blame] | 732 | #address-cells = <1>; |
| 733 | #size-cells = <0>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 734 | }; |
| 735 | |
| 736 | i2c3: i2c@01c2b800 { |
| 737 | compatible = "allwinner,sun6i-a31-i2c"; |
| 738 | reg = <0x01c2b800 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 739 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 740 | clocks = <&apb2_gates 3>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 741 | resets = <&apb2_rst 3>; |
| 742 | status = "disabled"; |
Chen-Yu Tsai | 495bccf | 2014-07-21 22:54:27 +0800 | [diff] [blame] | 743 | #address-cells = <1>; |
| 744 | #size-cells = <0>; |
Maxime Ripard | 96c7cc9 | 2014-03-04 17:28:39 +0100 | [diff] [blame] | 745 | }; |
| 746 | |
Chen-Yu Tsai | 3dca65f | 2014-07-16 01:15:45 +0800 | [diff] [blame] | 747 | gmac: ethernet@01c30000 { |
| 748 | compatible = "allwinner,sun7i-a20-gmac"; |
| 749 | reg = <0x01c30000 0x1054>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 750 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Chen-Yu Tsai | 3dca65f | 2014-07-16 01:15:45 +0800 | [diff] [blame] | 751 | interrupt-names = "macirq"; |
| 752 | clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; |
| 753 | clock-names = "stmmaceth", "allwinner_gmac_tx"; |
| 754 | resets = <&ahb1_rst 17>; |
| 755 | reset-names = "stmmaceth"; |
| 756 | snps,pbl = <2>; |
| 757 | snps,fixed-burst; |
| 758 | snps,force_sf_dma_mode; |
| 759 | status = "disabled"; |
| 760 | #address-cells = <1>; |
| 761 | #size-cells = <0>; |
| 762 | }; |
| 763 | |
Maxime Ripard | 8cffcb0 | 2014-04-17 11:06:46 +0200 | [diff] [blame] | 764 | timer@01c60000 { |
| 765 | compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; |
| 766 | reg = <0x01c60000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 767 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| 768 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
| 769 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| 770 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 8cffcb0 | 2014-04-17 11:06:46 +0200 | [diff] [blame] | 771 | clocks = <&ahb1_gates 19>; |
| 772 | resets = <&ahb1_rst 19>; |
| 773 | }; |
| 774 | |
Maxime Ripard | 0d6efe3 | 2014-02-05 14:05:06 +0100 | [diff] [blame] | 775 | spi0: spi@01c68000 { |
| 776 | compatible = "allwinner,sun6i-a31-spi"; |
| 777 | reg = <0x01c68000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 778 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 0d6efe3 | 2014-02-05 14:05:06 +0100 | [diff] [blame] | 779 | clocks = <&ahb1_gates 20>, <&spi0_clk>; |
| 780 | clock-names = "ahb", "mod"; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 781 | dmas = <&dma 23>, <&dma 23>; |
| 782 | dma-names = "rx", "tx"; |
Maxime Ripard | 0d6efe3 | 2014-02-05 14:05:06 +0100 | [diff] [blame] | 783 | resets = <&ahb1_rst 20>; |
| 784 | status = "disabled"; |
| 785 | }; |
| 786 | |
| 787 | spi1: spi@01c69000 { |
| 788 | compatible = "allwinner,sun6i-a31-spi"; |
| 789 | reg = <0x01c69000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 790 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 0d6efe3 | 2014-02-05 14:05:06 +0100 | [diff] [blame] | 791 | clocks = <&ahb1_gates 21>, <&spi1_clk>; |
| 792 | clock-names = "ahb", "mod"; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 793 | dmas = <&dma 24>, <&dma 24>; |
| 794 | dma-names = "rx", "tx"; |
Maxime Ripard | 0d6efe3 | 2014-02-05 14:05:06 +0100 | [diff] [blame] | 795 | resets = <&ahb1_rst 21>; |
| 796 | status = "disabled"; |
| 797 | }; |
| 798 | |
| 799 | spi2: spi@01c6a000 { |
| 800 | compatible = "allwinner,sun6i-a31-spi"; |
| 801 | reg = <0x01c6a000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 802 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 0d6efe3 | 2014-02-05 14:05:06 +0100 | [diff] [blame] | 803 | clocks = <&ahb1_gates 22>, <&spi2_clk>; |
| 804 | clock-names = "ahb", "mod"; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 805 | dmas = <&dma 25>, <&dma 25>; |
| 806 | dma-names = "rx", "tx"; |
Maxime Ripard | 0d6efe3 | 2014-02-05 14:05:06 +0100 | [diff] [blame] | 807 | resets = <&ahb1_rst 22>; |
| 808 | status = "disabled"; |
| 809 | }; |
| 810 | |
| 811 | spi3: spi@01c6b000 { |
| 812 | compatible = "allwinner,sun6i-a31-spi"; |
| 813 | reg = <0x01c6b000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 814 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 0d6efe3 | 2014-02-05 14:05:06 +0100 | [diff] [blame] | 815 | clocks = <&ahb1_gates 23>, <&spi3_clk>; |
| 816 | clock-names = "ahb", "mod"; |
Maxime Ripard | d2d878c | 2014-01-30 15:41:23 +0100 | [diff] [blame] | 817 | dmas = <&dma 26>, <&dma 26>; |
| 818 | dma-names = "rx", "tx"; |
Maxime Ripard | 0d6efe3 | 2014-02-05 14:05:06 +0100 | [diff] [blame] | 819 | resets = <&ahb1_rst 23>; |
| 820 | status = "disabled"; |
| 821 | }; |
| 822 | |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 823 | gic: interrupt-controller@01c81000 { |
| 824 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| 825 | reg = <0x01c81000 0x1000>, |
| 826 | <0x01c82000 0x1000>, |
| 827 | <0x01c84000 0x2000>, |
| 828 | <0x01c86000 0x2000>; |
| 829 | interrupt-controller; |
| 830 | #interrupt-cells = <3>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 831 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 832 | }; |
Maxime Ripard | 81ee429 | 2013-11-03 10:30:12 +0100 | [diff] [blame] | 833 | |
Chen-Yu Tsai | 5e70043 | 2014-07-30 20:56:06 +0800 | [diff] [blame] | 834 | rtc: rtc@01f00000 { |
| 835 | compatible = "allwinner,sun6i-a31-rtc"; |
| 836 | reg = <0x01f00000 0x54>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 837 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| 838 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
Chen-Yu Tsai | 5e70043 | 2014-07-30 20:56:06 +0800 | [diff] [blame] | 839 | }; |
| 840 | |
Maxime Ripard | 28240d2 | 2014-04-17 10:29:35 +0200 | [diff] [blame] | 841 | nmi_intc: interrupt-controller@01f00c0c { |
| 842 | compatible = "allwinner,sun6i-a31-sc-nmi"; |
| 843 | interrupt-controller; |
| 844 | #interrupt-cells = <2>; |
| 845 | reg = <0x01f00c0c 0x38>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 846 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 28240d2 | 2014-04-17 10:29:35 +0200 | [diff] [blame] | 847 | }; |
| 848 | |
Hans de Goede | a42ea60 | 2014-04-13 13:41:02 +0200 | [diff] [blame] | 849 | prcm@01f01400 { |
| 850 | compatible = "allwinner,sun6i-a31-prcm"; |
| 851 | reg = <0x01f01400 0x200>; |
Boris BREZILLON | cc08f5e | 2014-05-14 14:38:21 +0200 | [diff] [blame] | 852 | |
| 853 | ar100: ar100_clk { |
| 854 | compatible = "allwinner,sun6i-a31-ar100-clk"; |
| 855 | #clock-cells = <0>; |
Chen-Yu Tsai | f6c3b04 | 2014-11-13 02:08:32 +0800 | [diff] [blame] | 856 | clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; |
Boris BREZILLON | cc08f5e | 2014-05-14 14:38:21 +0200 | [diff] [blame] | 857 | clock-output-names = "ar100"; |
| 858 | }; |
| 859 | |
| 860 | ahb0: ahb0_clk { |
| 861 | compatible = "fixed-factor-clock"; |
| 862 | #clock-cells = <0>; |
| 863 | clock-div = <1>; |
| 864 | clock-mult = <1>; |
| 865 | clocks = <&ar100>; |
| 866 | clock-output-names = "ahb0"; |
| 867 | }; |
| 868 | |
| 869 | apb0: apb0_clk { |
| 870 | compatible = "allwinner,sun6i-a31-apb0-clk"; |
| 871 | #clock-cells = <0>; |
| 872 | clocks = <&ahb0>; |
| 873 | clock-output-names = "apb0"; |
| 874 | }; |
| 875 | |
| 876 | apb0_gates: apb0_gates_clk { |
| 877 | compatible = "allwinner,sun6i-a31-apb0-gates-clk"; |
| 878 | #clock-cells = <1>; |
| 879 | clocks = <&apb0>; |
| 880 | clock-output-names = "apb0_pio", "apb0_ir", |
| 881 | "apb0_timer", "apb0_p2wi", |
| 882 | "apb0_uart", "apb0_1wire", |
| 883 | "apb0_i2c"; |
| 884 | }; |
| 885 | |
Hans de Goede | 9b5c6e0 | 2014-12-17 18:18:19 +0100 | [diff] [blame] | 886 | ir_clk: ir_clk { |
| 887 | #clock-cells = <0>; |
| 888 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 889 | clocks = <&osc32k>, <&osc24M>; |
| 890 | clock-output-names = "ir"; |
| 891 | }; |
| 892 | |
Boris BREZILLON | cc08f5e | 2014-05-14 14:38:21 +0200 | [diff] [blame] | 893 | apb0_rst: apb0_rst { |
| 894 | compatible = "allwinner,sun6i-a31-clock-reset"; |
| 895 | #reset-cells = <1>; |
| 896 | }; |
Hans de Goede | a42ea60 | 2014-04-13 13:41:02 +0200 | [diff] [blame] | 897 | }; |
| 898 | |
Maxime Ripard | 81ee429 | 2013-11-03 10:30:12 +0100 | [diff] [blame] | 899 | cpucfg@01f01c00 { |
| 900 | compatible = "allwinner,sun6i-a31-cpuconfig"; |
| 901 | reg = <0x01f01c00 0x300>; |
| 902 | }; |
Boris BREZILLON | 209394a | 2014-05-13 16:03:03 +0200 | [diff] [blame] | 903 | |
Hans de Goede | 4ac367b | 2014-12-29 12:09:24 +0100 | [diff] [blame] | 904 | ir: ir@01f02000 { |
| 905 | compatible = "allwinner,sun5i-a13-ir"; |
| 906 | clocks = <&apb0_gates 1>, <&ir_clk>; |
| 907 | clock-names = "apb", "ir"; |
| 908 | resets = <&apb0_rst 1>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 909 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | 4ac367b | 2014-12-29 12:09:24 +0100 | [diff] [blame] | 910 | reg = <0x01f02000 0x40>; |
| 911 | status = "disabled"; |
| 912 | }; |
| 913 | |
Boris BREZILLON | 209394a | 2014-05-13 16:03:03 +0200 | [diff] [blame] | 914 | r_pio: pinctrl@01f02c00 { |
| 915 | compatible = "allwinner,sun6i-a31-r-pinctrl"; |
| 916 | reg = <0x01f02c00 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame^] | 917 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
| 918 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Boris BREZILLON | 209394a | 2014-05-13 16:03:03 +0200 | [diff] [blame] | 919 | clocks = <&apb0_gates 0>; |
| 920 | resets = <&apb0_rst 0>; |
| 921 | gpio-controller; |
| 922 | interrupt-controller; |
Chen-Yu Tsai | 7d4ff96 | 2014-06-30 23:57:51 +0200 | [diff] [blame] | 923 | #interrupt-cells = <2>; |
Boris BREZILLON | 209394a | 2014-05-13 16:03:03 +0200 | [diff] [blame] | 924 | #size-cells = <0>; |
| 925 | #gpio-cells = <3>; |
Hans de Goede | dbbcd88 | 2014-11-23 14:38:14 +0100 | [diff] [blame] | 926 | |
| 927 | ir_pins_a: ir@0 { |
| 928 | allwinner,pins = "PL4"; |
| 929 | allwinner,function = "s_ir"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 930 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 931 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Hans de Goede | dbbcd88 | 2014-11-23 14:38:14 +0100 | [diff] [blame] | 932 | }; |
Boris BREZILLON | 209394a | 2014-05-13 16:03:03 +0200 | [diff] [blame] | 933 | }; |
Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame] | 934 | }; |
| 935 | }; |