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Ondrej Zary45d44e52012-10-14 21:09:20 +02001#ifndef __SOUND_WM8766_H
2#define __SOUND_WM8766_H
3
4/*
5 * ALSA driver for ICEnsemble VT17xx
6 *
7 * Lowlevel functions for WM8766 codec
8 *
9 * Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26
27#define WM8766_REG_DACL1 0x00
28#define WM8766_REG_DACR1 0x01
29#define WM8766_VOL_MASK 0x1ff /* incl. update bit */
30#define WM8766_VOL_UPDATE (1 << 8) /* update volume */
31#define WM8766_REG_DACCTRL1 0x02
32#define WM8766_DAC_MUTEALL (1 << 0)
33#define WM8766_DAC_DEEMPALL (1 << 1)
34#define WM8766_DAC_PDWN (1 << 2)
35#define WM8766_DAC_ATC (1 << 3)
36#define WM8766_DAC_IZD (1 << 4)
37#define WM8766_DAC_PL_MASK 0x1e0
38#define WM8766_DAC_PL_LL (1 << 5) /* L chan: L signal */
39#define WM8766_DAC_PL_LR (2 << 5) /* L chan: R signal */
40#define WM8766_DAC_PL_LB (3 << 5) /* L chan: both */
41#define WM8766_DAC_PL_RL (1 << 7) /* R chan: L signal */
42#define WM8766_DAC_PL_RR (2 << 7) /* R chan: R signal */
43#define WM8766_DAC_PL_RB (3 << 7) /* R chan: both */
44#define WM8766_REG_IFCTRL 0x03
45#define WM8766_IF_FMT_RIGHTJ (0 << 0)
46#define WM8766_IF_FMT_LEFTJ (1 << 0)
47#define WM8766_IF_FMT_I2S (2 << 0)
48#define WM8766_IF_FMT_DSP (3 << 0)
49#define WM8766_IF_DSP_LATE (1 << 2) /* in DSP mode */
50#define WM8766_IF_LRC_INVERTED (1 << 2) /* in other modes */
51#define WM8766_IF_BCLK_INVERTED (1 << 3)
52#define WM8766_IF_IWL_16BIT (0 << 4)
53#define WM8766_IF_IWL_20BIT (1 << 4)
54#define WM8766_IF_IWL_24BIT (2 << 4)
55#define WM8766_IF_IWL_32BIT (3 << 4)
56#define WM8766_IF_MASK 0x3f
57#define WM8766_PHASE_INVERT1 (1 << 6)
58#define WM8766_PHASE_INVERT2 (1 << 7)
59#define WM8766_PHASE_INVERT3 (1 << 8)
60#define WM8766_REG_DACL2 0x04
61#define WM8766_REG_DACR2 0x05
62#define WM8766_REG_DACL3 0x06
63#define WM8766_REG_DACR3 0x07
64#define WM8766_REG_MASTDA 0x08
65#define WM8766_REG_DACCTRL2 0x09
66#define WM8766_DAC2_ZCD (1 << 0)
67#define WM8766_DAC2_ZFLAG_ALL (0 << 1)
68#define WM8766_DAC2_ZFLAG_1 (1 << 1)
69#define WM8766_DAC2_ZFLAG_2 (2 << 1)
70#define WM8766_DAC2_ZFLAG_3 (3 << 1)
71#define WM8766_DAC2_MUTE1 (1 << 3)
72#define WM8766_DAC2_MUTE2 (1 << 4)
73#define WM8766_DAC2_MUTE3 (1 << 5)
74#define WM8766_DAC2_DEEMP1 (1 << 6)
75#define WM8766_DAC2_DEEMP2 (1 << 7)
76#define WM8766_DAC2_DEEMP3 (1 << 8)
77#define WM8766_REG_DACCTRL3 0x0a
78#define WM8766_DAC3_DACPD1 (1 << 1)
79#define WM8766_DAC3_DACPD2 (1 << 2)
80#define WM8766_DAC3_DACPD3 (1 << 3)
81#define WM8766_DAC3_PWRDNALL (1 << 4)
82#define WM8766_DAC3_POWER_MASK 0x1e
83#define WM8766_DAC3_MASTER (1 << 5)
84#define WM8766_DAC3_DAC128FS (0 << 6)
85#define WM8766_DAC3_DAC192FS (1 << 6)
86#define WM8766_DAC3_DAC256FS (2 << 6)
87#define WM8766_DAC3_DAC384FS (3 << 6)
88#define WM8766_DAC3_DAC512FS (4 << 6)
89#define WM8766_DAC3_DAC768FS (5 << 6)
90#define WM8766_DAC3_MSTR_MASK 0x1e0
91#define WM8766_REG_MUTE1 0x0c
92#define WM8766_MUTE1_MPD (1 << 6)
93#define WM8766_REG_MUTE2 0x0f
94#define WM8766_MUTE2_MPD (1 << 5)
95#define WM8766_REG_RESET 0x1f
96
97#define WM8766_REG_COUNT 0x10 /* don't cache the RESET register */
98
99struct snd_wm8766;
100
101struct snd_wm8766_ops {
102 void (*write)(struct snd_wm8766 *wm, u16 addr, u16 data);
103};
104
105enum snd_wm8766_ctl_id {
106 WM8766_CTL_CH1_VOL,
107 WM8766_CTL_CH2_VOL,
108 WM8766_CTL_CH3_VOL,
109 WM8766_CTL_CH1_SW,
110 WM8766_CTL_CH2_SW,
111 WM8766_CTL_CH3_SW,
112 WM8766_CTL_PHASE1_SW,
113 WM8766_CTL_PHASE2_SW,
114 WM8766_CTL_PHASE3_SW,
115 WM8766_CTL_DEEMPH1_SW,
116 WM8766_CTL_DEEMPH2_SW,
117 WM8766_CTL_DEEMPH3_SW,
118 WM8766_CTL_IZD_SW,
119 WM8766_CTL_ZC_SW,
120
121 WM8766_CTL_COUNT,
122};
123
124#define WM8766_ENUM_MAX 16
125
126#define WM8766_FLAG_STEREO (1 << 0)
127#define WM8766_FLAG_VOL_UPDATE (1 << 1)
128#define WM8766_FLAG_INVERT (1 << 2)
129#define WM8766_FLAG_LIM (1 << 3)
130#define WM8766_FLAG_ALC (1 << 4)
131
132struct snd_wm8766_ctl {
133 struct snd_kcontrol *kctl;
Takashi Iwaia2af0502012-10-17 09:21:48 +0200134 const char *name;
Ondrej Zary45d44e52012-10-14 21:09:20 +0200135 snd_ctl_elem_type_t type;
136 const char *const enum_names[WM8766_ENUM_MAX];
137 const unsigned int *tlv;
138 u16 reg1, reg2, mask1, mask2, min, max, flags;
139 void (*set)(struct snd_wm8766 *wm, u16 ch1, u16 ch2);
140 void (*get)(struct snd_wm8766 *wm, u16 *ch1, u16 *ch2);
141};
142
143enum snd_wm8766_agc_mode { WM8766_AGC_OFF, WM8766_AGC_LIM, WM8766_AGC_ALC };
144
145struct snd_wm8766 {
146 struct snd_card *card;
147 struct snd_wm8766_ctl ctl[WM8766_CTL_COUNT];
148 enum snd_wm8766_agc_mode agc_mode;
149 struct snd_wm8766_ops ops;
150 u16 regs[WM8766_REG_COUNT]; /* 9-bit registers */
151};
152
153
154
155void snd_wm8766_init(struct snd_wm8766 *wm);
156void snd_wm8766_resume(struct snd_wm8766 *wm);
157void snd_wm8766_set_if(struct snd_wm8766 *wm, u16 dac);
158void snd_wm8766_set_master_mode(struct snd_wm8766 *wm, u16 mode);
159void snd_wm8766_set_power(struct snd_wm8766 *wm, u16 power);
160void snd_wm8766_volume_restore(struct snd_wm8766 *wm);
161int snd_wm8766_build_controls(struct snd_wm8766 *wm);
162
163#endif /* __SOUND_WM8766_H */