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Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
42#include <linux/bitops.h>
43#include <linux/if_vlan.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010044#include <linux/list.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020045#include <net/switchdev.h>
46
47#include "core.h"
48
49#define MLXSW_SP_VFID_BASE VLAN_N_VID
Ido Schimmel7f71eb42015-12-15 16:03:37 +010050#define MLXSW_SP_VFID_PORT_MAX 512 /* Non-bridged VLAN interfaces */
51#define MLXSW_SP_VFID_BR_MAX 8192 /* Bridged VLAN interfaces */
52#define MLXSW_SP_VFID_MAX (MLXSW_SP_VFID_PORT_MAX + MLXSW_SP_VFID_BR_MAX)
53
Jiri Pirko0d65fc12015-12-03 12:12:28 +010054#define MLXSW_SP_LAG_MAX 64
55#define MLXSW_SP_PORT_PER_LAG_MAX 16
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056
57struct mlxsw_sp_port;
58
Jiri Pirko0d65fc12015-12-03 12:12:28 +010059struct mlxsw_sp_upper {
60 struct net_device *dev;
61 unsigned int ref_count;
62};
63
Ido Schimmel7f71eb42015-12-15 16:03:37 +010064struct mlxsw_sp_vfid {
65 struct list_head list;
66 u16 nr_vports;
67 u16 vfid; /* Starting at 0 */
68 u16 vid;
69};
70
71static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
72{
73 return MLXSW_SP_VFID_BASE + vfid;
74}
75
Jiri Pirko56ade8f2015-10-16 14:01:37 +020076struct mlxsw_sp {
Ido Schimmel7f71eb42015-12-15 16:03:37 +010077 struct {
78 struct list_head list;
79 unsigned long mapped[BITS_TO_LONGS(MLXSW_SP_VFID_PORT_MAX)];
80 } port_vfids;
Jiri Pirko56ade8f2015-10-16 14:01:37 +020081 unsigned long active_fids[BITS_TO_LONGS(VLAN_N_VID)];
82 struct mlxsw_sp_port **ports;
83 struct mlxsw_core *core;
84 const struct mlxsw_bus_info *bus_info;
85 unsigned char base_mac[ETH_ALEN];
86 struct {
87 struct delayed_work dw;
88#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
89 unsigned int interval; /* ms */
90 } fdb_notify;
91#define MLXSW_SP_DEFAULT_AGEING_TIME 300
92 u32 ageing_time;
Jiri Pirko0d65fc12015-12-03 12:12:28 +010093 struct mlxsw_sp_upper master_bridge;
94 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
Jiri Pirko56ade8f2015-10-16 14:01:37 +020095};
96
Jiri Pirko0d65fc12015-12-03 12:12:28 +010097static inline struct mlxsw_sp_upper *
98mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
99{
100 return &mlxsw_sp->lags[lag_id];
101}
102
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200103struct mlxsw_sp_port_pcpu_stats {
104 u64 rx_packets;
105 u64 rx_bytes;
106 u64 tx_packets;
107 u64 tx_bytes;
108 struct u64_stats_sync syncp;
109 u32 tx_dropped;
110};
111
112struct mlxsw_sp_port {
113 struct net_device *dev;
114 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
115 struct mlxsw_sp *mlxsw_sp;
116 u8 local_port;
117 u8 stp_state;
Jiri Pirko0d9b9702015-10-28 10:16:56 +0100118 u8 learning:1,
119 learning_sync:1,
Ido Schimmel02930382015-10-28 10:16:58 +0100120 uc_flood:1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100121 bridged:1,
122 lagged:1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200123 u16 pvid;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100124 u16 lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100125 struct {
126 struct list_head list;
127 struct mlxsw_sp_vfid *vfid;
128 u16 vid;
129 } vport;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200130 /* 802.1Q bridge VLANs */
Ido Schimmelbd40e9d2015-12-15 16:03:36 +0100131 unsigned long *active_vlans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200132 /* VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100133 struct list_head vports_list;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200134};
135
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100136static inline struct mlxsw_sp_port *
137mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
138{
139 struct mlxsw_sp_port *mlxsw_sp_port;
140 u8 local_port;
141
142 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
143 lag_id, port_index);
144 mlxsw_sp_port = mlxsw_sp->ports[local_port];
145 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
146}
147
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100148static inline bool
149mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
150{
151 return mlxsw_sp_port->vport.vfid;
152}
153
154static inline u16
155mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
156{
157 return mlxsw_sp_vport->vport.vid;
158}
159
160static inline u16
161mlxsw_sp_vport_vfid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
162{
163 return mlxsw_sp_vport->vport.vfid->vfid;
164}
165
166static inline struct mlxsw_sp_port *
167mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
168{
169 struct mlxsw_sp_port *mlxsw_sp_vport;
170
171 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
172 vport.list) {
173 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
174 return mlxsw_sp_vport;
175 }
176
177 return NULL;
178}
179
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200180enum mlxsw_sp_flood_table {
181 MLXSW_SP_FLOOD_TABLE_UC,
182 MLXSW_SP_FLOOD_TABLE_BM,
183};
184
185int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
186int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
187
188int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
189void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
190int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
191void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
192void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
193int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
194 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
195 u16 vid);
196int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
197 u16 vid_end, bool is_member, bool untagged);
198int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
199 u16 vid);
200int mlxsw_sp_port_kill_vid(struct net_device *dev,
201 __be16 __always_unused proto, u16 vid);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100202int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 vfid,
Ido Schimmel19ae6122015-12-15 16:03:39 +0100203 bool set, bool only_uc);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200204
205#endif