| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #include <linux/linkage.h> |
| 2 | #include <asm/assembler.h> |
| George G. Davis | 3a1e501 | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 3 | #include "abort-macro.S" |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | /* |
| 5 | * Function: v6_early_abort |
| 6 | * |
| Russell King | da74047 | 2011-06-26 16:01:26 +0100 | [diff] [blame] | 7 | * Params : r2 = pt_regs |
| 8 | * : r4 = aborted context pc |
| Russell King | 3e287be | 2011-06-26 14:35:07 +0100 | [diff] [blame] | 9 | * : r5 = aborted context psr |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
| Russell King | da74047 | 2011-06-26 16:01:26 +0100 | [diff] [blame] | 11 | * Returns : r4 - r11, r13 preserved |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | * |
| 13 | * Purpose : obtain information about current aborted instruction. |
| George G. Davis | 3a1e501 | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 14 | * Note: we read user space. This means we might cause a data |
| 15 | * abort here if the I-TLB and D-TLB aren't seeing the same |
| 16 | * picture. Unfortunately, this does happen. We live with it. |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | */ |
| 18 | .align 5 |
| 19 | ENTRY(v6_early_abort) |
| Russell King | 7db44c7 | 2011-01-17 15:35:37 +0000 | [diff] [blame] | 20 | #ifdef CONFIG_CPU_V6 |
| Seth Forshee | 25ef4a6 | 2009-03-02 22:39:36 +0100 | [diff] [blame] | 21 | sub r1, sp, #4 @ Get unused stack location |
| 22 | strex r0, r1, [r1] @ Clear the exclusive monitor |
| Russell King | 7db44c7 | 2011-01-17 15:35:37 +0000 | [diff] [blame] | 23 | #elif defined(CONFIG_CPU_32v6K) |
| 24 | clrex |
| Catalin Marinas | 2c3a054 | 2005-10-02 22:34:35 +0100 | [diff] [blame] | 25 | #endif |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | mrc p15, 0, r1, c5, c0, 0 @ get FSR |
| 27 | mrc p15, 0, r0, c6, c0, 0 @ get FAR |
| George G. Davis | 3a1e501 | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 28 | /* |
| Will Deacon | f0c4b8d | 2012-04-20 17:20:08 +0100 | [diff] [blame] | 29 | * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. |
| George G. Davis | 3a1e501 | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 30 | */ |
| Will Deacon | f0c4b8d | 2012-04-20 17:20:08 +0100 | [diff] [blame] | 31 | #ifdef CONFIG_ARM_ERRATA_326103 |
| 32 | ldr ip, =0x4107b36 |
| 33 | mrc p15, 0, r3, c0, c0, 0 @ get processor id |
| 34 | teq ip, r3, lsr #4 @ r0 ARM1136? |
| Russell King | da74047 | 2011-06-26 16:01:26 +0100 | [diff] [blame] | 35 | bne do_DataAbort |
| Will Deacon | f0c4b8d | 2012-04-20 17:20:08 +0100 | [diff] [blame] | 36 | tst r5, #PSR_J_BIT @ Java? |
| 37 | tsteq r5, #PSR_T_BIT @ Thumb? |
| 38 | bne do_DataAbort |
| 39 | bic r1, r1, #1 << 11 @ clear bit 11 of FSR |
| 40 | ldr r3, [r4] @ read aborted ARM instruction |
| Catalin Marinas | 2658485 | 2009-05-30 14:00:18 +0100 | [diff] [blame] | 41 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
| Will Deacon | f0c4b8d | 2012-04-20 17:20:08 +0100 | [diff] [blame] | 42 | rev r3, r3 |
| Catalin Marinas | 2658485 | 2009-05-30 14:00:18 +0100 | [diff] [blame] | 43 | #endif |
| Russell King | 0d147db | 2011-06-26 14:42:02 +0100 | [diff] [blame] | 44 | do_ldrd_abort tmp=ip, insn=r3 |
| George G. Davis | 3a1e501 | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 45 | tst r3, #1 << 20 @ L = 0 -> write |
| 46 | orreq r1, r1, #1 << 11 @ yes. |
| Will Deacon | f0c4b8d | 2012-04-20 17:20:08 +0100 | [diff] [blame] | 47 | #endif |
| Russell King | da74047 | 2011-06-26 16:01:26 +0100 | [diff] [blame] | 48 | b do_DataAbort |