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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Trantor T128/T128F/T228 defines
3 * Note : architecturally, the T100 and T128 are different and won't work
4 *
5 * Copyright 1993, Drew Eckhardt
6 * Visionary Computing
7 * (Unix and Linux consulting and custom programming)
8 * drew@colorado.edu
9 * +1 (303) 440-4894
10 *
Henne667c6672006-11-08 19:56:28 -080011 * For more information, please consult
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 *
13 * Trantor Systems, Ltd.
14 * T128/T128F/T228 SCSI Host Adapter
15 * Hardware Specifications
Henne667c6672006-11-08 19:56:28 -080016 *
17 * Trantor Systems, Ltd.
Linus Torvalds1da177e2005-04-16 15:20:36 -070018 * 5415 Randall Place
19 * Fremont, CA 94538
20 * 1+ (415) 770-1400, FAX 1+ (415) 770-9910
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 */
22
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#ifndef T128_H
24#define T128_H
25
Olaf Hering44456d32005-07-27 11:45:17 -070026#define TDEBUG 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#define TDEBUG_INIT 0x1
28#define TDEBUG_TRANSFER 0x2
29
30/*
Henne667c6672006-11-08 19:56:28 -080031 * The trantor boards are memory mapped. They use an NCR5380 or
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 * equivalent (my sample board had part second sourced from ZILOG).
Henne667c6672006-11-08 19:56:28 -080033 * NCR's recommended "Pseudo-DMA" architecture is used, where
Linus Torvalds1da177e2005-04-16 15:20:36 -070034 * a PAL drives the DMA signals on the 5380 allowing fast, blind
Henne667c6672006-11-08 19:56:28 -080035 * transfers with proper handshaking.
Linus Torvalds1da177e2005-04-16 15:20:36 -070036 */
37
38/*
Henne667c6672006-11-08 19:56:28 -080039 * Note : a boot switch is provided for the purpose of informing the
Linus Torvalds1da177e2005-04-16 15:20:36 -070040 * firmware to boot or not boot from attached SCSI devices. So, I imagine
41 * there are fewer people who've yanked the ROM like they do on the Seagate
42 * to make bootup faster, and I'll probably use this for autodetection.
43 */
44#define T_ROM_OFFSET 0
45
46/*
47 * Note : my sample board *WAS NOT* populated with the SRAM, so this
48 * can't be used for autodetection without a ROM present.
49 */
50#define T_RAM_OFFSET 0x1800
51
52/*
53 * All of the registers are allocated 32 bytes of address space, except
54 * for the data register (read/write to/from the 5380 in pseudo-DMA mode)
55 */
56#define T_CONTROL_REG_OFFSET 0x1c00 /* rw */
57#define T_CR_INT 0x10 /* Enable interrupts */
58#define T_CR_CT 0x02 /* Reset watchdog timer */
59
60#define T_STATUS_REG_OFFSET 0x1c20 /* ro */
61#define T_ST_BOOT 0x80 /* Boot switch */
62#define T_ST_S3 0x40 /* User settable switches, */
63#define T_ST_S2 0x20 /* read 0 when switch is on, 1 off */
64#define T_ST_S1 0x10
65#define T_ST_PS2 0x08 /* Set for Microchannel 228 */
66#define T_ST_RDY 0x04 /* 5380 DRQ */
67#define T_ST_TIM 0x02 /* indicates 40us watchdog timer fired */
68#define T_ST_ZERO 0x01 /* Always zero */
69
70#define T_5380_OFFSET 0x1d00 /* 8 registers here, see NCR5380.h */
71
72#define T_DATA_REG_OFFSET 0x1e00 /* rw 512 bytes long */
73
74#ifndef ASM
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
76#ifndef CMD_PER_LUN
77#define CMD_PER_LUN 2
78#endif
79
80#ifndef CAN_QUEUE
Henne667c6672006-11-08 19:56:28 -080081#define CAN_QUEUE 32
Linus Torvalds1da177e2005-04-16 15:20:36 -070082#endif
83
Linus Torvalds1da177e2005-04-16 15:20:36 -070084#define NCR5380_implementation_fields \
85 void __iomem *base
86
87#define NCR5380_local_declare() \
88 void __iomem *base
89
90#define NCR5380_setup(instance) \
91 base = ((struct NCR5380_hostdata *)(instance->hostdata))->base
92
93#define T128_address(reg) (base + T_5380_OFFSET + ((reg) * 0x20))
94
Henne667c6672006-11-08 19:56:28 -080095#if !(TDEBUG & TDEBUG_TRANSFER)
Linus Torvalds1da177e2005-04-16 15:20:36 -070096#define NCR5380_read(reg) readb(T128_address(reg))
97#define NCR5380_write(reg, value) writeb((value),(T128_address(reg)))
98#else
99#define NCR5380_read(reg) \
100 (((unsigned char) printk("scsi%d : read register %d at address %08x\n"\
101 , instance->hostno, (reg), T128_address(reg))), readb(T128_address(reg)))
102
103#define NCR5380_write(reg, value) { \
Henne667c6672006-11-08 19:56:28 -0800104 printk("scsi%d : write %02x to register %d at address %08x\n", \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 instance->hostno, (value), (reg), T128_address(reg)); \
106 writeb((value), (T128_address(reg))); \
107}
108#endif
109
110#define NCR5380_intr t128_intr
111#define do_NCR5380_intr do_t128_intr
112#define NCR5380_queue_command t128_queue_command
113#define NCR5380_abort t128_abort
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114#define NCR5380_bus_reset t128_bus_reset
Finn Thain8c325132014-11-12 16:11:58 +1100115#define NCR5380_info t128_info
Al Virodd7ab712013-03-31 01:15:54 -0400116#define NCR5380_show_info t128_show_info
117#define NCR5380_write_info t128_write_info
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118
Henne667c6672006-11-08 19:56:28 -0800119/* 15 14 12 10 7 5 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 1101 0100 1010 1000 */
Henne667c6672006-11-08 19:56:28 -0800121
122#define T128_IRQS 0xc4a8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124#endif /* ndef ASM */
125#endif /* T128_H */