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Thomas Gleixnerce4c61f2006-05-23 11:43:28 +02001/*
2 * drivers/mtd/ndfc.c
3 *
4 * Overview:
Sean MacLennana808ad32008-12-10 13:16:34 +00005 * Platform independent driver for NDFC (NanD Flash Controller)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +02006 * integrated into EP440 cores
7 *
Sean MacLennana808ad32008-12-10 13:16:34 +00008 * Ported to an OF platform driver by Sean MacLennan
9 *
10 * The NDFC supports multiple chips, but this driver only supports a
11 * single chip since I do not have access to any boards with
12 * multiple chips.
13 *
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020014 * Author: Thomas Gleixner
15 *
16 * Copyright 2006 IBM
Sean MacLennana808ad32008-12-10 13:16:34 +000017 * Copyright 2008 PIKA Technologies
18 * Sean MacLennan <smaclennan@pikatech.com>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020019 *
20 * This program is free software; you can redistribute it and/or modify it
21 * under the terms of the GNU General Public License as published by the
22 * Free Software Foundation; either version 2 of the License, or (at your
23 * option) any later version.
24 *
25 */
26#include <linux/module.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/nand_ecc.h>
29#include <linux/mtd/partitions.h>
30#include <linux/mtd/ndfc.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020032#include <linux/mtd/mtd.h>
Sean MacLennana808ad32008-12-10 13:16:34 +000033#include <linux/of_platform.h>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020034#include <asm/io.h>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020035
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020036
37struct ndfc_controller {
Grant Likely2dc11582010-08-06 09:25:50 -060038 struct platform_device *ofdev;
Sean MacLennana808ad32008-12-10 13:16:34 +000039 void __iomem *ndfcbase;
40 struct mtd_info mtd;
41 struct nand_chip chip;
42 int chip_select;
43 struct nand_hw_control ndfc_control;
44#ifdef CONFIG_MTD_PARTITIONS
45 struct mtd_partition *parts;
46#endif
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020047};
48
49static struct ndfc_controller ndfc_ctrl;
50
51static void ndfc_select_chip(struct mtd_info *mtd, int chip)
52{
53 uint32_t ccr;
54 struct ndfc_controller *ndfc = &ndfc_ctrl;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020055
Sean MacLennana808ad32008-12-10 13:16:34 +000056 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020057 if (chip >= 0) {
58 ccr &= ~NDFC_CCR_BS_MASK;
Sean MacLennana808ad32008-12-10 13:16:34 +000059 ccr |= NDFC_CCR_BS(chip + ndfc->chip_select);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020060 } else
61 ccr |= NDFC_CCR_RESET_CE;
Sean MacLennana808ad32008-12-10 13:16:34 +000062 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020063}
64
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020065static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020066{
Thomas Gleixner1794c132006-06-22 13:06:43 +020067 struct ndfc_controller *ndfc = &ndfc_ctrl;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020068
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020069 if (cmd == NAND_CMD_NONE)
70 return;
71
72 if (ctrl & NAND_CLE)
Thomas Gleixner1794c132006-06-22 13:06:43 +020073 writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020074 else
Thomas Gleixner1794c132006-06-22 13:06:43 +020075 writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020076}
77
78static int ndfc_ready(struct mtd_info *mtd)
79{
80 struct ndfc_controller *ndfc = &ndfc_ctrl;
81
Sean MacLennana808ad32008-12-10 13:16:34 +000082 return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020083}
84
85static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
86{
87 uint32_t ccr;
88 struct ndfc_controller *ndfc = &ndfc_ctrl;
89
Sean MacLennana808ad32008-12-10 13:16:34 +000090 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020091 ccr |= NDFC_CCR_RESET_ECC;
Sean MacLennana808ad32008-12-10 13:16:34 +000092 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020093 wmb();
94}
95
96static int ndfc_calculate_ecc(struct mtd_info *mtd,
97 const u_char *dat, u_char *ecc_code)
98{
99 struct ndfc_controller *ndfc = &ndfc_ctrl;
100 uint32_t ecc;
101 uint8_t *p = (uint8_t *)&ecc;
102
103 wmb();
Sean MacLennana808ad32008-12-10 13:16:34 +0000104 ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
105 /* The NDFC uses Smart Media (SMC) bytes order */
Feng Kan76c23c32009-08-25 11:27:20 -0700106 ecc_code[0] = p[1];
107 ecc_code[1] = p[2];
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200108 ecc_code[2] = p[3];
109
110 return 0;
111}
112
113/*
114 * Speedups for buffer read/write/verify
115 *
116 * NDFC allows 32bit read/write of data. So we can speed up the buffer
117 * functions. No further checking, as nand_base will always read/write
118 * page aligned.
119 */
120static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
121{
122 struct ndfc_controller *ndfc = &ndfc_ctrl;
123 uint32_t *p = (uint32_t *) buf;
124
125 for(;len > 0; len -= 4)
Sean MacLennana808ad32008-12-10 13:16:34 +0000126 *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200127}
128
129static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
130{
131 struct ndfc_controller *ndfc = &ndfc_ctrl;
132 uint32_t *p = (uint32_t *) buf;
133
134 for(;len > 0; len -= 4)
Sean MacLennana808ad32008-12-10 13:16:34 +0000135 out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200136}
137
138static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
139{
140 struct ndfc_controller *ndfc = &ndfc_ctrl;
141 uint32_t *p = (uint32_t *) buf;
142
143 for(;len > 0; len -= 4)
Sean MacLennana808ad32008-12-10 13:16:34 +0000144 if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA))
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200145 return -EFAULT;
146 return 0;
147}
148
149/*
150 * Initialize chip structure
151 */
Sean MacLennana808ad32008-12-10 13:16:34 +0000152static int ndfc_chip_init(struct ndfc_controller *ndfc,
153 struct device_node *node)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200154{
Sean MacLennana808ad32008-12-10 13:16:34 +0000155#ifdef CONFIG_MTD_PARTITIONS
156#ifdef CONFIG_MTD_CMDLINE_PARTS
157 static const char *part_types[] = { "cmdlinepart", NULL };
158#else
159 static const char *part_types[] = { NULL };
160#endif
161#endif
162 struct device_node *flash_np;
163 struct nand_chip *chip = &ndfc->chip;
164 int ret;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200165
166 chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
167 chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200168 chip->cmd_ctrl = ndfc_hwcontrol;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200169 chip->dev_ready = ndfc_ready;
170 chip->select_chip = ndfc_select_chip;
171 chip->chip_delay = 50;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200172 chip->controller = &ndfc->ndfc_control;
173 chip->read_buf = ndfc_read_buf;
174 chip->write_buf = ndfc_write_buf;
175 chip->verify_buf = ndfc_verify_buf;
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200176 chip->ecc.correct = nand_correct_data;
177 chip->ecc.hwctl = ndfc_enable_hwecc;
178 chip->ecc.calculate = ndfc_calculate_ecc;
179 chip->ecc.mode = NAND_ECC_HW;
180 chip->ecc.size = 256;
181 chip->ecc.bytes = 3;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200182
Sean MacLennana808ad32008-12-10 13:16:34 +0000183 ndfc->mtd.priv = chip;
184 ndfc->mtd.owner = THIS_MODULE;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200185
Sean MacLennana808ad32008-12-10 13:16:34 +0000186 flash_np = of_get_next_child(node, NULL);
187 if (!flash_np)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200188 return -ENODEV;
Sean MacLennana808ad32008-12-10 13:16:34 +0000189
190 ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s",
Kay Sieversc36f1e32009-03-24 16:38:21 -0700191 dev_name(&ndfc->ofdev->dev), flash_np->name);
Sean MacLennana808ad32008-12-10 13:16:34 +0000192 if (!ndfc->mtd.name) {
193 ret = -ENOMEM;
194 goto err;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200195 }
196
Sean MacLennana808ad32008-12-10 13:16:34 +0000197 ret = nand_scan(&ndfc->mtd, 1);
198 if (ret)
199 goto err;
200
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200201#ifdef CONFIG_MTD_PARTITIONS
Sean MacLennana808ad32008-12-10 13:16:34 +0000202 ret = parse_mtd_partitions(&ndfc->mtd, part_types, &ndfc->parts, 0);
203 if (ret < 0)
204 goto err;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200205
Sean MacLennana808ad32008-12-10 13:16:34 +0000206#ifdef CONFIG_MTD_OF_PARTS
207 if (ret == 0) {
208 ret = of_mtd_parse_partitions(&ndfc->ofdev->dev, flash_np,
209 &ndfc->parts);
210 if (ret < 0)
211 goto err;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200212 }
Sean MacLennana808ad32008-12-10 13:16:34 +0000213#endif
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200214
Sean MacLennana808ad32008-12-10 13:16:34 +0000215 if (ret > 0)
216 ret = add_mtd_partitions(&ndfc->mtd, ndfc->parts, ret);
217 else
218#endif
219 ret = add_mtd_device(&ndfc->mtd);
220
221err:
222 of_node_put(flash_np);
223 if (ret)
224 kfree(ndfc->mtd.name);
225 return ret;
226}
227
Grant Likely1c48a5c2011-02-17 02:43:24 -0700228static int __devinit ndfc_probe(struct platform_device *ofdev)
Sean MacLennana808ad32008-12-10 13:16:34 +0000229{
230 struct ndfc_controller *ndfc = &ndfc_ctrl;
Ian Munsie766f2712010-10-01 17:06:08 +1000231 const __be32 *reg;
Sean MacLennana808ad32008-12-10 13:16:34 +0000232 u32 ccr;
233 int err, len;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200234
235 spin_lock_init(&ndfc->ndfc_control.lock);
236 init_waitqueue_head(&ndfc->ndfc_control.wq);
Sean MacLennana808ad32008-12-10 13:16:34 +0000237 ndfc->ofdev = ofdev;
238 dev_set_drvdata(&ofdev->dev, ndfc);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200239
Sean MacLennana808ad32008-12-10 13:16:34 +0000240 /* Read the reg property to get the chip select */
Grant Likely61c7a082010-04-13 16:12:29 -0700241 reg = of_get_property(ofdev->dev.of_node, "reg", &len);
Sean MacLennana808ad32008-12-10 13:16:34 +0000242 if (reg == NULL || len != 12) {
243 dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
244 return -ENOENT;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200245 }
Ian Munsie766f2712010-10-01 17:06:08 +1000246 ndfc->chip_select = be32_to_cpu(reg[0]);
Sean MacLennana808ad32008-12-10 13:16:34 +0000247
Grant Likely61c7a082010-04-13 16:12:29 -0700248 ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0);
Sean MacLennana808ad32008-12-10 13:16:34 +0000249 if (!ndfc->ndfcbase) {
250 dev_err(&ofdev->dev, "failed to get memory\n");
251 return -EIO;
252 }
253
254 ccr = NDFC_CCR_BS(ndfc->chip_select);
255
256 /* It is ok if ccr does not exist - just default to 0 */
Grant Likely61c7a082010-04-13 16:12:29 -0700257 reg = of_get_property(ofdev->dev.of_node, "ccr", NULL);
Sean MacLennana808ad32008-12-10 13:16:34 +0000258 if (reg)
Ian Munsie766f2712010-10-01 17:06:08 +1000259 ccr |= be32_to_cpup(reg);
Sean MacLennana808ad32008-12-10 13:16:34 +0000260
261 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
262
263 /* Set the bank settings if given */
Grant Likely61c7a082010-04-13 16:12:29 -0700264 reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL);
Sean MacLennana808ad32008-12-10 13:16:34 +0000265 if (reg) {
266 int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
Ian Munsie766f2712010-10-01 17:06:08 +1000267 out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg));
Sean MacLennana808ad32008-12-10 13:16:34 +0000268 }
269
Grant Likely61c7a082010-04-13 16:12:29 -0700270 err = ndfc_chip_init(ndfc, ofdev->dev.of_node);
Sean MacLennana808ad32008-12-10 13:16:34 +0000271 if (err) {
272 iounmap(ndfc->ndfcbase);
273 return err;
274 }
275
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200276 return 0;
277}
278
Grant Likely2dc11582010-08-06 09:25:50 -0600279static int __devexit ndfc_remove(struct platform_device *ofdev)
Sean MacLennana808ad32008-12-10 13:16:34 +0000280{
281 struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200282
Sean MacLennana808ad32008-12-10 13:16:34 +0000283 nand_release(&ndfc->mtd);
284
285 return 0;
286}
287
288static const struct of_device_id ndfc_match[] = {
289 { .compatible = "ibm,ndfc", },
290 {}
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200291};
Sean MacLennana808ad32008-12-10 13:16:34 +0000292MODULE_DEVICE_TABLE(of, ndfc_match);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200293
Grant Likely1c48a5c2011-02-17 02:43:24 -0700294static struct platform_driver ndfc_driver = {
Sean MacLennana808ad32008-12-10 13:16:34 +0000295 .driver = {
Grant Likely40182942010-04-13 16:13:02 -0700296 .name = "ndfc",
297 .owner = THIS_MODULE,
298 .of_match_table = ndfc_match,
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200299 },
Sean MacLennana808ad32008-12-10 13:16:34 +0000300 .probe = ndfc_probe,
301 .remove = __devexit_p(ndfc_remove),
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200302};
303
304static int __init ndfc_nand_init(void)
305{
Grant Likely1c48a5c2011-02-17 02:43:24 -0700306 return platform_driver_register(&ndfc_driver);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200307}
308
309static void __exit ndfc_nand_exit(void)
310{
Grant Likely1c48a5c2011-02-17 02:43:24 -0700311 platform_driver_unregister(&ndfc_driver);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200312}
313
314module_init(ndfc_nand_init);
315module_exit(ndfc_nand_exit);
316
317MODULE_LICENSE("GPL");
318MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
Sean MacLennana808ad32008-12-10 13:16:34 +0000319MODULE_DESCRIPTION("OF Platform driver for NDFC");