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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver
3 * Basic data header
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#ifndef _NSP32_H
17#define _NSP32_H
18
Olaf Hering733482e2005-11-08 21:34:55 -080019#include <linux/version.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020//#define NSP32_DEBUG 9
21
22/*
23 * VENDOR/DEVICE ID
24 */
25#define PCI_VENDOR_ID_IODATA 0x10fc
26#define PCI_VENDOR_ID_WORKBIT 0x1145
27
28#define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
29#define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
30#define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
31#define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
32#define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
33#define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
34#define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
35#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
36#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009
37
38/*
39 * MODEL
40 */
41enum {
42 MODEL_IODATA = 0,
43 MODEL_KME = 1,
44 MODEL_WORKBIT = 2,
45 MODEL_LOGITEC = 3,
46 MODEL_PCI_WORKBIT = 4,
47 MODEL_PCI_LOGITEC = 5,
48 MODEL_PCI_MELCO = 6,
49};
50
51static char * nsp32_model[] = {
52 "I-O DATA CBSC-II CardBus card",
53 "KME SCSI CardBus card",
54 "Workbit duo SCSI CardBus card",
55 "Logitec CardBus card with external ROM",
56 "Workbit / I-O DATA PCI card",
57 "Logitec PCI card with external ROM",
58 "Melco CardBus/PCI card with external ROM",
59};
60
61
62/*
63 * SCSI Generic Definitions
64 */
65#define EXTENDED_SDTR_LEN 0x03
66
67/* Little Endian */
68typedef u32 u32_le;
69typedef u16 u16_le;
70
71/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 * BASIC Definitions
73 */
74#ifndef TRUE
75# define TRUE 1
76#endif
77#ifndef FALSE
78# define FALSE 0
79#endif
80#define ASSERT 1
81#define NEGATE 0
82
83
84/*******************/
85/* normal register */
86/*******************/
87/*
88 * Don't access below register with Double Word:
89 * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0.
90 */
91#define IRQ_CONTROL 0x00 /* BASE+00, W, W */
92#define IRQ_STATUS 0x00 /* BASE+00, W, R */
93# define IRQSTATUS_LATCHED_MSG BIT(0)
94# define IRQSTATUS_LATCHED_IO BIT(1)
95# define IRQSTATUS_LATCHED_CD BIT(2)
96# define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
97# define IRQSTATUS_RESELECT_OCCUER BIT(4)
98# define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
99# define IRQSTATUS_SCSIRESET_IRQ BIT(6)
100# define IRQSTATUS_TIMER_IRQ BIT(7)
101# define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
102# define IRQSTATUS_PCI_IRQ BIT(9)
103# define IRQSTATUS_BMCNTERR_IRQ BIT(10)
104# define IRQSTATUS_AUTOSCSI_IRQ BIT(11)
105# define PCI_IRQ_MASK BIT(12)
106# define TIMER_IRQ_MASK BIT(13)
107# define FIFO_IRQ_MASK BIT(14)
108# define SCSI_IRQ_MASK BIT(15)
109# define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \
110 TIMER_IRQ_MASK | \
111 FIFO_IRQ_MASK | \
112 SCSI_IRQ_MASK )
113# define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \
114 IRQSTATUS_PHASE_CHANGE_IRQ | \
115 IRQSTATUS_SCSIRESET_IRQ | \
116 IRQSTATUS_TIMER_IRQ | \
117 IRQSTATUS_FIFO_SHLD_IRQ | \
118 IRQSTATUS_PCI_IRQ | \
119 IRQSTATUS_BMCNTERR_IRQ | \
120 IRQSTATUS_AUTOSCSI_IRQ )
121
122#define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
123#define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
124# define CB_MMIO_MODE BIT(0)
125# define CB_IO_MODE BIT(1)
126# define BM_TEST BIT(2)
127# define BM_TEST_DIR BIT(3)
128# define DUAL_EDGE_ENABLE BIT(4)
129# define NO_TRANSFER_TO_HOST BIT(5)
130# define TRANSFER_GO BIT(7)
131# define BLIEND_MODE BIT(8)
132# define BM_START BIT(9)
133# define ADVANCED_BM_WRITE BIT(10)
134# define BM_SINGLE_MODE BIT(11)
135# define FIFO_TRUE_FULL BIT(12)
136# define FIFO_TRUE_EMPTY BIT(13)
137# define ALL_COUNTER_CLR BIT(14)
138# define FIFOTEST BIT(15)
139
140#define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
141
142#define TIMER_SET 0x06 /* BASE+06, W, R/W */
143# define TIMER_CNT_MASK (0xff)
144# define TIMER_STOP BIT(8)
145
146#define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
147#define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
148
149#define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
150# define FIFO_REST_MASK 0x1ff
151# define FIFO_EMPTY_SHLD_FLAG BIT(14)
152# define FIFO_FULL_SHLD_FLAG BIT(15)
153
154#define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
155# define SREQSMPLRATE_RATE0 BIT(0)
156# define SREQSMPLRATE_RATE1 BIT(1)
157# define SAMPLING_ENABLE BIT(2)
158# define SMPL_40M (0) /* 40MHz: 0-100ns/period */
159# define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */
160# define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */
161
162#define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
163# define BUSCTL_SEL BIT(0)
164# define BUSCTL_RST BIT(1)
165# define BUSCTL_DATAOUT_ENB BIT(2)
166# define BUSCTL_ATN BIT(3)
167# define BUSCTL_ACK BIT(4)
168# define BUSCTL_BSY BIT(5)
169# define AUTODIRECTION BIT(6)
170# define ACKENB BIT(7)
171
172#define CLR_COUNTER 0x12 /* BASE+12, B, W */
173# define ACK_COUNTER_CLR BIT(0)
174# define SREQ_COUNTER_CLR BIT(1)
175# define FIFO_HOST_POINTER_CLR BIT(2)
176# define FIFO_REST_COUNT_CLR BIT(3)
177# define BM_COUNTER_CLR BIT(4)
178# define SAVED_ACK_CLR BIT(5)
179# define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \
180 SREQ_COUNTER_CLR | \
181 FIFO_HOST_POINTER_CLR | \
182 FIFO_REST_COUNT_CLR | \
183 BM_COUNTER_CLR | \
184 SAVED_ACK_CLR )
185
186#define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */
187# define BUSMON_MSG BIT(0)
188# define BUSMON_IO BIT(1)
189# define BUSMON_CD BIT(2)
190# define BUSMON_BSY BIT(3)
191# define BUSMON_ACK BIT(4)
192# define BUSMON_REQ BIT(5)
193# define BUSMON_SEL BIT(6)
194# define BUSMON_ATN BIT(7)
195
196#define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
197
198#define PARITY_CONTROL 0x16 /* BASE+16, B, W */
199# define PARITY_CHECK_ENABLE BIT(0)
200# define PARITY_ERROR_CLEAR BIT(1)
201#define PARITY_STATUS 0x16 /* BASE+16, B, R */
202//# define PARITY_CHECK_ENABLE BIT(0)
203# define PARITY_ERROR_NORMAL BIT(1)
204# define PARITY_ERROR_LSB BIT(1)
205# define PARITY_ERROR_MSB BIT(2)
206
207#define RESELECT_ID 0x18 /* BASE+18, B, R */
208
209#define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
210# define CLEAR_CDB_FIFO_POINTER BIT(0)
211# define AUTO_COMMAND_PHASE BIT(1)
212# define AUTOSCSI_START BIT(2)
213# define AUTOSCSI_RESTART BIT(3)
214# define AUTO_PARAMETER BIT(4)
215# define AUTO_ATN BIT(5)
216# define AUTO_MSGIN_00_OR_04 BIT(6)
217# define AUTO_MSGIN_02 BIT(7)
218# define AUTO_MSGIN_03 BIT(8)
219
220#define SET_ARBIT 0x1a /* BASE+1a, B, W */
221# define ARBIT_GO BIT(0)
222# define ARBIT_CLEAR BIT(1)
223
224#define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
225//# define ARBIT_GO BIT(0)
226# define ARBIT_WIN BIT(1)
227# define ARBIT_FAIL BIT(2)
228# define AUTO_PARAMETER_VALID BIT(3)
229# define SGT_VALID BIT(4)
230
231#define SYNC_REG 0x1c /* BASE+1c, B, R/W */
232
233#define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
234
235#define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
236#define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
237#define SCSI_DATA_IN 0x22 /* BASE+22, B, R */
238
239#define SCAM_CONTROL 0x24 /* BASE+24, B, W */
240#define SCAM_STATUS 0x24 /* BASE+24, B, R */
241# define SCAM_MSG BIT(0)
242# define SCAM_IO BIT(1)
243# define SCAM_CD BIT(2)
244# define SCAM_BSY BIT(3)
245# define SCAM_SEL BIT(4)
246# define SCAM_XFEROK BIT(5)
247
248#define SCAM_DATA 0x26 /* BASE+26, B, R/W */
249# define SD0 BIT(0)
250# define SD1 BIT(1)
251# define SD2 BIT(2)
252# define SD3 BIT(3)
253# define SD4 BIT(4)
254# define SD5 BIT(5)
255# define SD6 BIT(6)
256# define SD7 BIT(7)
257
258#define SACK_CNT 0x28 /* BASE+28, DW, R/W */
259#define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
260
261#define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
262#define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
263#define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
264
265#define BM_CNT 0x38 /* BASE+38, DW, R/W */
266# define BM_COUNT_MASK 0x0001ffffUL
267# define SGTEND BIT(31) /* Last SGT marker */
268
269#define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
270#define WAIT_REG 0x40 /* Bi only */
271
272#define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
273# define COMMAND_PHASE BIT(0)
274# define DATA_IN_PHASE BIT(1)
275# define DATA_OUT_PHASE BIT(2)
276# define MSGOUT_PHASE BIT(3)
277# define STATUS_PHASE BIT(4)
278# define ILLEGAL_PHASE BIT(5)
279# define BUS_FREE_OCCUER BIT(6)
280# define MSG_IN_OCCUER BIT(7)
281# define MSG_OUT_OCCUER BIT(8)
282# define SELECTION_TIMEOUT BIT(9)
283# define MSGIN_00_VALID BIT(10)
284# define MSGIN_02_VALID BIT(11)
285# define MSGIN_03_VALID BIT(12)
286# define MSGIN_04_VALID BIT(13)
287# define AUTOSCSI_BUSY BIT(15)
288
289#define SCSI_CSB_IN 0x42 /* BASE+42, B, R */
290
291#define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
292# define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
293# define MV_VALID BIT(7)
294
295#define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
296#define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */
297
298#define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
299#define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
300#define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
301#define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
302
303
304/********************/
305/* indexed register */
306/********************/
307
308#define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
309# define CLOCK_2 BIT(0) /* MCLK/2 */
310# define CLOCK_4 BIT(1) /* MCLK/4 */
311# define PCICLK BIT(7) /* PCICLK (33MHz) */
312
313#define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
314# define BPWR BIT(0)
315# define SENSE BIT(1) /* Read Only */
316
317#define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
318#define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
319# define LED_ON (0)
320# define LED_OFF BIT(0)
321
322#define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
323# define IRQSELECT_RESELECT_IRQ BIT(0)
324# define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
325# define IRQSELECT_SCSIRESET_IRQ BIT(2)
326# define IRQSELECT_TIMER_IRQ BIT(3)
327# define IRQSELECT_FIFO_SHLD_IRQ BIT(4)
328# define IRQSELECT_TARGET_ABORT_IRQ BIT(5)
329# define IRQSELECT_MASTER_ABORT_IRQ BIT(6)
330# define IRQSELECT_SERR_IRQ BIT(7)
331# define IRQSELECT_PERR_IRQ BIT(8)
332# define IRQSELECT_BMCNTERR_IRQ BIT(9)
333# define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
334
335#define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */
336# define OLD_MSG BIT(0)
337# define OLD_IO BIT(1)
338# define OLD_CD BIT(2)
339# define OLD_BUSY BIT(3)
340
341#define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
342#define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
343
344#define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
345# define ROM_WRITE_ENB BIT(0)
346# define IO_ACCESS_ENB BIT(1)
347# define ROM_ADR_CLEAR BIT(2)
348
349#define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
350
351#define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
352
353#define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */
354# define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
355# define OEM1 BIT(2) /* OEM select */
356# define OPTB BIT(3) /* KME mode select */
357# define OPTC BIT(4) /* KME mode select */
358# define OPTD BIT(5) /* KME mode select */
359# define OPTE BIT(6) /* KME mode select */
360# define OPTF BIT(7) /* Power management */
361
362#define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
363#define MISC_RD 0x0c
364# define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
365# define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
366# define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */
367# define DELAYED_BMSTART BIT(3)
368# define MASTER_TERMINATION_SELECT BIT(4)
369# define BMREQ_NEGATE_TIMING_SEL BIT(5)
370# define AUTOSEL_TIMING_SEL BIT(6)
371# define MISC_MABORT_MASK BIT(7)
372# define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
373
374#define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
375# define BM_CYCLE0 BIT(0)
376# define BM_CYCLE1 BIT(1)
377# define BM_FRAME_ASSERT_TIMING BIT(2)
378# define BM_IRDY_ASSERT_TIMING BIT(3)
379# define BM_SINGLE_BUS_MASTER BIT(4)
380# define MEMRD_CMD0 BIT(5)
381# define SGT_AUTO_PARA_MEMED_CMD BIT(6)
382# define MEMRD_CMD1 BIT(7)
383
384
385#define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
386# define SREQ_EDGH_SELECT BIT(0)
387
388#define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */
389# define REQCNT_UP BIT(0)
390# define ACKCNT_UP BIT(1)
391# define BMADR_UP BIT(4)
392# define BMCNT_UP BIT(5)
393# define SGT_CNT_UP BIT(7)
394
395#define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
396#define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
397#define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
398#define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
399#define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
400
401#define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */
402# define SCL BIT(0)
403# define ENA BIT(1)
404# define SDA BIT(2)
405
406#define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
407#define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
408#define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
409#define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
410#define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
411#define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
412#define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
413#define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
414#define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
415#define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
416#define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
417#define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
418#define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
419#define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
420
421
422/*
423 * Useful Bus Monitor status combinations.
424 */
425#define BUSMON_BUS_FREE 0
426#define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ )
427#define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
428#define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ )
429#define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ )
430#define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ )
431#define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
432#define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL)
433#define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL)
434
435#define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK )
436#define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK )
437#define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK )
438#define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK )
439#define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK )
440#define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )
441#define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO )
442
443
444/************************************************************************
445 * structure for DMA/Scatter Gather list
446 */
447#define NSP32_SG_SIZE SG_ALL
448
449typedef struct _nsp32_sgtable {
450 /* values must be little endian */
451 u32_le addr; /* transfer address */
452 u32_le len; /* transfer length. BIT(31) is for SGT_END mark */
453} __attribute__ ((packed)) nsp32_sgtable;
454
455typedef struct _nsp32_sglun {
456 nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */
457} __attribute__ ((packed)) nsp32_sglun;
458#define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN)
459
460/* Auto parameter mode memory map. */
461/* All values must be little endian. */
462typedef struct _nsp32_autoparam {
463 u8 cdb[4 * 0x10]; /* SCSI Command */
464 u32_le msgout; /* outgoing messages */
465 u8 syncreg; /* sync register value */
466 u8 ackwidth; /* ack width register value */
467 u8 target_id; /* target/host device id */
468 u8 sample_reg; /* hazard killer sampling rate */
469 u16_le command_control; /* command control register */
470 u16_le transfer_control; /* transfer control register */
471 u32_le sgt_pointer; /* SG table physical address for DMA */
472 u32_le dummy[2];
473} __attribute__ ((packed)) nsp32_autoparam; /* must be packed struct */
474
475/*
476 * host data structure
477 */
478/* message in/out buffer */
479#define MSGOUTBUF_MAX 20
480#define MSGINBUF_MAX 20
481
482/* flag for trans_method */
483#define NSP32_TRANSFER_BUSMASTER BIT(0)
484#define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
485#define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */
486
487
488/*
489 * structure for connected LUN dynamic data
490 *
491 * Note: Currently tagged queuing is disabled, each nsp32_lunt holds
492 * one SCSI command and one state.
493 */
494#define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
495#define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
496
497typedef struct _nsp32_lunt {
498 struct scsi_cmnd *SCpnt; /* Current Handling struct scsi_cmnd */
499 unsigned long save_datp; /* Save Data Pointer - saved position from initial address */
500 int msgin03; /* auto msg in 03 flag */
501 unsigned int sg_num; /* Total number of SG entries */
502 int cur_entry; /* Current SG entry number */
503 nsp32_sglun *sglun; /* sg table per lun */
504 dma_addr_t sglun_paddr; /* sglun physical address */
505} nsp32_lunt;
506
507
508/*
509 * SCSI TARGET/LUN definition
510 */
511#define NSP32_HOST_SCSIID 7 /* SCSI initiator is everytime defined as 7 */
512#define MAX_TARGET 8
513#define MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */
514
515
516typedef struct _nsp32_sync_table {
517 unsigned char period_num; /* period number */
518 unsigned char ackwidth; /* ack width designated by period */
519 unsigned char start_period; /* search range - start period */
520 unsigned char end_period; /* search range - end period */
521 unsigned char sample_rate; /* hazard killer parameter */
522} nsp32_sync_table;
523
524
525/*
526 * structure for target device static data
527 */
528/* flag for nsp32_target.sync_flag */
529#define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
530#define SDTR_TARGET BIT(1) /* sending SDTR from target */
531#define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */
532
533/* syncronous period value for nsp32_target.config_max */
534#define FAST5M 0x32
535#define FAST10M 0x19
536#define ULTRA20M 0x0c
537
538/* flag for nsp32_target.{sync_offset}, period */
539#define ASYNC_OFFSET 0 /* asynchronous transfer */
540#define SYNC_OFFSET 0xf /* synchronous transfer max offset */
541
542/* syncreg:
543 bit:07 06 05 04 03 02 01 00
544 ---PERIOD-- ---OFFSET-- */
545#define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f))
546
547typedef struct _nsp32_target {
548 unsigned char syncreg; /* value for SYNCREG */
549 unsigned char ackwidth; /* value for ACKWIDTH */
550 unsigned char period; /* sync period (0-255) */
551 unsigned char offset; /* sync offset (0-15) */
552 int sync_flag; /* SDTR_*, 0 */
553 int limit_entry; /* max speed limit entry designated
554 by EEPROM configuration */
555 unsigned char sample_reg; /* SREQ hazard killer register */
556} nsp32_target;
557
558typedef struct _nsp32_hw_data {
559 int IrqNumber;
560 int BaseAddress;
561 int NumAddress;
562 void __iomem *MmioAddress;
563#define NSP32_MMIO_OFFSET 0x0800
564 unsigned long MmioLength;
565
566 struct scsi_cmnd *CurrentSC;
567
568 struct pci_dev *Pci;
569 const struct pci_device_id *pci_devid;
570 struct Scsi_Host *Host;
571 spinlock_t Lock;
572
573 char info_str[100];
574
575 /* allocated memory region */
576 nsp32_sglun *sg_list; /* sglist virtuxal address */
577 dma_addr_t sg_paddr; /* physical address of hw_sg_table */
578 nsp32_autoparam *autoparam; /* auto parameter transfer region */
579 dma_addr_t auto_paddr; /* physical address of autoparam */
580 int cur_entry; /* current sgt entry */
581
582 /* target/LUN */
583 nsp32_lunt *cur_lunt; /* Current connected LUN table */
584 nsp32_lunt lunt[MAX_TARGET][MAX_LUN]; /* All LUN table */
585
586 nsp32_target *cur_target; /* Current connected SCSI ID */
587 nsp32_target target[MAX_TARGET]; /* SCSI ID */
588 int cur_id; /* Current connected target ID */
589 int cur_lun; /* Current connected target LUN */
590
591 /* behavior setting parameters */
592 int trans_method; /* transfer method flag */
593 int resettime; /* Reset time */
594 int clock; /* clock dividing flag */
595 nsp32_sync_table *synct; /* sync_table determined by clock */
596 int syncnum; /* the max number of synct element */
597
598 /* message buffer */
599 unsigned char msgoutbuf[MSGOUTBUF_MAX]; /* msgout buffer */
600 char msgout_len; /* msgoutbuf length */
601 unsigned char msginbuf [MSGINBUF_MAX]; /* megin buffer */
602 char msgin_len; /* msginbuf length */
603
604} nsp32_hw_data;
605
606/*
607 * TIME definition
608 */
609#define RESET_HOLD_TIME 10000 /* reset time in us (SCSI-2 says the
610 minimum is 25us) */
611#define SEL_TIMEOUT_TIME 10000 /* 250ms defined in SCSI specification
612 (25.6us/1unit) */
613#define ARBIT_TIMEOUT_TIME 100 /* 100us */
614#define REQSACK_TIMEOUT_TIME 10000 /* max wait time for REQ/SACK assertion
615 or negation, 10000us == 10ms */
616
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617#endif /* _NSP32_H */
618/* end */