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Tien Hock Lohc5abbba2015-02-24 01:53:03 -08001/*
2 * Copyright (C) 2013 Altera Corporation
3 * Based on gpio-mpc8xxx.c
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/io.h>
20#include <linux/of_gpio.h>
21#include <linux/platform_device.h>
22
23#define ALTERA_GPIO_MAX_NGPIO 32
24#define ALTERA_GPIO_DATA 0x0
25#define ALTERA_GPIO_DIR 0x4
26#define ALTERA_GPIO_IRQ_MASK 0x8
27#define ALTERA_GPIO_EDGE_CAP 0xc
28
29/**
30* struct altera_gpio_chip
31* @mmchip : memory mapped chip structure.
32* @gpio_lock : synchronization lock so that new irq/set/get requests
33 will be blocked until the current one completes.
34* @interrupt_trigger : specifies the hardware configured IRQ trigger type
35 (rising, falling, both, high)
36* @mapped_irq : kernel mapped irq number.
37*/
38struct altera_gpio_chip {
39 struct of_mm_gpio_chip mmchip;
40 spinlock_t gpio_lock;
41 int interrupt_trigger;
42 int mapped_irq;
43};
44
45static void altera_gpio_irq_unmask(struct irq_data *d)
46{
47 struct altera_gpio_chip *altera_gc;
48 struct of_mm_gpio_chip *mm_gc;
49 unsigned long flags;
50 u32 intmask;
51
52 altera_gc = irq_data_get_irq_chip_data(d);
53 mm_gc = &altera_gc->mmchip;
54
55 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
56 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
57 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
58 intmask |= BIT(irqd_to_hwirq(d));
59 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
60 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
61}
62
63static void altera_gpio_irq_mask(struct irq_data *d)
64{
65 struct altera_gpio_chip *altera_gc;
66 struct of_mm_gpio_chip *mm_gc;
67 unsigned long flags;
68 u32 intmask;
69
70 altera_gc = irq_data_get_irq_chip_data(d);
71 mm_gc = &altera_gc->mmchip;
72
73 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
74 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
75 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
76 intmask &= ~BIT(irqd_to_hwirq(d));
77 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
78 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
79}
80
81/**
82 * This controller's IRQ type is synthesized in hardware, so this function
83 * just checks if the requested set_type matches the synthesized IRQ type
84 */
85static int altera_gpio_irq_set_type(struct irq_data *d,
86 unsigned int type)
87{
88 struct altera_gpio_chip *altera_gc;
89
90 altera_gc = irq_data_get_irq_chip_data(d);
91
92 if (type == IRQ_TYPE_NONE)
93 return 0;
94 if (type == IRQ_TYPE_LEVEL_HIGH &&
95 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
96 return 0;
97 if (type == IRQ_TYPE_EDGE_RISING &&
98 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_RISING)
99 return 0;
100 if (type == IRQ_TYPE_EDGE_FALLING &&
101 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_FALLING)
102 return 0;
103 if (type == IRQ_TYPE_EDGE_BOTH &&
104 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_BOTH)
105 return 0;
106
107 return -EINVAL;
108}
109
Daniel Lockyer38e003f2015-06-10 14:26:27 +0100110static unsigned int altera_gpio_irq_startup(struct irq_data *d)
111{
Tien Hock Lohc5abbba2015-02-24 01:53:03 -0800112 altera_gpio_irq_unmask(d);
113
114 return 0;
115}
116
117static struct irq_chip altera_irq_chip = {
118 .name = "altera-gpio",
119 .irq_mask = altera_gpio_irq_mask,
120 .irq_unmask = altera_gpio_irq_unmask,
121 .irq_set_type = altera_gpio_irq_set_type,
122 .irq_startup = altera_gpio_irq_startup,
123 .irq_shutdown = altera_gpio_irq_mask,
124};
125
126static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
127{
128 struct of_mm_gpio_chip *mm_gc;
129
130 mm_gc = to_of_mm_gpio_chip(gc);
131
132 return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
133}
134
135static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
136{
137 struct of_mm_gpio_chip *mm_gc;
138 struct altera_gpio_chip *chip;
139 unsigned long flags;
140 unsigned int data_reg;
141
142 mm_gc = to_of_mm_gpio_chip(gc);
143 chip = container_of(mm_gc, struct altera_gpio_chip, mmchip);
144
145 spin_lock_irqsave(&chip->gpio_lock, flags);
146 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
147 if (value)
148 data_reg |= BIT(offset);
149 else
150 data_reg &= ~BIT(offset);
151 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
152 spin_unlock_irqrestore(&chip->gpio_lock, flags);
153}
154
155static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
156{
157 struct of_mm_gpio_chip *mm_gc;
158 struct altera_gpio_chip *chip;
159 unsigned long flags;
160 unsigned int gpio_ddr;
161
162 mm_gc = to_of_mm_gpio_chip(gc);
163 chip = container_of(mm_gc, struct altera_gpio_chip, mmchip);
164
165 spin_lock_irqsave(&chip->gpio_lock, flags);
166 /* Set pin as input, assumes software controlled IP */
167 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
168 gpio_ddr &= ~BIT(offset);
169 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
170 spin_unlock_irqrestore(&chip->gpio_lock, flags);
171
172 return 0;
173}
174
175static int altera_gpio_direction_output(struct gpio_chip *gc,
176 unsigned offset, int value)
177{
178 struct of_mm_gpio_chip *mm_gc;
179 struct altera_gpio_chip *chip;
180 unsigned long flags;
181 unsigned int data_reg, gpio_ddr;
182
183 mm_gc = to_of_mm_gpio_chip(gc);
184 chip = container_of(mm_gc, struct altera_gpio_chip, mmchip);
185
186 spin_lock_irqsave(&chip->gpio_lock, flags);
187 /* Sets the GPIO value */
188 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
189 if (value)
190 data_reg |= BIT(offset);
191 else
192 data_reg &= ~BIT(offset);
193 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
194
195 /* Set pin as output, assumes software controlled IP */
196 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
197 gpio_ddr |= BIT(offset);
198 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
199 spin_unlock_irqrestore(&chip->gpio_lock, flags);
200
201 return 0;
202}
203
204static void altera_gpio_irq_edge_handler(unsigned int irq,
205 struct irq_desc *desc)
206{
207 struct altera_gpio_chip *altera_gc;
208 struct irq_chip *chip;
209 struct of_mm_gpio_chip *mm_gc;
210 struct irq_domain *irqdomain;
211 unsigned long status;
212 int i;
213
214 altera_gc = irq_desc_get_handler_data(desc);
215 chip = irq_desc_get_chip(desc);
216 mm_gc = &altera_gc->mmchip;
217 irqdomain = altera_gc->mmchip.gc.irqdomain;
218
219 chained_irq_enter(chip, desc);
220
221 while ((status =
222 (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
223 readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
224 writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
225 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
226 generic_handle_irq(irq_find_mapping(irqdomain, i));
227 }
228 }
229
230 chained_irq_exit(chip, desc);
231}
232
233
234static void altera_gpio_irq_leveL_high_handler(unsigned int irq,
235 struct irq_desc *desc)
236{
237 struct altera_gpio_chip *altera_gc;
238 struct irq_chip *chip;
239 struct of_mm_gpio_chip *mm_gc;
240 struct irq_domain *irqdomain;
241 unsigned long status;
242 int i;
243
244 altera_gc = irq_desc_get_handler_data(desc);
245 chip = irq_desc_get_chip(desc);
246 mm_gc = &altera_gc->mmchip;
247 irqdomain = altera_gc->mmchip.gc.irqdomain;
248
249 chained_irq_enter(chip, desc);
250
251 status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
252 status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
253
254 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
255 generic_handle_irq(irq_find_mapping(irqdomain, i));
256 }
257 chained_irq_exit(chip, desc);
258}
259
kbuild test robotc4b40492015-03-19 17:40:02 +0800260static int altera_gpio_probe(struct platform_device *pdev)
Tien Hock Lohc5abbba2015-02-24 01:53:03 -0800261{
262 struct device_node *node = pdev->dev.of_node;
263 int reg, ret;
264 struct altera_gpio_chip *altera_gc;
265
266 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
267 if (!altera_gc)
268 return -ENOMEM;
269
270 spin_lock_init(&altera_gc->gpio_lock);
271
272 if (of_property_read_u32(node, "altr,ngpio", &reg))
273 /* By default assume maximum ngpio */
274 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
275 else
276 altera_gc->mmchip.gc.ngpio = reg;
277
278 if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
279 dev_warn(&pdev->dev,
280 "ngpio is greater than %d, defaulting to %d\n",
281 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
282 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
283 }
284
285 altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
286 altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
287 altera_gc->mmchip.gc.get = altera_gpio_get;
288 altera_gc->mmchip.gc.set = altera_gpio_set;
289 altera_gc->mmchip.gc.owner = THIS_MODULE;
290 altera_gc->mmchip.gc.dev = &pdev->dev;
291
292 ret = of_mm_gpiochip_add(node, &altera_gc->mmchip);
293 if (ret) {
294 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
295 return ret;
296 }
297
298 platform_set_drvdata(pdev, altera_gc);
299
300 altera_gc->mapped_irq = platform_get_irq(pdev, 0);
301
302 if (altera_gc->mapped_irq < 0)
303 goto skip_irq;
304
305 if (of_property_read_u32(node, "altr,interrupt-type", &reg)) {
306 ret = -EINVAL;
307 dev_err(&pdev->dev,
308 "altr,interrupt-type value not set in device tree\n");
309 goto teardown;
310 }
311 altera_gc->interrupt_trigger = reg;
312
313 ret = gpiochip_irqchip_add(&altera_gc->mmchip.gc, &altera_irq_chip, 0,
314 handle_simple_irq, IRQ_TYPE_NONE);
315
316 if (ret) {
317 dev_info(&pdev->dev, "could not add irqchip\n");
318 return ret;
319 }
320
321 gpiochip_set_chained_irqchip(&altera_gc->mmchip.gc,
322 &altera_irq_chip,
323 altera_gc->mapped_irq,
324 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH ?
325 altera_gpio_irq_leveL_high_handler :
326 altera_gpio_irq_edge_handler);
327
328skip_irq:
329 return 0;
330teardown:
331 pr_err("%s: registration failed with status %d\n",
332 node->full_name, ret);
333
334 return ret;
335}
336
337static int altera_gpio_remove(struct platform_device *pdev)
338{
339 struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
340
341 gpiochip_remove(&altera_gc->mmchip.gc);
342
Masahiro Yamada1c8b5d62015-06-17 20:59:43 +0900343 return 0;
Tien Hock Lohc5abbba2015-02-24 01:53:03 -0800344}
345
346static const struct of_device_id altera_gpio_of_match[] = {
347 { .compatible = "altr,pio-1.0", },
348 {},
349};
350MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
351
352static struct platform_driver altera_gpio_driver = {
353 .driver = {
354 .name = "altera_gpio",
355 .of_match_table = of_match_ptr(altera_gpio_of_match),
356 },
357 .probe = altera_gpio_probe,
358 .remove = altera_gpio_remove,
359};
360
361static int __init altera_gpio_init(void)
362{
363 return platform_driver_register(&altera_gpio_driver);
364}
365subsys_initcall(altera_gpio_init);
366
367static void __exit altera_gpio_exit(void)
368{
369 platform_driver_unregister(&altera_gpio_driver);
370}
371module_exit(altera_gpio_exit);
372
373MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
374MODULE_DESCRIPTION("Altera GPIO driver");
375MODULE_LICENSE("GPL");