Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2008-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __ADRENO_H |
| 14 | #define __ADRENO_H |
| 15 | |
| 16 | #include "kgsl_device.h" |
| 17 | #include "kgsl_sharedmem.h" |
| 18 | #include "adreno_drawctxt.h" |
| 19 | #include "adreno_ringbuffer.h" |
| 20 | #include "adreno_profile.h" |
| 21 | #include "adreno_dispatch.h" |
| 22 | #include "kgsl_iommu.h" |
| 23 | #include "adreno_perfcounter.h" |
| 24 | #include <linux/stat.h> |
| 25 | #include <linux/delay.h> |
Carter Cooper | 05f2a6b | 2017-03-20 11:43:11 -0600 | [diff] [blame] | 26 | #include "kgsl_gmu.h" |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 27 | |
| 28 | #include "a4xx_reg.h" |
| 29 | |
| 30 | #ifdef CONFIG_QCOM_OCMEM |
| 31 | #include <soc/qcom/ocmem.h> |
| 32 | #endif |
| 33 | |
| 34 | #define DEVICE_3D_NAME "kgsl-3d" |
| 35 | #define DEVICE_3D0_NAME "kgsl-3d0" |
| 36 | |
| 37 | /* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */ |
| 38 | #define ADRENO_DEVICE(device) \ |
| 39 | container_of(device, struct adreno_device, dev) |
| 40 | |
| 41 | /* KGSL_DEVICE - given an adreno_device, return the KGSL device struct */ |
| 42 | #define KGSL_DEVICE(_dev) (&((_dev)->dev)) |
| 43 | |
| 44 | /* ADRENO_CONTEXT - Given a context return the adreno context struct */ |
| 45 | #define ADRENO_CONTEXT(context) \ |
| 46 | container_of(context, struct adreno_context, base) |
| 47 | |
| 48 | /* ADRENO_GPU_DEVICE - Given an adreno device return the GPU specific struct */ |
| 49 | #define ADRENO_GPU_DEVICE(_a) ((_a)->gpucore->gpudev) |
| 50 | |
| 51 | #define ADRENO_CHIPID_CORE(_id) (((_id) >> 24) & 0xFF) |
| 52 | #define ADRENO_CHIPID_MAJOR(_id) (((_id) >> 16) & 0xFF) |
| 53 | #define ADRENO_CHIPID_MINOR(_id) (((_id) >> 8) & 0xFF) |
| 54 | #define ADRENO_CHIPID_PATCH(_id) ((_id) & 0xFF) |
| 55 | |
| 56 | /* ADRENO_GPUREV - Return the GPU ID for the given adreno_device */ |
| 57 | #define ADRENO_GPUREV(_a) ((_a)->gpucore->gpurev) |
| 58 | |
| 59 | /* |
| 60 | * ADRENO_FEATURE - return true if the specified feature is supported by the GPU |
| 61 | * core |
| 62 | */ |
| 63 | #define ADRENO_FEATURE(_dev, _bit) \ |
| 64 | ((_dev)->gpucore->features & (_bit)) |
| 65 | |
| 66 | /** |
| 67 | * ADRENO_QUIRK - return true if the specified quirk is required by the GPU |
| 68 | */ |
| 69 | #define ADRENO_QUIRK(_dev, _bit) \ |
| 70 | ((_dev)->quirks & (_bit)) |
| 71 | |
| 72 | /* |
| 73 | * ADRENO_PREEMPT_STYLE - return preemption style |
| 74 | */ |
| 75 | #define ADRENO_PREEMPT_STYLE(flags) \ |
| 76 | ((flags & KGSL_CONTEXT_PREEMPT_STYLE_MASK) >> \ |
| 77 | KGSL_CONTEXT_PREEMPT_STYLE_SHIFT) |
| 78 | |
| 79 | /* |
| 80 | * return the dispatcher drawqueue in which the given drawobj should |
| 81 | * be submitted |
| 82 | */ |
| 83 | #define ADRENO_DRAWOBJ_DISPATCH_DRAWQUEUE(c) \ |
| 84 | (&((ADRENO_CONTEXT(c->context))->rb->dispatch_q)) |
| 85 | |
| 86 | #define ADRENO_DRAWOBJ_RB(c) \ |
| 87 | ((ADRENO_CONTEXT(c->context))->rb) |
| 88 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 89 | #define ADRENO_FW(a, f) (&(a->fw[f])) |
| 90 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 91 | /* Adreno core features */ |
| 92 | /* The core uses OCMEM for GMEM/binning memory */ |
| 93 | #define ADRENO_USES_OCMEM BIT(0) |
| 94 | /* The core supports an accelerated warm start */ |
| 95 | #define ADRENO_WARM_START BIT(1) |
| 96 | /* The core supports the microcode bootstrap functionality */ |
| 97 | #define ADRENO_USE_BOOTSTRAP BIT(2) |
| 98 | /* The core supports SP/TP hw controlled power collapse */ |
| 99 | #define ADRENO_SPTP_PC BIT(3) |
| 100 | /* The core supports Peak Power Detection(PPD)*/ |
| 101 | #define ADRENO_PPD BIT(4) |
| 102 | /* The GPU supports content protection */ |
| 103 | #define ADRENO_CONTENT_PROTECTION BIT(5) |
| 104 | /* The GPU supports preemption */ |
| 105 | #define ADRENO_PREEMPTION BIT(6) |
| 106 | /* The core uses GPMU for power and limit management */ |
| 107 | #define ADRENO_GPMU BIT(7) |
| 108 | /* The GPMU supports Limits Management */ |
| 109 | #define ADRENO_LM BIT(8) |
| 110 | /* The core uses 64 bit GPU addresses */ |
| 111 | #define ADRENO_64BIT BIT(9) |
| 112 | /* The GPU supports retention for cpz registers */ |
| 113 | #define ADRENO_CPZ_RETENTION BIT(10) |
Shrenuj Bansal | ae67281 | 2016-02-24 14:17:30 -0800 | [diff] [blame] | 114 | /* The core has soft fault detection available */ |
| 115 | #define ADRENO_SOFT_FAULT_DETECT BIT(11) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 116 | /* The GMU supports RPMh for power management*/ |
| 117 | #define ADRENO_RPMH BIT(12) |
| 118 | /* The GMU supports IFPC power management*/ |
| 119 | #define ADRENO_IFPC BIT(13) |
| 120 | /* The GMU supports HW based NAP */ |
| 121 | #define ADRENO_HW_NAP BIT(14) |
| 122 | /* The GMU supports min voltage*/ |
| 123 | #define ADRENO_MIN_VOLT BIT(15) |
Shrenuj Bansal | 4fd6a56 | 2017-08-07 15:12:54 -0700 | [diff] [blame] | 124 | /* The core supports IO-coherent memory */ |
| 125 | #define ADRENO_IOCOHERENT BIT(16) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 126 | |
| 127 | /* |
| 128 | * Adreno GPU quirks - control bits for various workarounds |
| 129 | */ |
| 130 | |
Lynus Vaz | 85c8cee | 2017-03-07 11:31:02 +0530 | [diff] [blame] | 131 | /* Set TWOPASSUSEWFI in PC_DBG_ECO_CNTL (5XX/6XX) */ |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 132 | #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) |
| 133 | /* Lock/unlock mutex to sync with the IOMMU */ |
| 134 | #define ADRENO_QUIRK_IOMMU_SYNC BIT(1) |
| 135 | /* Submit critical packets at GPU wake up */ |
| 136 | #define ADRENO_QUIRK_CRITICAL_PACKETS BIT(2) |
| 137 | /* Mask out RB1-3 activity signals from HW hang detection logic */ |
| 138 | #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(3) |
| 139 | /* Disable RB sampler datapath clock gating optimization */ |
| 140 | #define ADRENO_QUIRK_DISABLE_RB_DP2CLOCKGATING BIT(4) |
| 141 | /* Disable local memory(LM) feature to avoid corner case error */ |
| 142 | #define ADRENO_QUIRK_DISABLE_LMLOADKILL BIT(5) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 143 | /* Allow HFI to use registers to send message to GMU */ |
| 144 | #define ADRENO_QUIRK_HFI_USE_REG BIT(6) |
Carter Cooper | 6682ead | 2017-09-28 14:52:53 -0600 | [diff] [blame] | 145 | /* Only set protected SECVID registers once */ |
| 146 | #define ADRENO_QUIRK_SECVID_SET_ONCE BIT(7) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 147 | |
| 148 | /* Flags to control command packet settings */ |
| 149 | #define KGSL_CMD_FLAGS_NONE 0 |
| 150 | #define KGSL_CMD_FLAGS_PMODE BIT(0) |
| 151 | #define KGSL_CMD_FLAGS_INTERNAL_ISSUE BIT(1) |
| 152 | #define KGSL_CMD_FLAGS_WFI BIT(2) |
| 153 | #define KGSL_CMD_FLAGS_PROFILE BIT(3) |
| 154 | #define KGSL_CMD_FLAGS_PWRON_FIXUP BIT(4) |
| 155 | |
| 156 | /* Command identifiers */ |
| 157 | #define KGSL_CONTEXT_TO_MEM_IDENTIFIER 0x2EADBEEF |
| 158 | #define KGSL_CMD_IDENTIFIER 0x2EEDFACE |
| 159 | #define KGSL_CMD_INTERNAL_IDENTIFIER 0x2EEDD00D |
| 160 | #define KGSL_START_OF_IB_IDENTIFIER 0x2EADEABE |
| 161 | #define KGSL_END_OF_IB_IDENTIFIER 0x2ABEDEAD |
| 162 | #define KGSL_START_OF_PROFILE_IDENTIFIER 0x2DEFADE1 |
| 163 | #define KGSL_END_OF_PROFILE_IDENTIFIER 0x2DEFADE2 |
| 164 | #define KGSL_PWRON_FIXUP_IDENTIFIER 0x2AFAFAFA |
| 165 | |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 166 | /* Number of times to try hard reset */ |
| 167 | #define NUM_TIMES_RESET_RETRY 5 |
| 168 | |
Kyle Piefer | 5e1b78bd | 2017-10-19 13:22:10 -0700 | [diff] [blame] | 169 | /* Number of times to poll the AHB fence in ISR */ |
| 170 | #define FENCE_RETRY_MAX 100 |
| 171 | |
Harshdeep Dhatt | e804696 | 2017-11-10 15:45:24 -0700 | [diff] [blame] | 172 | /* Number of times to see if INT_0_STATUS changed or not */ |
| 173 | #define STATUS_RETRY_MAX 3 |
| 174 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 175 | /* One cannot wait forever for the core to idle, so set an upper limit to the |
| 176 | * amount of time to wait for the core to go idle |
| 177 | */ |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 178 | #define ADRENO_IDLE_TIMEOUT (20 * 1000) |
| 179 | |
| 180 | #define ADRENO_UCHE_GMEM_BASE 0x100000 |
| 181 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 182 | #define ADRENO_FW_PFP 0 |
| 183 | #define ADRENO_FW_SQE 0 |
| 184 | #define ADRENO_FW_PM4 1 |
| 185 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 186 | enum adreno_gpurev { |
| 187 | ADRENO_REV_UNKNOWN = 0, |
| 188 | ADRENO_REV_A304 = 304, |
| 189 | ADRENO_REV_A305 = 305, |
| 190 | ADRENO_REV_A305C = 306, |
| 191 | ADRENO_REV_A306 = 307, |
| 192 | ADRENO_REV_A306A = 308, |
| 193 | ADRENO_REV_A310 = 310, |
| 194 | ADRENO_REV_A320 = 320, |
| 195 | ADRENO_REV_A330 = 330, |
| 196 | ADRENO_REV_A305B = 335, |
| 197 | ADRENO_REV_A405 = 405, |
| 198 | ADRENO_REV_A418 = 418, |
| 199 | ADRENO_REV_A420 = 420, |
| 200 | ADRENO_REV_A430 = 430, |
| 201 | ADRENO_REV_A505 = 505, |
| 202 | ADRENO_REV_A506 = 506, |
Rajesh Kemisetti | aed6ec7 | 2017-02-06 09:37:00 +0530 | [diff] [blame] | 203 | ADRENO_REV_A508 = 508, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 204 | ADRENO_REV_A510 = 510, |
| 205 | ADRENO_REV_A512 = 512, |
| 206 | ADRENO_REV_A530 = 530, |
| 207 | ADRENO_REV_A540 = 540, |
Rajesh Kemisetti | 8d5cc6e | 2017-06-06 16:44:17 +0530 | [diff] [blame] | 208 | ADRENO_REV_A615 = 615, |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 209 | ADRENO_REV_A630 = 630, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 210 | }; |
| 211 | |
| 212 | #define ADRENO_START_WARM 0 |
| 213 | #define ADRENO_START_COLD 1 |
| 214 | |
| 215 | #define ADRENO_SOFT_FAULT BIT(0) |
| 216 | #define ADRENO_HARD_FAULT BIT(1) |
| 217 | #define ADRENO_TIMEOUT_FAULT BIT(2) |
| 218 | #define ADRENO_IOMMU_PAGE_FAULT BIT(3) |
| 219 | #define ADRENO_PREEMPT_FAULT BIT(4) |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 220 | #define ADRENO_GMU_FAULT BIT(5) |
Hareesh Gundu | 28b9efd | 2017-08-24 23:11:09 +0530 | [diff] [blame] | 221 | #define ADRENO_CTX_DETATCH_TIMEOUT_FAULT BIT(6) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 222 | |
| 223 | #define ADRENO_SPTP_PC_CTRL 0 |
| 224 | #define ADRENO_PPD_CTRL 1 |
| 225 | #define ADRENO_LM_CTRL 2 |
| 226 | #define ADRENO_HWCG_CTRL 3 |
| 227 | #define ADRENO_THROTTLING_CTRL 4 |
| 228 | |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 229 | /* VBIF, GBIF halt request and ack mask */ |
| 230 | #define GBIF_HALT_REQUEST 0x1E0 |
| 231 | #define VBIF_RESET_ACK_MASK 0x00f0 |
| 232 | #define VBIF_RESET_ACK_TIMEOUT 100 |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 233 | |
| 234 | /* number of throttle counters for DCVS adjustment */ |
| 235 | #define ADRENO_GPMU_THROTTLE_COUNTERS 4 |
| 236 | /* base for throttle counters */ |
| 237 | #define ADRENO_GPMU_THROTTLE_COUNTERS_BASE_REG 43 |
| 238 | |
| 239 | struct adreno_gpudev; |
| 240 | |
| 241 | /* Time to allow preemption to complete (in ms) */ |
| 242 | #define ADRENO_PREEMPT_TIMEOUT 10000 |
| 243 | |
| 244 | #define ADRENO_INT_BIT(a, _bit) (((a)->gpucore->gpudev->int_bits) ? \ |
| 245 | (adreno_get_int(a, _bit) < 0 ? 0 : \ |
| 246 | BIT(adreno_get_int(a, _bit))) : 0) |
| 247 | |
| 248 | /** |
| 249 | * enum adreno_preempt_states |
| 250 | * ADRENO_PREEMPT_NONE: No preemption is scheduled |
| 251 | * ADRENO_PREEMPT_START: The S/W has started |
| 252 | * ADRENO_PREEMPT_TRIGGERED: A preeempt has been triggered in the HW |
| 253 | * ADRENO_PREEMPT_FAULTED: The preempt timer has fired |
| 254 | * ADRENO_PREEMPT_PENDING: The H/W has signaled preemption complete |
| 255 | * ADRENO_PREEMPT_COMPLETE: Preemption could not be finished in the IRQ handler, |
| 256 | * worker has been scheduled |
| 257 | */ |
| 258 | enum adreno_preempt_states { |
| 259 | ADRENO_PREEMPT_NONE = 0, |
| 260 | ADRENO_PREEMPT_START, |
| 261 | ADRENO_PREEMPT_TRIGGERED, |
| 262 | ADRENO_PREEMPT_FAULTED, |
| 263 | ADRENO_PREEMPT_PENDING, |
| 264 | ADRENO_PREEMPT_COMPLETE, |
| 265 | }; |
| 266 | |
| 267 | /** |
| 268 | * struct adreno_preemption |
| 269 | * @state: The current state of preemption |
| 270 | * @counters: Memory descriptor for the memory where the GPU writes the |
| 271 | * preemption counters on switch |
| 272 | * @timer: A timer to make sure preemption doesn't stall |
| 273 | * @work: A work struct for the preemption worker (for 5XX) |
| 274 | * @token_submit: Indicates if a preempt token has been submitted in |
| 275 | * current ringbuffer (for 4XX) |
Harshdeep Dhatt | a8ec51c | 2017-09-21 17:24:08 -0600 | [diff] [blame] | 276 | * preempt_level: The level of preemption (for 6XX) |
| 277 | * skipsaverestore: To skip saverestore during L1 preemption (for 6XX) |
| 278 | * usesgmem: enable GMEM save/restore across preemption (for 6XX) |
Harshdeep Dhatt | 4ab35b1 | 2017-11-16 08:34:39 -0700 | [diff] [blame] | 279 | * count: Track the number of preemptions triggered |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 280 | */ |
| 281 | struct adreno_preemption { |
| 282 | atomic_t state; |
| 283 | struct kgsl_memdesc counters; |
| 284 | struct timer_list timer; |
| 285 | struct work_struct work; |
| 286 | bool token_submit; |
Harshdeep Dhatt | a8ec51c | 2017-09-21 17:24:08 -0600 | [diff] [blame] | 287 | unsigned int preempt_level; |
| 288 | bool skipsaverestore; |
| 289 | bool usesgmem; |
Harshdeep Dhatt | 4ab35b1 | 2017-11-16 08:34:39 -0700 | [diff] [blame] | 290 | unsigned int count; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 291 | }; |
| 292 | |
| 293 | |
| 294 | struct adreno_busy_data { |
| 295 | unsigned int gpu_busy; |
Deepak Kumar | 84b9e03 | 2017-11-08 13:08:50 +0530 | [diff] [blame] | 296 | unsigned int bif_ram_cycles; |
| 297 | unsigned int bif_ram_cycles_read_ch1; |
| 298 | unsigned int bif_ram_cycles_write_ch0; |
| 299 | unsigned int bif_ram_cycles_write_ch1; |
| 300 | unsigned int bif_starved_ram; |
| 301 | unsigned int bif_starved_ram_ch1; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 302 | unsigned int throttle_cycles[ADRENO_GPMU_THROTTLE_COUNTERS]; |
| 303 | }; |
| 304 | |
| 305 | /** |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 306 | * struct adreno_firmware - Struct holding fw details |
| 307 | * @fwvirt: Buffer which holds the ucode |
| 308 | * @size: Size of ucode buffer |
| 309 | * @version: Version of ucode |
| 310 | * @memdesc: Memory descriptor which holds ucode buffer info |
| 311 | */ |
| 312 | struct adreno_firmware { |
| 313 | unsigned int *fwvirt; |
| 314 | size_t size; |
| 315 | unsigned int version; |
| 316 | struct kgsl_memdesc memdesc; |
| 317 | }; |
| 318 | |
| 319 | /** |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 320 | * struct adreno_gpu_core - A specific GPU core definition |
| 321 | * @gpurev: Unique GPU revision identifier |
| 322 | * @core: Match for the core version of the GPU |
| 323 | * @major: Match for the major version of the GPU |
| 324 | * @minor: Match for the minor version of the GPU |
| 325 | * @patchid: Match for the patch revision of the GPU |
| 326 | * @features: Common adreno features supported by this core |
| 327 | * @pm4fw_name: Filename for th PM4 firmware |
| 328 | * @pfpfw_name: Filename for the PFP firmware |
| 329 | * @zap_name: Filename for the Zap Shader ucode |
| 330 | * @gpudev: Pointer to the GPU family specific functions for this core |
| 331 | * @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core |
| 332 | * @pm4_jt_idx: Index of the jump table in the PM4 microcode |
| 333 | * @pm4_jt_addr: Address offset to load the jump table for the PM4 microcode |
| 334 | * @pfp_jt_idx: Index of the jump table in the PFP microcode |
| 335 | * @pfp_jt_addr: Address offset to load the jump table for the PFP microcode |
| 336 | * @pm4_bstrp_size: Size of the bootstrap loader for PM4 microcode |
| 337 | * @pfp_bstrp_size: Size of the bootstrap loader for PFP microcde |
| 338 | * @pfp_bstrp_ver: Version of the PFP microcode that supports bootstraping |
| 339 | * @shader_offset: Offset of shader from gpu reg base |
| 340 | * @shader_size: Shader size |
| 341 | * @num_protected_regs: number of protected registers |
| 342 | * @gpmufw_name: Filename for the GPMU firmware |
| 343 | * @gpmu_major: Match for the GPMU & firmware, major revision |
| 344 | * @gpmu_minor: Match for the GPMU & firmware, minor revision |
| 345 | * @gpmu_features: Supported features for any given GPMU version |
| 346 | * @busy_mask: mask to check if GPU is busy in RBBM_STATUS |
| 347 | * @lm_major: Limits Management register sequence, major revision |
| 348 | * @lm_minor: LM register sequence, minor revision |
| 349 | * @regfw_name: Filename for the register sequence firmware |
| 350 | * @gpmu_tsens: ID for the temporature sensor used by the GPMU |
| 351 | * @max_power: Max possible power draw of a core, units elephant tail hairs |
| 352 | */ |
| 353 | struct adreno_gpu_core { |
| 354 | enum adreno_gpurev gpurev; |
| 355 | unsigned int core, major, minor, patchid; |
| 356 | unsigned long features; |
| 357 | const char *pm4fw_name; |
| 358 | const char *pfpfw_name; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 359 | const char *sqefw_name; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 360 | const char *zap_name; |
| 361 | struct adreno_gpudev *gpudev; |
| 362 | size_t gmem_size; |
| 363 | unsigned int pm4_jt_idx; |
| 364 | unsigned int pm4_jt_addr; |
| 365 | unsigned int pfp_jt_idx; |
| 366 | unsigned int pfp_jt_addr; |
| 367 | unsigned int pm4_bstrp_size; |
| 368 | unsigned int pfp_bstrp_size; |
| 369 | unsigned int pfp_bstrp_ver; |
| 370 | unsigned long shader_offset; |
| 371 | unsigned int shader_size; |
| 372 | unsigned int num_protected_regs; |
| 373 | const char *gpmufw_name; |
| 374 | unsigned int gpmu_major; |
| 375 | unsigned int gpmu_minor; |
| 376 | unsigned int gpmu_features; |
| 377 | unsigned int busy_mask; |
| 378 | unsigned int lm_major, lm_minor; |
| 379 | const char *regfw_name; |
| 380 | unsigned int gpmu_tsens; |
| 381 | unsigned int max_power; |
| 382 | }; |
| 383 | |
Lokesh Batra | a8300e0 | 2017-05-25 11:17:40 -0700 | [diff] [blame] | 384 | |
| 385 | enum gpu_coresight_sources { |
| 386 | GPU_CORESIGHT_GX = 0, |
| 387 | GPU_CORESIGHT_CX = 1, |
| 388 | GPU_CORESIGHT_MAX, |
| 389 | }; |
| 390 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 391 | /** |
| 392 | * struct adreno_device - The mothership structure for all adreno related info |
| 393 | * @dev: Reference to struct kgsl_device |
| 394 | * @priv: Holds the private flags specific to the adreno_device |
| 395 | * @chipid: Chip ID specific to the GPU |
| 396 | * @gmem_base: Base physical address of GMEM |
| 397 | * @gmem_size: GMEM size |
| 398 | * @gpucore: Pointer to the adreno_gpu_core structure |
| 399 | * @pfp_fw: Buffer which holds the pfp ucode |
| 400 | * @pfp_fw_size: Size of pfp ucode buffer |
| 401 | * @pfp_fw_version: Version of pfp ucode |
| 402 | * @pfp: Memory descriptor which holds pfp ucode buffer info |
| 403 | * @pm4_fw: Buffer which holds the pm4 ucode |
| 404 | * @pm4_fw_size: Size of pm4 ucode buffer |
| 405 | * @pm4_fw_version: Version of pm4 ucode |
| 406 | * @pm4: Memory descriptor which holds pm4 ucode buffer info |
| 407 | * @gpmu_cmds_size: Length of gpmu cmd stream |
| 408 | * @gpmu_cmds: gpmu cmd stream |
| 409 | * @ringbuffers: Array of pointers to adreno_ringbuffers |
| 410 | * @num_ringbuffers: Number of ringbuffers for the GPU |
| 411 | * @cur_rb: Pointer to the current ringbuffer |
| 412 | * @next_rb: Ringbuffer we are switching to during preemption |
| 413 | * @prev_rb: Ringbuffer we are switching from during preemption |
| 414 | * @fast_hang_detect: Software fault detection availability |
| 415 | * @ft_policy: Defines the fault tolerance policy |
| 416 | * @long_ib_detect: Long IB detection availability |
| 417 | * @ft_pf_policy: Defines the fault policy for page faults |
| 418 | * @ocmem_hdl: Handle to the ocmem allocated buffer |
| 419 | * @profile: Container for adreno profiler information |
| 420 | * @dispatcher: Container for adreno GPU dispatcher |
| 421 | * @pwron_fixup: Command buffer to run a post-power collapse shader workaround |
| 422 | * @pwron_fixup_dwords: Number of dwords in the command buffer |
| 423 | * @input_work: Work struct for turning on the GPU after a touch event |
| 424 | * @busy_data: Struct holding GPU VBIF busy stats |
Deepak Kumar | 84b9e03 | 2017-11-08 13:08:50 +0530 | [diff] [blame] | 425 | * @ram_cycles_lo: Number of DDR clock cycles for the monitor session (Only |
| 426 | * DDR channel 0 read cycles in case of GBIF) |
| 427 | * @ram_cycles_lo_ch1_read: Number of DDR channel 1 Read clock cycles for |
| 428 | * the monitor session |
| 429 | * @ram_cycles_lo_ch0_write: Number of DDR channel 0 Write clock cycles for |
| 430 | * the monitor session |
| 431 | * @ram_cycles_lo_ch1_write: Number of DDR channel 0 Write clock cycles for |
| 432 | * the monitor session |
Deepak Kumar | c52781f | 2017-11-06 16:10:17 +0530 | [diff] [blame] | 433 | * @starved_ram_lo: Number of cycles VBIF/GBIF is stalled by DDR (Only channel 0 |
| 434 | * stall cycles in case of GBIF) |
| 435 | * @starved_ram_lo_ch1: Number of cycles GBIF is stalled by DDR channel 1 |
| 436 | * @perfctr_pwr_lo: GPU busy cycles |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 437 | * @halt: Atomic variable to check whether the GPU is currently halted |
Deepak Kumar | 273c571 | 2017-01-03 21:49:03 +0530 | [diff] [blame] | 438 | * @pending_irq_refcnt: Atomic variable to keep track of running IRQ handlers |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 439 | * @ctx_d_debugfs: Context debugfs node |
| 440 | * @pwrctrl_flag: Flag to hold adreno specific power attributes |
| 441 | * @profile_buffer: Memdesc holding the drawobj profiling buffer |
| 442 | * @profile_index: Index to store the start/stop ticks in the profiling |
| 443 | * buffer |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 444 | * @pwrup_reglist: Memdesc holding the power up register list |
| 445 | * which is used by CP during preemption and IFPC |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 446 | * @sp_local_gpuaddr: Base GPU virtual address for SP local memory |
| 447 | * @sp_pvt_gpuaddr: Base GPU virtual address for SP private memory |
| 448 | * @lm_fw: The LM firmware handle |
| 449 | * @lm_sequence: Pointer to the start of the register write sequence for LM |
| 450 | * @lm_size: The dword size of the LM sequence |
| 451 | * @lm_limit: limiting value for LM |
| 452 | * @lm_threshold_count: register value for counter for lm threshold breakin |
| 453 | * @lm_threshold_cross: number of current peaks exceeding threshold |
| 454 | * @speed_bin: Indicate which power level set to use |
| 455 | * @csdev: Pointer to a coresight device (if applicable) |
| 456 | * @gpmu_throttle_counters - counteers for number of throttled clocks |
| 457 | * @irq_storm_work: Worker to handle possible interrupt storms |
| 458 | * @active_list: List to track active contexts |
| 459 | * @active_list_lock: Lock to protect active_list |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 460 | * @gpu_llc_slice: GPU system cache slice descriptor |
Sushmita Susheelendra | b197668 | 2016-11-07 14:21:11 -0700 | [diff] [blame] | 461 | * @gpu_llc_slice_enable: To enable the GPU system cache slice or not |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 462 | * @gpuhtw_llc_slice: GPU pagetables system cache slice descriptor |
Sushmita Susheelendra | d3756c0 | 2017-01-11 15:05:40 -0700 | [diff] [blame] | 463 | * @gpuhtw_llc_slice_enable: To enable the GPUHTW system cache slice or not |
Harshdeep Dhatt | a9e0d76 | 2017-05-10 14:16:42 -0600 | [diff] [blame] | 464 | * @zap_loaded: Used to track if zap was successfully loaded or not |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 465 | */ |
| 466 | struct adreno_device { |
| 467 | struct kgsl_device dev; /* Must be first field in this struct */ |
| 468 | unsigned long priv; |
| 469 | unsigned int chipid; |
| 470 | unsigned long gmem_base; |
| 471 | unsigned long gmem_size; |
Lynus Vaz | 9ed8cf9 | 2017-09-21 21:55:34 +0530 | [diff] [blame] | 472 | unsigned long cx_dbgc_base; |
| 473 | unsigned int cx_dbgc_len; |
| 474 | void __iomem *cx_dbgc_virt; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 475 | const struct adreno_gpu_core *gpucore; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 476 | struct adreno_firmware fw[2]; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 477 | size_t gpmu_cmds_size; |
| 478 | unsigned int *gpmu_cmds; |
| 479 | struct adreno_ringbuffer ringbuffers[KGSL_PRIORITY_MAX_RB_LEVELS]; |
| 480 | int num_ringbuffers; |
| 481 | struct adreno_ringbuffer *cur_rb; |
| 482 | struct adreno_ringbuffer *next_rb; |
| 483 | struct adreno_ringbuffer *prev_rb; |
| 484 | unsigned int fast_hang_detect; |
| 485 | unsigned long ft_policy; |
| 486 | unsigned int long_ib_detect; |
| 487 | unsigned long ft_pf_policy; |
| 488 | struct ocmem_buf *ocmem_hdl; |
| 489 | struct adreno_profile profile; |
| 490 | struct adreno_dispatcher dispatcher; |
| 491 | struct kgsl_memdesc pwron_fixup; |
| 492 | unsigned int pwron_fixup_dwords; |
| 493 | struct work_struct input_work; |
| 494 | struct adreno_busy_data busy_data; |
| 495 | unsigned int ram_cycles_lo; |
Deepak Kumar | 84b9e03 | 2017-11-08 13:08:50 +0530 | [diff] [blame] | 496 | unsigned int ram_cycles_lo_ch1_read; |
| 497 | unsigned int ram_cycles_lo_ch0_write; |
| 498 | unsigned int ram_cycles_lo_ch1_write; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 499 | unsigned int starved_ram_lo; |
Deepak Kumar | c52781f | 2017-11-06 16:10:17 +0530 | [diff] [blame] | 500 | unsigned int starved_ram_lo_ch1; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 501 | unsigned int perfctr_pwr_lo; |
| 502 | atomic_t halt; |
Deepak Kumar | 273c571 | 2017-01-03 21:49:03 +0530 | [diff] [blame] | 503 | atomic_t pending_irq_refcnt; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 504 | struct dentry *ctx_d_debugfs; |
| 505 | unsigned long pwrctrl_flag; |
| 506 | |
| 507 | struct kgsl_memdesc profile_buffer; |
| 508 | unsigned int profile_index; |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 509 | struct kgsl_memdesc pwrup_reglist; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 510 | uint64_t sp_local_gpuaddr; |
| 511 | uint64_t sp_pvt_gpuaddr; |
| 512 | const struct firmware *lm_fw; |
| 513 | uint32_t *lm_sequence; |
| 514 | uint32_t lm_size; |
| 515 | struct adreno_preemption preempt; |
| 516 | struct work_struct gpmu_work; |
| 517 | uint32_t lm_leakage; |
| 518 | uint32_t lm_limit; |
| 519 | uint32_t lm_threshold_count; |
| 520 | uint32_t lm_threshold_cross; |
| 521 | |
| 522 | unsigned int speed_bin; |
| 523 | unsigned int quirks; |
| 524 | |
Lokesh Batra | a8300e0 | 2017-05-25 11:17:40 -0700 | [diff] [blame] | 525 | struct coresight_device *csdev[GPU_CORESIGHT_MAX]; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 526 | uint32_t gpmu_throttle_counters[ADRENO_GPMU_THROTTLE_COUNTERS]; |
| 527 | struct work_struct irq_storm_work; |
| 528 | |
| 529 | struct list_head active_list; |
| 530 | spinlock_t active_list_lock; |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 531 | |
| 532 | void *gpu_llc_slice; |
Sushmita Susheelendra | b197668 | 2016-11-07 14:21:11 -0700 | [diff] [blame] | 533 | bool gpu_llc_slice_enable; |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 534 | void *gpuhtw_llc_slice; |
Sushmita Susheelendra | d3756c0 | 2017-01-11 15:05:40 -0700 | [diff] [blame] | 535 | bool gpuhtw_llc_slice_enable; |
Harshdeep Dhatt | a9e0d76 | 2017-05-10 14:16:42 -0600 | [diff] [blame] | 536 | unsigned int zap_loaded; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 537 | }; |
| 538 | |
| 539 | /** |
| 540 | * enum adreno_device_flags - Private flags for the adreno_device |
| 541 | * @ADRENO_DEVICE_PWRON - Set during init after a power collapse |
| 542 | * @ADRENO_DEVICE_PWRON_FIXUP - Set if the target requires the shader fixup |
| 543 | * after power collapse |
| 544 | * @ADRENO_DEVICE_CORESIGHT - Set if the coresight (trace bus) registers should |
| 545 | * be restored after power collapse |
| 546 | * @ADRENO_DEVICE_HANG_INTR - Set if the hang interrupt should be enabled for |
| 547 | * this target |
| 548 | * @ADRENO_DEVICE_STARTED - Set if the device start sequence is in progress |
| 549 | * @ADRENO_DEVICE_FAULT - Set if the device is currently in fault (and shouldn't |
| 550 | * send any more commands to the ringbuffer) |
| 551 | * @ADRENO_DEVICE_DRAWOBJ_PROFILE - Set if the device supports drawobj |
| 552 | * profiling via the ALWAYSON counter |
| 553 | * @ADRENO_DEVICE_PREEMPTION - Turn on/off preemption |
| 554 | * @ADRENO_DEVICE_SOFT_FAULT_DETECT - Set if soft fault detect is enabled |
| 555 | * @ADRENO_DEVICE_GPMU_INITIALIZED - Set if GPMU firmware initialization succeed |
| 556 | * @ADRENO_DEVICE_ISDB_ENABLED - Set if the Integrated Shader DeBugger is |
| 557 | * attached and enabled |
| 558 | * @ADRENO_DEVICE_CACHE_FLUSH_TS_SUSPENDED - Set if a CACHE_FLUSH_TS irq storm |
| 559 | * is in progress |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 560 | * @ADRENO_DEVICE_HARD_RESET - Set if soft reset fails and hard reset is needed |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 561 | */ |
| 562 | enum adreno_device_flags { |
| 563 | ADRENO_DEVICE_PWRON = 0, |
| 564 | ADRENO_DEVICE_PWRON_FIXUP = 1, |
| 565 | ADRENO_DEVICE_INITIALIZED = 2, |
| 566 | ADRENO_DEVICE_CORESIGHT = 3, |
| 567 | ADRENO_DEVICE_HANG_INTR = 4, |
| 568 | ADRENO_DEVICE_STARTED = 5, |
| 569 | ADRENO_DEVICE_FAULT = 6, |
| 570 | ADRENO_DEVICE_DRAWOBJ_PROFILE = 7, |
| 571 | ADRENO_DEVICE_GPU_REGULATOR_ENABLED = 8, |
| 572 | ADRENO_DEVICE_PREEMPTION = 9, |
| 573 | ADRENO_DEVICE_SOFT_FAULT_DETECT = 10, |
| 574 | ADRENO_DEVICE_GPMU_INITIALIZED = 11, |
| 575 | ADRENO_DEVICE_ISDB_ENABLED = 12, |
| 576 | ADRENO_DEVICE_CACHE_FLUSH_TS_SUSPENDED = 13, |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 577 | ADRENO_DEVICE_HARD_RESET = 14, |
Harshdeep Dhatt | 38e57d7 | 2017-08-30 13:24:07 -0600 | [diff] [blame] | 578 | ADRENO_DEVICE_PREEMPTION_EXECUTION = 15, |
Lokesh Batra | a8300e0 | 2017-05-25 11:17:40 -0700 | [diff] [blame] | 579 | ADRENO_DEVICE_CORESIGHT_CX = 16, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 580 | }; |
| 581 | |
| 582 | /** |
| 583 | * struct adreno_drawobj_profile_entry - a single drawobj entry in the |
| 584 | * kernel profiling buffer |
| 585 | * @started: Number of GPU ticks at start of the drawobj |
| 586 | * @retired: Number of GPU ticks at the end of the drawobj |
| 587 | */ |
| 588 | struct adreno_drawobj_profile_entry { |
| 589 | uint64_t started; |
| 590 | uint64_t retired; |
| 591 | }; |
| 592 | |
| 593 | #define ADRENO_DRAWOBJ_PROFILE_COUNT \ |
| 594 | (PAGE_SIZE / sizeof(struct adreno_drawobj_profile_entry)) |
| 595 | |
| 596 | #define ADRENO_DRAWOBJ_PROFILE_OFFSET(_index, _member) \ |
| 597 | ((_index) * sizeof(struct adreno_drawobj_profile_entry) \ |
| 598 | + offsetof(struct adreno_drawobj_profile_entry, _member)) |
| 599 | |
| 600 | |
| 601 | /** |
| 602 | * adreno_regs: List of registers that are used in kgsl driver for all |
| 603 | * 3D devices. Each device type has different offset value for the same |
| 604 | * register, so an array of register offsets are declared for every device |
| 605 | * and are indexed by the enumeration values defined in this enum |
| 606 | */ |
| 607 | enum adreno_regs { |
| 608 | ADRENO_REG_CP_ME_RAM_WADDR, |
| 609 | ADRENO_REG_CP_ME_RAM_DATA, |
| 610 | ADRENO_REG_CP_PFP_UCODE_DATA, |
| 611 | ADRENO_REG_CP_PFP_UCODE_ADDR, |
| 612 | ADRENO_REG_CP_WFI_PEND_CTR, |
| 613 | ADRENO_REG_CP_RB_BASE, |
| 614 | ADRENO_REG_CP_RB_BASE_HI, |
| 615 | ADRENO_REG_CP_RB_RPTR_ADDR_LO, |
| 616 | ADRENO_REG_CP_RB_RPTR_ADDR_HI, |
| 617 | ADRENO_REG_CP_RB_RPTR, |
| 618 | ADRENO_REG_CP_RB_WPTR, |
| 619 | ADRENO_REG_CP_CNTL, |
| 620 | ADRENO_REG_CP_ME_CNTL, |
| 621 | ADRENO_REG_CP_RB_CNTL, |
| 622 | ADRENO_REG_CP_IB1_BASE, |
| 623 | ADRENO_REG_CP_IB1_BASE_HI, |
| 624 | ADRENO_REG_CP_IB1_BUFSZ, |
| 625 | ADRENO_REG_CP_IB2_BASE, |
| 626 | ADRENO_REG_CP_IB2_BASE_HI, |
| 627 | ADRENO_REG_CP_IB2_BUFSZ, |
| 628 | ADRENO_REG_CP_TIMESTAMP, |
| 629 | ADRENO_REG_CP_SCRATCH_REG6, |
| 630 | ADRENO_REG_CP_SCRATCH_REG7, |
| 631 | ADRENO_REG_CP_ME_RAM_RADDR, |
| 632 | ADRENO_REG_CP_ROQ_ADDR, |
| 633 | ADRENO_REG_CP_ROQ_DATA, |
| 634 | ADRENO_REG_CP_MERCIU_ADDR, |
| 635 | ADRENO_REG_CP_MERCIU_DATA, |
| 636 | ADRENO_REG_CP_MERCIU_DATA2, |
| 637 | ADRENO_REG_CP_MEQ_ADDR, |
| 638 | ADRENO_REG_CP_MEQ_DATA, |
| 639 | ADRENO_REG_CP_HW_FAULT, |
| 640 | ADRENO_REG_CP_PROTECT_STATUS, |
| 641 | ADRENO_REG_CP_PREEMPT, |
| 642 | ADRENO_REG_CP_PREEMPT_DEBUG, |
| 643 | ADRENO_REG_CP_PREEMPT_DISABLE, |
| 644 | ADRENO_REG_CP_PROTECT_REG_0, |
| 645 | ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_LO, |
| 646 | ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI, |
Harshdeep Dhatt | 59a6957 | 2017-11-01 14:46:13 -0600 | [diff] [blame] | 647 | ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO, |
| 648 | ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI, |
| 649 | ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO, |
| 650 | ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI, |
| 651 | ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO, |
| 652 | ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 653 | ADRENO_REG_RBBM_STATUS, |
| 654 | ADRENO_REG_RBBM_STATUS3, |
| 655 | ADRENO_REG_RBBM_PERFCTR_CTL, |
| 656 | ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0, |
| 657 | ADRENO_REG_RBBM_PERFCTR_LOAD_CMD1, |
| 658 | ADRENO_REG_RBBM_PERFCTR_LOAD_CMD2, |
| 659 | ADRENO_REG_RBBM_PERFCTR_LOAD_CMD3, |
| 660 | ADRENO_REG_RBBM_PERFCTR_PWR_1_LO, |
| 661 | ADRENO_REG_RBBM_INT_0_MASK, |
| 662 | ADRENO_REG_RBBM_INT_0_STATUS, |
| 663 | ADRENO_REG_RBBM_PM_OVERRIDE2, |
| 664 | ADRENO_REG_RBBM_INT_CLEAR_CMD, |
| 665 | ADRENO_REG_RBBM_SW_RESET_CMD, |
| 666 | ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD, |
| 667 | ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD2, |
| 668 | ADRENO_REG_RBBM_CLOCK_CTL, |
| 669 | ADRENO_REG_VPC_DEBUG_RAM_SEL, |
| 670 | ADRENO_REG_VPC_DEBUG_RAM_READ, |
| 671 | ADRENO_REG_PA_SC_AA_CONFIG, |
| 672 | ADRENO_REG_SQ_GPR_MANAGEMENT, |
| 673 | ADRENO_REG_SQ_INST_STORE_MANAGEMENT, |
| 674 | ADRENO_REG_TP0_CHICKEN, |
| 675 | ADRENO_REG_RBBM_RBBM_CTL, |
| 676 | ADRENO_REG_UCHE_INVALIDATE0, |
| 677 | ADRENO_REG_UCHE_INVALIDATE1, |
Abhilash Kumar | f1af104 | 2017-07-14 13:13:44 +0530 | [diff] [blame] | 678 | ADRENO_REG_RBBM_PERFCTR_RBBM_0_LO, |
| 679 | ADRENO_REG_RBBM_PERFCTR_RBBM_0_HI, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 680 | ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_LO, |
| 681 | ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI, |
| 682 | ADRENO_REG_RBBM_SECVID_TRUST_CONTROL, |
| 683 | ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO, |
| 684 | ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI, |
| 685 | ADRENO_REG_RBBM_SECVID_TRUST_CONFIG, |
| 686 | ADRENO_REG_RBBM_SECVID_TSB_CONTROL, |
| 687 | ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE, |
| 688 | ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI, |
| 689 | ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE, |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 690 | ADRENO_REG_RBBM_GPR0_CNTL, |
| 691 | ADRENO_REG_RBBM_VBIF_GX_RESET_STATUS, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 692 | ADRENO_REG_VBIF_XIN_HALT_CTRL0, |
| 693 | ADRENO_REG_VBIF_XIN_HALT_CTRL1, |
| 694 | ADRENO_REG_VBIF_VERSION, |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 695 | ADRENO_REG_GBIF_HALT, |
| 696 | ADRENO_REG_GBIF_HALT_ACK, |
Kyle Piefer | da0fa54 | 2017-08-04 13:39:40 -0700 | [diff] [blame] | 697 | ADRENO_REG_GMU_AO_AHB_FENCE_CTRL, |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 698 | ADRENO_REG_GMU_AO_INTERRUPT_EN, |
Kyle Piefer | e7b06b4 | 2017-04-06 13:53:01 -0700 | [diff] [blame] | 699 | ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR, |
| 700 | ADRENO_REG_GMU_AO_HOST_INTERRUPT_STATUS, |
| 701 | ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK, |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 702 | ADRENO_REG_GMU_PWR_COL_KEEPALIVE, |
| 703 | ADRENO_REG_GMU_AHB_FENCE_STATUS, |
| 704 | ADRENO_REG_GMU_RPMH_POWER_STATE, |
| 705 | ADRENO_REG_GMU_HFI_CTRL_STATUS, |
| 706 | ADRENO_REG_GMU_HFI_VERSION_INFO, |
| 707 | ADRENO_REG_GMU_HFI_SFR_ADDR, |
| 708 | ADRENO_REG_GMU_GMU2HOST_INTR_CLR, |
| 709 | ADRENO_REG_GMU_GMU2HOST_INTR_INFO, |
Kyle Piefer | e7b06b4 | 2017-04-06 13:53:01 -0700 | [diff] [blame] | 710 | ADRENO_REG_GMU_GMU2HOST_INTR_MASK, |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 711 | ADRENO_REG_GMU_HOST2GMU_INTR_SET, |
| 712 | ADRENO_REG_GMU_HOST2GMU_INTR_CLR, |
| 713 | ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO, |
George Shen | 6927d8f | 2017-07-19 11:38:10 -0700 | [diff] [blame] | 714 | ADRENO_REG_GMU_NMI_CONTROL_STATUS, |
| 715 | ADRENO_REG_GMU_CM3_CFG, |
Lynus Vaz | 76ecd06 | 2017-06-01 20:00:53 +0530 | [diff] [blame] | 716 | ADRENO_REG_GPMU_POWER_COUNTER_ENABLE, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 717 | ADRENO_REG_REGISTER_MAX, |
| 718 | }; |
| 719 | |
| 720 | enum adreno_int_bits { |
| 721 | ADRENO_INT_RBBM_AHB_ERROR, |
| 722 | ADRENO_INT_BITS_MAX, |
| 723 | }; |
| 724 | |
| 725 | /** |
| 726 | * adreno_reg_offsets: Holds array of register offsets |
| 727 | * @offsets: Offset array of size defined by enum adreno_regs |
| 728 | * @offset_0: This is the index of the register in offset array whose value |
| 729 | * is 0. 0 is a valid register offset and during initialization of the |
| 730 | * offset array we need to know if an offset value is correctly defined to 0 |
| 731 | */ |
| 732 | struct adreno_reg_offsets { |
| 733 | unsigned int *const offsets; |
| 734 | enum adreno_regs offset_0; |
| 735 | }; |
| 736 | |
| 737 | #define ADRENO_REG_UNUSED 0xFFFFFFFF |
| 738 | #define ADRENO_REG_SKIP 0xFFFFFFFE |
| 739 | #define ADRENO_REG_DEFINE(_offset, _reg) [_offset] = _reg |
| 740 | #define ADRENO_INT_DEFINE(_offset, _val) ADRENO_REG_DEFINE(_offset, _val) |
| 741 | |
| 742 | /* |
| 743 | * struct adreno_vbif_data - Describes vbif register value pair |
| 744 | * @reg: Offset to vbif register |
| 745 | * @val: The value that should be programmed in the register at reg |
| 746 | */ |
| 747 | struct adreno_vbif_data { |
| 748 | unsigned int reg; |
| 749 | unsigned int val; |
| 750 | }; |
| 751 | |
| 752 | /* |
| 753 | * struct adreno_vbif_platform - Holds an array of vbif reg value pairs |
| 754 | * for a particular core |
| 755 | * @devfunc: Pointer to platform/core identification function |
| 756 | * @vbif: Array of reg value pairs for vbif registers |
| 757 | */ |
| 758 | struct adreno_vbif_platform { |
| 759 | int (*devfunc)(struct adreno_device *); |
| 760 | const struct adreno_vbif_data *vbif; |
| 761 | }; |
| 762 | |
| 763 | /* |
| 764 | * struct adreno_vbif_snapshot_registers - Holds an array of vbif registers |
| 765 | * listed for snapshot dump for a particular core |
| 766 | * @version: vbif version |
| 767 | * @mask: vbif revision mask |
| 768 | * @registers: vbif registers listed for snapshot dump |
| 769 | * @count: count of vbif registers listed for snapshot |
| 770 | */ |
| 771 | struct adreno_vbif_snapshot_registers { |
| 772 | const unsigned int version; |
| 773 | const unsigned int mask; |
| 774 | const unsigned int *registers; |
| 775 | const int count; |
| 776 | }; |
| 777 | |
| 778 | /** |
| 779 | * struct adreno_coresight_register - Definition for a coresight (tracebus) |
| 780 | * debug register |
| 781 | * @offset: Offset of the debug register in the KGSL mmio region |
| 782 | * @initial: Default value to write when coresight is enabled |
| 783 | * @value: Current shadow value of the register (to be reprogrammed after power |
| 784 | * collapse) |
| 785 | */ |
| 786 | struct adreno_coresight_register { |
| 787 | unsigned int offset; |
| 788 | unsigned int initial; |
| 789 | unsigned int value; |
| 790 | }; |
| 791 | |
| 792 | struct adreno_coresight_attr { |
| 793 | struct device_attribute attr; |
| 794 | struct adreno_coresight_register *reg; |
| 795 | }; |
| 796 | |
| 797 | ssize_t adreno_coresight_show_register(struct device *device, |
| 798 | struct device_attribute *attr, char *buf); |
| 799 | |
| 800 | ssize_t adreno_coresight_store_register(struct device *dev, |
| 801 | struct device_attribute *attr, const char *buf, size_t size); |
| 802 | |
| 803 | #define ADRENO_CORESIGHT_ATTR(_attrname, _reg) \ |
| 804 | struct adreno_coresight_attr coresight_attr_##_attrname = { \ |
| 805 | __ATTR(_attrname, 0644, \ |
| 806 | adreno_coresight_show_register, \ |
| 807 | adreno_coresight_store_register), \ |
| 808 | (_reg), } |
| 809 | |
| 810 | /** |
| 811 | * struct adreno_coresight - GPU specific coresight definition |
| 812 | * @registers - Array of GPU specific registers to configure trace bus output |
| 813 | * @count - Number of registers in the array |
| 814 | * @groups - Pointer to an attribute list of control files |
| 815 | * @atid - The unique ATID value of the coresight device |
| 816 | */ |
| 817 | struct adreno_coresight { |
| 818 | struct adreno_coresight_register *registers; |
| 819 | unsigned int count; |
| 820 | const struct attribute_group **groups; |
| 821 | unsigned int atid; |
| 822 | }; |
| 823 | |
| 824 | |
| 825 | struct adreno_irq_funcs { |
| 826 | void (*func)(struct adreno_device *, int); |
| 827 | }; |
| 828 | #define ADRENO_IRQ_CALLBACK(_c) { .func = _c } |
| 829 | |
| 830 | struct adreno_irq { |
| 831 | unsigned int mask; |
| 832 | struct adreno_irq_funcs *funcs; |
| 833 | }; |
| 834 | |
| 835 | /* |
| 836 | * struct adreno_debugbus_block - Holds info about debug buses of a chip |
| 837 | * @block_id: Bus identifier |
| 838 | * @dwords: Number of dwords of data that this block holds |
| 839 | */ |
| 840 | struct adreno_debugbus_block { |
| 841 | unsigned int block_id; |
| 842 | unsigned int dwords; |
| 843 | }; |
| 844 | |
| 845 | /* |
| 846 | * struct adreno_snapshot_section_sizes - Structure holding the size of |
| 847 | * different sections dumped during device snapshot |
| 848 | * @cp_pfp: CP PFP data section size |
| 849 | * @cp_me: CP ME data section size |
| 850 | * @vpc_mem: VPC memory section size |
| 851 | * @cp_meq: CP MEQ size |
| 852 | * @shader_mem: Size of shader memory of 1 shader section |
| 853 | * @cp_merciu: CP MERCIU size |
| 854 | * @roq: ROQ size |
| 855 | */ |
| 856 | struct adreno_snapshot_sizes { |
| 857 | int cp_pfp; |
| 858 | int cp_me; |
| 859 | int vpc_mem; |
| 860 | int cp_meq; |
| 861 | int shader_mem; |
| 862 | int cp_merciu; |
| 863 | int roq; |
| 864 | }; |
| 865 | |
| 866 | /* |
| 867 | * struct adreno_snapshot_data - Holds data used in snapshot |
| 868 | * @sect_sizes: Has sections sizes |
| 869 | */ |
| 870 | struct adreno_snapshot_data { |
| 871 | struct adreno_snapshot_sizes *sect_sizes; |
| 872 | }; |
| 873 | |
Kyle Piefer | edc6c8a | 2017-11-10 14:51:58 -0800 | [diff] [blame] | 874 | enum adreno_cp_marker_type { |
| 875 | IFPC_DISABLE, |
| 876 | IFPC_ENABLE, |
| 877 | IB1LIST_START, |
| 878 | IB1LIST_END, |
| 879 | }; |
| 880 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 881 | struct adreno_gpudev { |
| 882 | /* |
| 883 | * These registers are in a different location on different devices, |
| 884 | * so define them in the structure and use them as variables. |
| 885 | */ |
| 886 | const struct adreno_reg_offsets *reg_offsets; |
| 887 | unsigned int *const int_bits; |
| 888 | const struct adreno_ft_perf_counters *ft_perf_counters; |
| 889 | unsigned int ft_perf_counters_count; |
| 890 | |
| 891 | struct adreno_perfcounters *perfcounters; |
| 892 | const struct adreno_invalid_countables *invalid_countables; |
| 893 | struct adreno_snapshot_data *snapshot_data; |
| 894 | |
Lokesh Batra | a8300e0 | 2017-05-25 11:17:40 -0700 | [diff] [blame] | 895 | struct adreno_coresight *coresight[GPU_CORESIGHT_MAX]; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 896 | |
| 897 | struct adreno_irq *irq; |
| 898 | int num_prio_levels; |
| 899 | unsigned int vbif_xin_halt_ctrl0_mask; |
| 900 | /* GPU specific function hooks */ |
| 901 | void (*irq_trace)(struct adreno_device *, unsigned int status); |
| 902 | void (*snapshot)(struct adreno_device *, struct kgsl_snapshot *); |
Carter Cooper | b88b708 | 2017-09-14 09:03:26 -0600 | [diff] [blame] | 903 | void (*snapshot_gmu)(struct adreno_device *, struct kgsl_snapshot *); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 904 | void (*platform_setup)(struct adreno_device *); |
| 905 | void (*init)(struct adreno_device *); |
| 906 | void (*remove)(struct adreno_device *); |
| 907 | int (*rb_start)(struct adreno_device *, unsigned int start_type); |
| 908 | int (*microcode_read)(struct adreno_device *); |
| 909 | void (*perfcounter_init)(struct adreno_device *); |
| 910 | void (*perfcounter_close)(struct adreno_device *); |
| 911 | void (*start)(struct adreno_device *); |
| 912 | bool (*is_sptp_idle)(struct adreno_device *); |
| 913 | int (*regulator_enable)(struct adreno_device *); |
| 914 | void (*regulator_disable)(struct adreno_device *); |
| 915 | void (*pwrlevel_change_settings)(struct adreno_device *, |
| 916 | unsigned int prelevel, unsigned int postlevel, |
| 917 | bool post); |
| 918 | uint64_t (*read_throttling_counters)(struct adreno_device *); |
| 919 | void (*count_throttles)(struct adreno_device *, uint64_t adj); |
| 920 | int (*enable_pwr_counters)(struct adreno_device *, |
| 921 | unsigned int counter); |
| 922 | unsigned int (*preemption_pre_ibsubmit)( |
| 923 | struct adreno_device *adreno_dev, |
| 924 | struct adreno_ringbuffer *rb, |
| 925 | unsigned int *cmds, |
| 926 | struct kgsl_context *context); |
| 927 | int (*preemption_yield_enable)(unsigned int *); |
Kyle Piefer | edc6c8a | 2017-11-10 14:51:58 -0800 | [diff] [blame] | 928 | unsigned int (*set_marker)(unsigned int *cmds, |
| 929 | enum adreno_cp_marker_type type); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 930 | unsigned int (*preemption_post_ibsubmit)( |
| 931 | struct adreno_device *adreno_dev, |
| 932 | unsigned int *cmds); |
| 933 | int (*preemption_init)(struct adreno_device *); |
| 934 | void (*preemption_schedule)(struct adreno_device *); |
Harshdeep Dhatt | 2e42f12 | 2017-05-31 17:27:19 -0600 | [diff] [blame] | 935 | int (*preemption_context_init)(struct kgsl_context *); |
| 936 | void (*preemption_context_destroy)(struct kgsl_context *); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 937 | void (*enable_64bit)(struct adreno_device *); |
| 938 | void (*clk_set_options)(struct adreno_device *, |
Deepak Kumar | a309e0e | 2017-03-17 17:27:42 +0530 | [diff] [blame] | 939 | const char *, struct clk *, bool on); |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 940 | void (*llc_configure_gpu_scid)(struct adreno_device *adreno_dev); |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 941 | void (*llc_configure_gpuhtw_scid)(struct adreno_device *adreno_dev); |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 942 | void (*llc_enable_overrides)(struct adreno_device *adreno_dev); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 943 | void (*pre_reset)(struct adreno_device *); |
| 944 | int (*oob_set)(struct adreno_device *adreno_dev, unsigned int set_mask, |
| 945 | unsigned int check_mask, |
| 946 | unsigned int clear_mask); |
| 947 | void (*oob_clear)(struct adreno_device *adreno_dev, |
| 948 | unsigned int clear_mask); |
Carter Cooper | df7ba70 | 2017-03-20 11:28:04 -0600 | [diff] [blame] | 949 | void (*gpu_keepalive)(struct adreno_device *adreno_dev, |
| 950 | bool state); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 951 | int (*rpmh_gpu_pwrctrl)(struct adreno_device *, unsigned int ops, |
| 952 | unsigned int arg1, unsigned int arg2); |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 953 | bool (*hw_isidle)(struct adreno_device *); |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 954 | int (*wait_for_lowest_idle)(struct adreno_device *); |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 955 | int (*wait_for_gmu_idle)(struct adreno_device *); |
Lynus Vaz | 1fde74d | 2017-03-20 18:02:47 +0530 | [diff] [blame] | 956 | const char *(*iommu_fault_block)(struct adreno_device *adreno_dev, |
| 957 | unsigned int fsynr1); |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 958 | int (*reset)(struct kgsl_device *, int fault); |
Shrenuj Bansal | 49d0e9f | 2017-05-08 16:10:24 -0700 | [diff] [blame] | 959 | int (*soft_reset)(struct adreno_device *); |
Shrenuj Bansal | d197bf6 | 2017-04-07 11:00:09 -0700 | [diff] [blame] | 960 | bool (*gx_is_on)(struct adreno_device *); |
| 961 | bool (*sptprac_is_on)(struct adreno_device *); |
Harshdeep Dhatt | 6ba7a94 | 2017-08-21 17:53:52 -0600 | [diff] [blame] | 962 | unsigned int (*ccu_invalidate)(struct adreno_device *adreno_dev, |
| 963 | unsigned int *cmds); |
Tarun Karra | 1382e51 | 2017-10-30 19:41:25 -0700 | [diff] [blame] | 964 | int (*perfcounter_update)(struct adreno_device *adreno_dev, |
| 965 | struct adreno_perfcount_register *reg, |
| 966 | bool update_reg); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 967 | }; |
| 968 | |
| 969 | /** |
| 970 | * enum kgsl_ft_policy_bits - KGSL fault tolerance policy bits |
| 971 | * @KGSL_FT_OFF: Disable fault detection (not used) |
| 972 | * @KGSL_FT_REPLAY: Replay the faulting command |
| 973 | * @KGSL_FT_SKIPIB: Skip the faulting indirect buffer |
| 974 | * @KGSL_FT_SKIPFRAME: Skip the frame containing the faulting IB |
| 975 | * @KGSL_FT_DISABLE: Tells the dispatcher to disable FT for the command obj |
| 976 | * @KGSL_FT_TEMP_DISABLE: Disables FT for all commands |
| 977 | * @KGSL_FT_THROTTLE: Disable the context if it faults too often |
| 978 | * @KGSL_FT_SKIPCMD: Skip the command containing the faulting IB |
| 979 | */ |
| 980 | enum kgsl_ft_policy_bits { |
| 981 | KGSL_FT_OFF = 0, |
| 982 | KGSL_FT_REPLAY = 1, |
| 983 | KGSL_FT_SKIPIB = 2, |
| 984 | KGSL_FT_SKIPFRAME = 3, |
| 985 | KGSL_FT_DISABLE = 4, |
| 986 | KGSL_FT_TEMP_DISABLE = 5, |
| 987 | KGSL_FT_THROTTLE = 6, |
| 988 | KGSL_FT_SKIPCMD = 7, |
| 989 | /* KGSL_FT_MAX_BITS is used to calculate the mask */ |
| 990 | KGSL_FT_MAX_BITS, |
| 991 | /* Internal bits - set during GFT */ |
| 992 | /* Skip the PM dump on replayed command obj's */ |
| 993 | KGSL_FT_SKIP_PMDUMP = 31, |
| 994 | }; |
| 995 | |
| 996 | #define KGSL_FT_POLICY_MASK GENMASK(KGSL_FT_MAX_BITS - 1, 0) |
| 997 | |
| 998 | #define KGSL_FT_DEFAULT_POLICY \ |
| 999 | (BIT(KGSL_FT_REPLAY) | \ |
| 1000 | BIT(KGSL_FT_SKIPCMD) | \ |
| 1001 | BIT(KGSL_FT_THROTTLE)) |
| 1002 | |
| 1003 | #define ADRENO_FT_TYPES \ |
| 1004 | { BIT(KGSL_FT_OFF), "off" }, \ |
| 1005 | { BIT(KGSL_FT_REPLAY), "replay" }, \ |
| 1006 | { BIT(KGSL_FT_SKIPIB), "skipib" }, \ |
| 1007 | { BIT(KGSL_FT_SKIPFRAME), "skipframe" }, \ |
| 1008 | { BIT(KGSL_FT_DISABLE), "disable" }, \ |
| 1009 | { BIT(KGSL_FT_TEMP_DISABLE), "temp" }, \ |
| 1010 | { BIT(KGSL_FT_THROTTLE), "throttle"}, \ |
| 1011 | { BIT(KGSL_FT_SKIPCMD), "skipcmd" } |
| 1012 | |
| 1013 | /** |
| 1014 | * enum kgsl_ft_pagefault_policy_bits - KGSL pagefault policy bits |
| 1015 | * @KGSL_FT_PAGEFAULT_INT_ENABLE: No longer used, but retained for compatibility |
| 1016 | * @KGSL_FT_PAGEFAULT_GPUHALT_ENABLE: enable GPU halt on pagefaults |
| 1017 | * @KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE: log one pagefault per page |
| 1018 | * @KGSL_FT_PAGEFAULT_LOG_ONE_PER_INT: log one pagefault per interrupt |
| 1019 | */ |
| 1020 | enum { |
| 1021 | KGSL_FT_PAGEFAULT_INT_ENABLE = 0, |
| 1022 | KGSL_FT_PAGEFAULT_GPUHALT_ENABLE = 1, |
| 1023 | KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE = 2, |
| 1024 | KGSL_FT_PAGEFAULT_LOG_ONE_PER_INT = 3, |
| 1025 | /* KGSL_FT_PAGEFAULT_MAX_BITS is used to calculate the mask */ |
| 1026 | KGSL_FT_PAGEFAULT_MAX_BITS, |
| 1027 | }; |
| 1028 | |
| 1029 | #define KGSL_FT_PAGEFAULT_MASK GENMASK(KGSL_FT_PAGEFAULT_MAX_BITS - 1, 0) |
| 1030 | |
| 1031 | #define KGSL_FT_PAGEFAULT_DEFAULT_POLICY 0 |
| 1032 | |
| 1033 | #define FOR_EACH_RINGBUFFER(_dev, _rb, _i) \ |
| 1034 | for ((_i) = 0, (_rb) = &((_dev)->ringbuffers[0]); \ |
| 1035 | (_i) < (_dev)->num_ringbuffers; \ |
| 1036 | (_i)++, (_rb)++) |
| 1037 | |
| 1038 | struct adreno_ft_perf_counters { |
| 1039 | unsigned int counter; |
| 1040 | unsigned int countable; |
| 1041 | }; |
| 1042 | |
| 1043 | extern unsigned int *adreno_ft_regs; |
| 1044 | extern unsigned int adreno_ft_regs_num; |
| 1045 | extern unsigned int *adreno_ft_regs_val; |
| 1046 | |
| 1047 | extern struct adreno_gpudev adreno_a3xx_gpudev; |
| 1048 | extern struct adreno_gpudev adreno_a4xx_gpudev; |
| 1049 | extern struct adreno_gpudev adreno_a5xx_gpudev; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1050 | extern struct adreno_gpudev adreno_a6xx_gpudev; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1051 | |
| 1052 | extern int adreno_wake_nice; |
| 1053 | extern unsigned int adreno_wake_timeout; |
| 1054 | |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 1055 | int adreno_start(struct kgsl_device *device, int priority); |
| 1056 | int adreno_soft_reset(struct kgsl_device *device); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1057 | long adreno_ioctl(struct kgsl_device_private *dev_priv, |
| 1058 | unsigned int cmd, unsigned long arg); |
| 1059 | |
| 1060 | long adreno_ioctl_helper(struct kgsl_device_private *dev_priv, |
| 1061 | unsigned int cmd, unsigned long arg, |
| 1062 | const struct kgsl_ioctl *cmds, int len); |
| 1063 | |
Carter Cooper | 1d8f547 | 2017-03-15 15:01:09 -0600 | [diff] [blame] | 1064 | int a5xx_critical_packet_submit(struct adreno_device *adreno_dev, |
| 1065 | struct adreno_ringbuffer *rb); |
| 1066 | int adreno_set_unsecured_mode(struct adreno_device *adreno_dev, |
| 1067 | struct adreno_ringbuffer *rb); |
Carter Cooper | 8567af0 | 2017-03-15 14:22:03 -0600 | [diff] [blame] | 1068 | void adreno_spin_idle_debug(struct adreno_device *adreno_dev, const char *str); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1069 | int adreno_spin_idle(struct adreno_device *device, unsigned int timeout); |
| 1070 | int adreno_idle(struct kgsl_device *device); |
| 1071 | bool adreno_isidle(struct kgsl_device *device); |
| 1072 | |
| 1073 | int adreno_set_constraint(struct kgsl_device *device, |
| 1074 | struct kgsl_context *context, |
| 1075 | struct kgsl_device_constraint *constraint); |
| 1076 | |
| 1077 | void adreno_shadermem_regread(struct kgsl_device *device, |
| 1078 | unsigned int offsetwords, |
| 1079 | unsigned int *value); |
| 1080 | |
| 1081 | void adreno_snapshot(struct kgsl_device *device, |
| 1082 | struct kgsl_snapshot *snapshot, |
| 1083 | struct kgsl_context *context); |
| 1084 | |
Carter Cooper | b88b708 | 2017-09-14 09:03:26 -0600 | [diff] [blame] | 1085 | void adreno_snapshot_gmu(struct kgsl_device *device, |
| 1086 | struct kgsl_snapshot *snapshot); |
| 1087 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1088 | int adreno_reset(struct kgsl_device *device, int fault); |
| 1089 | |
| 1090 | void adreno_fault_skipcmd_detached(struct adreno_device *adreno_dev, |
| 1091 | struct adreno_context *drawctxt, |
| 1092 | struct kgsl_drawobj *drawobj); |
| 1093 | |
| 1094 | int adreno_coresight_init(struct adreno_device *adreno_dev); |
| 1095 | |
| 1096 | void adreno_coresight_start(struct adreno_device *adreno_dev); |
| 1097 | void adreno_coresight_stop(struct adreno_device *adreno_dev); |
| 1098 | |
| 1099 | void adreno_coresight_remove(struct adreno_device *adreno_dev); |
| 1100 | |
| 1101 | bool adreno_hw_isidle(struct adreno_device *adreno_dev); |
| 1102 | |
| 1103 | void adreno_fault_detect_start(struct adreno_device *adreno_dev); |
| 1104 | void adreno_fault_detect_stop(struct adreno_device *adreno_dev); |
| 1105 | |
| 1106 | void adreno_hang_int_callback(struct adreno_device *adreno_dev, int bit); |
| 1107 | void adreno_cp_callback(struct adreno_device *adreno_dev, int bit); |
| 1108 | |
| 1109 | int adreno_sysfs_init(struct adreno_device *adreno_dev); |
| 1110 | void adreno_sysfs_close(struct adreno_device *adreno_dev); |
| 1111 | |
| 1112 | void adreno_irqctrl(struct adreno_device *adreno_dev, int state); |
| 1113 | |
| 1114 | long adreno_ioctl_perfcounter_get(struct kgsl_device_private *dev_priv, |
| 1115 | unsigned int cmd, void *data); |
| 1116 | |
| 1117 | long adreno_ioctl_perfcounter_put(struct kgsl_device_private *dev_priv, |
| 1118 | unsigned int cmd, void *data); |
| 1119 | |
| 1120 | int adreno_efuse_map(struct adreno_device *adreno_dev); |
| 1121 | int adreno_efuse_read_u32(struct adreno_device *adreno_dev, unsigned int offset, |
| 1122 | unsigned int *val); |
| 1123 | void adreno_efuse_unmap(struct adreno_device *adreno_dev); |
| 1124 | |
Lynus Vaz | 9ed8cf9 | 2017-09-21 21:55:34 +0530 | [diff] [blame] | 1125 | bool adreno_is_cx_dbgc_register(struct kgsl_device *device, |
| 1126 | unsigned int offset); |
| 1127 | void adreno_cx_dbgc_regread(struct kgsl_device *adreno_device, |
| 1128 | unsigned int offsetwords, unsigned int *value); |
| 1129 | void adreno_cx_dbgc_regwrite(struct kgsl_device *device, |
| 1130 | unsigned int offsetwords, unsigned int value); |
| 1131 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1132 | #define ADRENO_TARGET(_name, _id) \ |
| 1133 | static inline int adreno_is_##_name(struct adreno_device *adreno_dev) \ |
| 1134 | { \ |
| 1135 | return (ADRENO_GPUREV(adreno_dev) == (_id)); \ |
| 1136 | } |
| 1137 | |
| 1138 | static inline int adreno_is_a3xx(struct adreno_device *adreno_dev) |
| 1139 | { |
| 1140 | return ((ADRENO_GPUREV(adreno_dev) >= 300) && |
| 1141 | (ADRENO_GPUREV(adreno_dev) < 400)); |
| 1142 | } |
| 1143 | |
| 1144 | ADRENO_TARGET(a304, ADRENO_REV_A304) |
| 1145 | ADRENO_TARGET(a305, ADRENO_REV_A305) |
| 1146 | ADRENO_TARGET(a305b, ADRENO_REV_A305B) |
| 1147 | ADRENO_TARGET(a305c, ADRENO_REV_A305C) |
| 1148 | ADRENO_TARGET(a306, ADRENO_REV_A306) |
| 1149 | ADRENO_TARGET(a306a, ADRENO_REV_A306A) |
| 1150 | ADRENO_TARGET(a310, ADRENO_REV_A310) |
| 1151 | ADRENO_TARGET(a320, ADRENO_REV_A320) |
| 1152 | ADRENO_TARGET(a330, ADRENO_REV_A330) |
| 1153 | |
| 1154 | static inline int adreno_is_a330v2(struct adreno_device *adreno_dev) |
| 1155 | { |
| 1156 | return ((ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A330) && |
| 1157 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) > 0)); |
| 1158 | } |
| 1159 | |
| 1160 | static inline int adreno_is_a330v21(struct adreno_device *adreno_dev) |
| 1161 | { |
| 1162 | return ((ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A330) && |
| 1163 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) > 0xF)); |
| 1164 | } |
| 1165 | |
| 1166 | static inline int adreno_is_a4xx(struct adreno_device *adreno_dev) |
| 1167 | { |
| 1168 | return ADRENO_GPUREV(adreno_dev) >= 400 && |
| 1169 | ADRENO_GPUREV(adreno_dev) < 500; |
| 1170 | } |
| 1171 | |
| 1172 | ADRENO_TARGET(a405, ADRENO_REV_A405); |
| 1173 | |
| 1174 | static inline int adreno_is_a405v2(struct adreno_device *adreno_dev) |
| 1175 | { |
| 1176 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A405) && |
| 1177 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0x10); |
| 1178 | } |
| 1179 | |
| 1180 | ADRENO_TARGET(a418, ADRENO_REV_A418) |
| 1181 | ADRENO_TARGET(a420, ADRENO_REV_A420) |
| 1182 | ADRENO_TARGET(a430, ADRENO_REV_A430) |
| 1183 | |
| 1184 | static inline int adreno_is_a430v2(struct adreno_device *adreno_dev) |
| 1185 | { |
| 1186 | return ((ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A430) && |
| 1187 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1)); |
| 1188 | } |
| 1189 | |
| 1190 | static inline int adreno_is_a5xx(struct adreno_device *adreno_dev) |
| 1191 | { |
| 1192 | return ADRENO_GPUREV(adreno_dev) >= 500 && |
| 1193 | ADRENO_GPUREV(adreno_dev) < 600; |
| 1194 | } |
| 1195 | |
| 1196 | ADRENO_TARGET(a505, ADRENO_REV_A505) |
| 1197 | ADRENO_TARGET(a506, ADRENO_REV_A506) |
Rajesh Kemisetti | aed6ec7 | 2017-02-06 09:37:00 +0530 | [diff] [blame] | 1198 | ADRENO_TARGET(a508, ADRENO_REV_A508) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1199 | ADRENO_TARGET(a510, ADRENO_REV_A510) |
| 1200 | ADRENO_TARGET(a512, ADRENO_REV_A512) |
| 1201 | ADRENO_TARGET(a530, ADRENO_REV_A530) |
| 1202 | ADRENO_TARGET(a540, ADRENO_REV_A540) |
| 1203 | |
| 1204 | static inline int adreno_is_a530v1(struct adreno_device *adreno_dev) |
| 1205 | { |
| 1206 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530) && |
| 1207 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0); |
| 1208 | } |
| 1209 | |
| 1210 | static inline int adreno_is_a530v2(struct adreno_device *adreno_dev) |
| 1211 | { |
| 1212 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530) && |
| 1213 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1); |
| 1214 | } |
| 1215 | |
| 1216 | static inline int adreno_is_a530v3(struct adreno_device *adreno_dev) |
| 1217 | { |
| 1218 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530) && |
| 1219 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 2); |
| 1220 | } |
| 1221 | |
| 1222 | static inline int adreno_is_a505_or_a506(struct adreno_device *adreno_dev) |
| 1223 | { |
| 1224 | return ADRENO_GPUREV(adreno_dev) >= 505 && |
| 1225 | ADRENO_GPUREV(adreno_dev) <= 506; |
| 1226 | } |
| 1227 | |
| 1228 | static inline int adreno_is_a540v1(struct adreno_device *adreno_dev) |
| 1229 | { |
| 1230 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A540) && |
| 1231 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0); |
| 1232 | } |
| 1233 | |
| 1234 | static inline int adreno_is_a540v2(struct adreno_device *adreno_dev) |
| 1235 | { |
| 1236 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A540) && |
| 1237 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1); |
| 1238 | } |
| 1239 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1240 | static inline int adreno_is_a6xx(struct adreno_device *adreno_dev) |
| 1241 | { |
| 1242 | return ADRENO_GPUREV(adreno_dev) >= 600 && |
| 1243 | ADRENO_GPUREV(adreno_dev) < 700; |
| 1244 | } |
| 1245 | |
Rajesh Kemisetti | 8d5cc6e | 2017-06-06 16:44:17 +0530 | [diff] [blame] | 1246 | ADRENO_TARGET(a615, ADRENO_REV_A615) |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1247 | ADRENO_TARGET(a630, ADRENO_REV_A630) |
| 1248 | |
Shrenuj Bansal | 397e589 | 2017-03-13 13:38:47 -0700 | [diff] [blame] | 1249 | static inline int adreno_is_a630v1(struct adreno_device *adreno_dev) |
| 1250 | { |
| 1251 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A630) && |
| 1252 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0); |
| 1253 | } |
| 1254 | |
Kyle Piefer | 24029597 | 2017-08-10 11:38:00 -0700 | [diff] [blame] | 1255 | static inline int adreno_is_a630v2(struct adreno_device *adreno_dev) |
| 1256 | { |
| 1257 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A630) && |
| 1258 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1); |
| 1259 | } |
| 1260 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1261 | /* |
| 1262 | * adreno_checkreg_off() - Checks the validity of a register enum |
| 1263 | * @adreno_dev: Pointer to adreno device |
| 1264 | * @offset_name: The register enum that is checked |
| 1265 | */ |
| 1266 | static inline bool adreno_checkreg_off(struct adreno_device *adreno_dev, |
| 1267 | enum adreno_regs offset_name) |
| 1268 | { |
| 1269 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1270 | |
| 1271 | if (offset_name >= ADRENO_REG_REGISTER_MAX || |
| 1272 | gpudev->reg_offsets->offsets[offset_name] == ADRENO_REG_UNUSED) |
| 1273 | return false; |
| 1274 | |
| 1275 | /* |
| 1276 | * GPU register programming is kept common as much as possible |
| 1277 | * across the cores, Use ADRENO_REG_SKIP when certain register |
| 1278 | * programming needs to be skipped for certain GPU cores. |
| 1279 | * Example: Certain registers on a5xx like IB1_BASE are 64 bit. |
| 1280 | * Common programming programs 64bit register but upper 32 bits |
| 1281 | * are skipped in a4xx and a3xx using ADRENO_REG_SKIP. |
| 1282 | */ |
| 1283 | if (gpudev->reg_offsets->offsets[offset_name] == ADRENO_REG_SKIP) |
| 1284 | return false; |
| 1285 | |
| 1286 | return true; |
| 1287 | } |
| 1288 | |
| 1289 | /* |
| 1290 | * adreno_readreg() - Read a register by getting its offset from the |
| 1291 | * offset array defined in gpudev node |
| 1292 | * @adreno_dev: Pointer to the the adreno device |
| 1293 | * @offset_name: The register enum that is to be read |
| 1294 | * @val: Register value read is placed here |
| 1295 | */ |
| 1296 | static inline void adreno_readreg(struct adreno_device *adreno_dev, |
| 1297 | enum adreno_regs offset_name, unsigned int *val) |
| 1298 | { |
| 1299 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1300 | |
| 1301 | if (adreno_checkreg_off(adreno_dev, offset_name)) |
| 1302 | kgsl_regread(KGSL_DEVICE(adreno_dev), |
| 1303 | gpudev->reg_offsets->offsets[offset_name], val); |
| 1304 | else |
| 1305 | *val = 0; |
| 1306 | } |
| 1307 | |
| 1308 | /* |
| 1309 | * adreno_writereg() - Write a register by getting its offset from the |
| 1310 | * offset array defined in gpudev node |
| 1311 | * @adreno_dev: Pointer to the the adreno device |
| 1312 | * @offset_name: The register enum that is to be written |
| 1313 | * @val: Value to write |
| 1314 | */ |
| 1315 | static inline void adreno_writereg(struct adreno_device *adreno_dev, |
| 1316 | enum adreno_regs offset_name, unsigned int val) |
| 1317 | { |
| 1318 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1319 | |
| 1320 | if (adreno_checkreg_off(adreno_dev, offset_name)) |
| 1321 | kgsl_regwrite(KGSL_DEVICE(adreno_dev), |
| 1322 | gpudev->reg_offsets->offsets[offset_name], val); |
| 1323 | } |
| 1324 | |
| 1325 | /* |
| 1326 | * adreno_getreg() - Returns the offset value of a register from the |
| 1327 | * register offset array in the gpudev node |
| 1328 | * @adreno_dev: Pointer to the the adreno device |
| 1329 | * @offset_name: The register enum whore offset is returned |
| 1330 | */ |
| 1331 | static inline unsigned int adreno_getreg(struct adreno_device *adreno_dev, |
| 1332 | enum adreno_regs offset_name) |
| 1333 | { |
| 1334 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1335 | |
| 1336 | if (!adreno_checkreg_off(adreno_dev, offset_name)) |
| 1337 | return ADRENO_REG_REGISTER_MAX; |
| 1338 | return gpudev->reg_offsets->offsets[offset_name]; |
| 1339 | } |
| 1340 | |
| 1341 | /* |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1342 | * adreno_read_gmureg() - Read a GMU register by getting its offset from the |
| 1343 | * offset array defined in gpudev node |
| 1344 | * @adreno_dev: Pointer to the the adreno device |
| 1345 | * @offset_name: The register enum that is to be read |
| 1346 | * @val: Register value read is placed here |
| 1347 | */ |
| 1348 | static inline void adreno_read_gmureg(struct adreno_device *adreno_dev, |
| 1349 | enum adreno_regs offset_name, unsigned int *val) |
| 1350 | { |
| 1351 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1352 | |
| 1353 | if (adreno_checkreg_off(adreno_dev, offset_name)) |
| 1354 | kgsl_gmu_regread(KGSL_DEVICE(adreno_dev), |
| 1355 | gpudev->reg_offsets->offsets[offset_name], val); |
| 1356 | else |
Carter Cooper | 83454bf | 2017-03-20 11:26:04 -0600 | [diff] [blame] | 1357 | *val = 0; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1358 | } |
| 1359 | |
| 1360 | /* |
| 1361 | * adreno_write_gmureg() - Write a GMU register by getting its offset from the |
| 1362 | * offset array defined in gpudev node |
| 1363 | * @adreno_dev: Pointer to the the adreno device |
| 1364 | * @offset_name: The register enum that is to be written |
| 1365 | * @val: Value to write |
| 1366 | */ |
| 1367 | static inline void adreno_write_gmureg(struct adreno_device *adreno_dev, |
| 1368 | enum adreno_regs offset_name, unsigned int val) |
| 1369 | { |
| 1370 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1371 | |
| 1372 | if (adreno_checkreg_off(adreno_dev, offset_name)) |
| 1373 | kgsl_gmu_regwrite(KGSL_DEVICE(adreno_dev), |
| 1374 | gpudev->reg_offsets->offsets[offset_name], val); |
| 1375 | } |
| 1376 | |
| 1377 | /* |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1378 | * adreno_get_int() - Returns the offset value of an interrupt bit from |
| 1379 | * the interrupt bit array in the gpudev node |
| 1380 | * @adreno_dev: Pointer to the the adreno device |
| 1381 | * @bit_name: The interrupt bit enum whose bit is returned |
| 1382 | */ |
| 1383 | static inline unsigned int adreno_get_int(struct adreno_device *adreno_dev, |
| 1384 | enum adreno_int_bits bit_name) |
| 1385 | { |
| 1386 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1387 | |
| 1388 | if (bit_name >= ADRENO_INT_BITS_MAX) |
| 1389 | return -ERANGE; |
| 1390 | |
| 1391 | return gpudev->int_bits[bit_name]; |
| 1392 | } |
| 1393 | |
| 1394 | /** |
| 1395 | * adreno_gpu_fault() - Return the current state of the GPU |
| 1396 | * @adreno_dev: A pointer to the adreno_device to query |
| 1397 | * |
| 1398 | * Return 0 if there is no fault or positive with the last type of fault that |
| 1399 | * occurred |
| 1400 | */ |
| 1401 | static inline unsigned int adreno_gpu_fault(struct adreno_device *adreno_dev) |
| 1402 | { |
| 1403 | /* make sure we're reading the latest value */ |
| 1404 | smp_rmb(); |
| 1405 | return atomic_read(&adreno_dev->dispatcher.fault); |
| 1406 | } |
| 1407 | |
| 1408 | /** |
| 1409 | * adreno_set_gpu_fault() - Set the current fault status of the GPU |
| 1410 | * @adreno_dev: A pointer to the adreno_device to set |
| 1411 | * @state: fault state to set |
| 1412 | * |
| 1413 | */ |
| 1414 | static inline void adreno_set_gpu_fault(struct adreno_device *adreno_dev, |
| 1415 | int state) |
| 1416 | { |
| 1417 | /* only set the fault bit w/o overwriting other bits */ |
| 1418 | atomic_add(state, &adreno_dev->dispatcher.fault); |
| 1419 | |
| 1420 | /* make sure other CPUs see the update */ |
| 1421 | smp_wmb(); |
| 1422 | } |
| 1423 | |
Lynus Vaz | 43695aa | 2017-09-01 21:55:23 +0530 | [diff] [blame] | 1424 | static inline bool adreno_gmu_gpu_fault(struct adreno_device *adreno_dev) |
| 1425 | { |
| 1426 | return adreno_gpu_fault(adreno_dev) & ADRENO_GMU_FAULT; |
| 1427 | } |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1428 | |
| 1429 | /** |
| 1430 | * adreno_clear_gpu_fault() - Clear the GPU fault register |
| 1431 | * @adreno_dev: A pointer to an adreno_device structure |
| 1432 | * |
| 1433 | * Clear the GPU fault status for the adreno device |
| 1434 | */ |
| 1435 | |
| 1436 | static inline void adreno_clear_gpu_fault(struct adreno_device *adreno_dev) |
| 1437 | { |
| 1438 | atomic_set(&adreno_dev->dispatcher.fault, 0); |
| 1439 | |
| 1440 | /* make sure other CPUs see the update */ |
| 1441 | smp_wmb(); |
| 1442 | } |
| 1443 | |
| 1444 | /** |
| 1445 | * adreno_gpu_halt() - Return the GPU halt refcount |
| 1446 | * @adreno_dev: A pointer to the adreno_device |
| 1447 | */ |
| 1448 | static inline int adreno_gpu_halt(struct adreno_device *adreno_dev) |
| 1449 | { |
| 1450 | /* make sure we're reading the latest value */ |
| 1451 | smp_rmb(); |
| 1452 | return atomic_read(&adreno_dev->halt); |
| 1453 | } |
| 1454 | |
| 1455 | |
| 1456 | /** |
| 1457 | * adreno_clear_gpu_halt() - Clear the GPU halt refcount |
| 1458 | * @adreno_dev: A pointer to the adreno_device |
| 1459 | */ |
| 1460 | static inline void adreno_clear_gpu_halt(struct adreno_device *adreno_dev) |
| 1461 | { |
| 1462 | atomic_set(&adreno_dev->halt, 0); |
| 1463 | |
| 1464 | /* make sure other CPUs see the update */ |
| 1465 | smp_wmb(); |
| 1466 | } |
| 1467 | |
| 1468 | /** |
| 1469 | * adreno_get_gpu_halt() - Increment GPU halt refcount |
| 1470 | * @adreno_dev: A pointer to the adreno_device |
| 1471 | */ |
| 1472 | static inline void adreno_get_gpu_halt(struct adreno_device *adreno_dev) |
| 1473 | { |
| 1474 | atomic_inc(&adreno_dev->halt); |
| 1475 | } |
| 1476 | |
| 1477 | /** |
| 1478 | * adreno_put_gpu_halt() - Decrement GPU halt refcount |
| 1479 | * @adreno_dev: A pointer to the adreno_device |
| 1480 | */ |
| 1481 | static inline void adreno_put_gpu_halt(struct adreno_device *adreno_dev) |
| 1482 | { |
| 1483 | /* Make sure the refcount is good */ |
| 1484 | int ret = atomic_dec_if_positive(&adreno_dev->halt); |
| 1485 | |
| 1486 | WARN(ret < 0, "GPU halt refcount unbalanced\n"); |
| 1487 | } |
| 1488 | |
| 1489 | |
| 1490 | /* |
| 1491 | * adreno_vbif_start() - Program VBIF registers, called in device start |
| 1492 | * @adreno_dev: Pointer to device whose vbif data is to be programmed |
| 1493 | * @vbif_platforms: list register value pair of vbif for a family |
| 1494 | * of adreno cores |
| 1495 | * @num_platforms: Number of platforms contained in vbif_platforms |
| 1496 | */ |
| 1497 | static inline void adreno_vbif_start(struct adreno_device *adreno_dev, |
| 1498 | const struct adreno_vbif_platform *vbif_platforms, |
| 1499 | int num_platforms) |
| 1500 | { |
| 1501 | int i; |
| 1502 | const struct adreno_vbif_data *vbif = NULL; |
| 1503 | |
| 1504 | for (i = 0; i < num_platforms; i++) { |
| 1505 | if (vbif_platforms[i].devfunc(adreno_dev)) { |
| 1506 | vbif = vbif_platforms[i].vbif; |
| 1507 | break; |
| 1508 | } |
| 1509 | } |
| 1510 | |
| 1511 | while ((vbif != NULL) && (vbif->reg != 0)) { |
| 1512 | kgsl_regwrite(KGSL_DEVICE(adreno_dev), vbif->reg, vbif->val); |
| 1513 | vbif++; |
| 1514 | } |
| 1515 | } |
| 1516 | |
| 1517 | /** |
| 1518 | * adreno_set_protected_registers() - Protect the specified range of registers |
| 1519 | * from being accessed by the GPU |
| 1520 | * @adreno_dev: pointer to the Adreno device |
| 1521 | * @index: Pointer to the index of the protect mode register to write to |
| 1522 | * @reg: Starting dword register to write |
| 1523 | * @mask_len: Size of the mask to protect (# of registers = 2 ** mask_len) |
| 1524 | * |
| 1525 | * Add the range of registers to the list of protected mode registers that will |
| 1526 | * cause an exception if the GPU accesses them. There are 16 available |
| 1527 | * protected mode registers. Index is used to specify which register to write |
| 1528 | * to - the intent is to call this function multiple times with the same index |
| 1529 | * pointer for each range and the registers will be magically programmed in |
| 1530 | * incremental fashion |
| 1531 | */ |
| 1532 | static inline void adreno_set_protected_registers( |
| 1533 | struct adreno_device *adreno_dev, unsigned int *index, |
| 1534 | unsigned int reg, int mask_len) |
| 1535 | { |
| 1536 | unsigned int val; |
| 1537 | unsigned int base = |
| 1538 | adreno_getreg(adreno_dev, ADRENO_REG_CP_PROTECT_REG_0); |
| 1539 | unsigned int offset = *index; |
| 1540 | unsigned int max_slots = adreno_dev->gpucore->num_protected_regs ? |
| 1541 | adreno_dev->gpucore->num_protected_regs : 16; |
| 1542 | |
| 1543 | /* Do we have a free slot? */ |
| 1544 | if (WARN(*index >= max_slots, "Protected register slots full: %d/%d\n", |
| 1545 | *index, max_slots)) |
| 1546 | return; |
| 1547 | |
| 1548 | /* |
| 1549 | * On A4XX targets with more than 16 protected mode registers |
| 1550 | * the upper registers are not contiguous with the lower 16 |
| 1551 | * registers so we have to adjust the base and offset accordingly |
| 1552 | */ |
| 1553 | |
| 1554 | if (adreno_is_a4xx(adreno_dev) && *index >= 0x10) { |
| 1555 | base = A4XX_CP_PROTECT_REG_10; |
| 1556 | offset = *index - 0x10; |
| 1557 | } |
| 1558 | |
| 1559 | val = 0x60000000 | ((mask_len & 0x1F) << 24) | ((reg << 2) & 0xFFFFF); |
| 1560 | |
| 1561 | kgsl_regwrite(KGSL_DEVICE(adreno_dev), base + offset, val); |
| 1562 | *index = *index + 1; |
| 1563 | } |
| 1564 | |
| 1565 | #ifdef CONFIG_DEBUG_FS |
| 1566 | void adreno_debugfs_init(struct adreno_device *adreno_dev); |
| 1567 | void adreno_context_debugfs_init(struct adreno_device *adreno_dev, |
| 1568 | struct adreno_context *ctx); |
| 1569 | #else |
| 1570 | static inline void adreno_debugfs_init(struct adreno_device *adreno_dev) { } |
| 1571 | static inline void adreno_context_debugfs_init(struct adreno_device *device, |
| 1572 | struct adreno_context *context) |
| 1573 | { } |
| 1574 | #endif |
| 1575 | |
| 1576 | /** |
| 1577 | * adreno_compare_pm4_version() - Compare the PM4 microcode version |
| 1578 | * @adreno_dev: Pointer to the adreno_device struct |
| 1579 | * @version: Version number to compare again |
| 1580 | * |
| 1581 | * Compare the current version against the specified version and return -1 if |
| 1582 | * the current code is older, 0 if equal or 1 if newer. |
| 1583 | */ |
| 1584 | static inline int adreno_compare_pm4_version(struct adreno_device *adreno_dev, |
| 1585 | unsigned int version) |
| 1586 | { |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1587 | if (adreno_dev->fw[ADRENO_FW_PM4].version == version) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1588 | return 0; |
| 1589 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1590 | return (adreno_dev->fw[ADRENO_FW_PM4].version > version) ? 1 : -1; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1591 | } |
| 1592 | |
| 1593 | /** |
| 1594 | * adreno_compare_pfp_version() - Compare the PFP microcode version |
| 1595 | * @adreno_dev: Pointer to the adreno_device struct |
| 1596 | * @version: Version number to compare against |
| 1597 | * |
| 1598 | * Compare the current version against the specified version and return -1 if |
| 1599 | * the current code is older, 0 if equal or 1 if newer. |
| 1600 | */ |
| 1601 | static inline int adreno_compare_pfp_version(struct adreno_device *adreno_dev, |
| 1602 | unsigned int version) |
| 1603 | { |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1604 | if (adreno_dev->fw[ADRENO_FW_PFP].version == version) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1605 | return 0; |
| 1606 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1607 | return (adreno_dev->fw[ADRENO_FW_PFP].version > version) ? 1 : -1; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1608 | } |
| 1609 | |
| 1610 | /* |
| 1611 | * adreno_bootstrap_ucode() - Checks if Ucode bootstrapping is supported |
| 1612 | * @adreno_dev: Pointer to the the adreno device |
| 1613 | */ |
| 1614 | static inline int adreno_bootstrap_ucode(struct adreno_device *adreno_dev) |
| 1615 | { |
| 1616 | return (ADRENO_FEATURE(adreno_dev, ADRENO_USE_BOOTSTRAP) && |
| 1617 | adreno_compare_pfp_version(adreno_dev, |
| 1618 | adreno_dev->gpucore->pfp_bstrp_ver) >= 0) ? 1 : 0; |
| 1619 | } |
| 1620 | |
| 1621 | /** |
| 1622 | * adreno_in_preempt_state() - Check if preemption state is equal to given state |
| 1623 | * @adreno_dev: Device whose preemption state is checked |
| 1624 | * @state: State to compare against |
| 1625 | */ |
| 1626 | static inline bool adreno_in_preempt_state(struct adreno_device *adreno_dev, |
| 1627 | enum adreno_preempt_states state) |
| 1628 | { |
| 1629 | return atomic_read(&adreno_dev->preempt.state) == state; |
| 1630 | } |
| 1631 | /** |
| 1632 | * adreno_set_preempt_state() - Set the specified preemption state |
| 1633 | * @adreno_dev: Device to change preemption state |
| 1634 | * @state: State to set |
| 1635 | */ |
| 1636 | static inline void adreno_set_preempt_state(struct adreno_device *adreno_dev, |
| 1637 | enum adreno_preempt_states state) |
| 1638 | { |
| 1639 | /* |
| 1640 | * atomic_set doesn't use barriers, so we need to do it ourselves. One |
| 1641 | * before... |
| 1642 | */ |
| 1643 | smp_wmb(); |
| 1644 | atomic_set(&adreno_dev->preempt.state, state); |
| 1645 | |
| 1646 | /* ... and one after */ |
| 1647 | smp_wmb(); |
| 1648 | } |
| 1649 | |
Harshdeep Dhatt | 38e57d7 | 2017-08-30 13:24:07 -0600 | [diff] [blame] | 1650 | static inline bool adreno_is_preemption_execution_enabled( |
| 1651 | struct adreno_device *adreno_dev) |
| 1652 | { |
| 1653 | return test_bit(ADRENO_DEVICE_PREEMPTION_EXECUTION, &adreno_dev->priv); |
| 1654 | } |
| 1655 | |
| 1656 | static inline bool adreno_is_preemption_setup_enabled( |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1657 | struct adreno_device *adreno_dev) |
| 1658 | { |
| 1659 | return test_bit(ADRENO_DEVICE_PREEMPTION, &adreno_dev->priv); |
| 1660 | } |
Harshdeep Dhatt | 38e57d7 | 2017-08-30 13:24:07 -0600 | [diff] [blame] | 1661 | |
| 1662 | static inline bool adreno_is_preemption_enabled( |
| 1663 | struct adreno_device *adreno_dev) |
| 1664 | { |
| 1665 | return 0; |
| 1666 | } |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1667 | /** |
| 1668 | * adreno_ctx_get_rb() - Return the ringbuffer that a context should |
| 1669 | * use based on priority |
| 1670 | * @adreno_dev: The adreno device that context is using |
| 1671 | * @drawctxt: The context pointer |
| 1672 | */ |
| 1673 | static inline struct adreno_ringbuffer *adreno_ctx_get_rb( |
| 1674 | struct adreno_device *adreno_dev, |
| 1675 | struct adreno_context *drawctxt) |
| 1676 | { |
| 1677 | struct kgsl_context *context; |
| 1678 | int level; |
| 1679 | |
| 1680 | if (!drawctxt) |
| 1681 | return NULL; |
| 1682 | |
| 1683 | context = &(drawctxt->base); |
| 1684 | |
| 1685 | /* |
| 1686 | * If preemption is disabled then everybody needs to go on the same |
| 1687 | * ringbuffer |
| 1688 | */ |
| 1689 | |
Harshdeep Dhatt | 38e57d7 | 2017-08-30 13:24:07 -0600 | [diff] [blame] | 1690 | if (!adreno_is_preemption_execution_enabled(adreno_dev)) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1691 | return &(adreno_dev->ringbuffers[0]); |
| 1692 | |
| 1693 | /* |
| 1694 | * Math to convert the priority field in context structure to an RB ID. |
| 1695 | * Divide up the context priority based on number of ringbuffer levels. |
| 1696 | */ |
| 1697 | level = context->priority / adreno_dev->num_ringbuffers; |
| 1698 | if (level < adreno_dev->num_ringbuffers) |
| 1699 | return &(adreno_dev->ringbuffers[level]); |
| 1700 | else |
| 1701 | return &(adreno_dev->ringbuffers[ |
| 1702 | adreno_dev->num_ringbuffers - 1]); |
| 1703 | } |
| 1704 | |
| 1705 | /* |
| 1706 | * adreno_compare_prio_level() - Compares 2 priority levels based on enum values |
| 1707 | * @p1: First priority level |
| 1708 | * @p2: Second priority level |
| 1709 | * |
| 1710 | * Returns greater than 0 if p1 is higher priority, 0 if levels are equal else |
| 1711 | * less than 0 |
| 1712 | */ |
| 1713 | static inline int adreno_compare_prio_level(int p1, int p2) |
| 1714 | { |
| 1715 | return p2 - p1; |
| 1716 | } |
| 1717 | |
| 1718 | void adreno_readreg64(struct adreno_device *adreno_dev, |
| 1719 | enum adreno_regs lo, enum adreno_regs hi, uint64_t *val); |
| 1720 | |
| 1721 | void adreno_writereg64(struct adreno_device *adreno_dev, |
| 1722 | enum adreno_regs lo, enum adreno_regs hi, uint64_t val); |
| 1723 | |
| 1724 | unsigned int adreno_get_rptr(struct adreno_ringbuffer *rb); |
| 1725 | |
| 1726 | static inline bool adreno_rb_empty(struct adreno_ringbuffer *rb) |
| 1727 | { |
| 1728 | return (adreno_get_rptr(rb) == rb->wptr); |
| 1729 | } |
| 1730 | |
| 1731 | static inline bool adreno_soft_fault_detect(struct adreno_device *adreno_dev) |
| 1732 | { |
| 1733 | return adreno_dev->fast_hang_detect && |
| 1734 | !test_bit(ADRENO_DEVICE_ISDB_ENABLED, &adreno_dev->priv); |
| 1735 | } |
| 1736 | |
| 1737 | static inline bool adreno_long_ib_detect(struct adreno_device *adreno_dev) |
| 1738 | { |
| 1739 | return adreno_dev->long_ib_detect && |
| 1740 | !test_bit(ADRENO_DEVICE_ISDB_ENABLED, &adreno_dev->priv); |
| 1741 | } |
| 1742 | |
| 1743 | /* |
| 1744 | * adreno_support_64bit() - Check the feature flag only if it is in |
| 1745 | * 64bit kernel otherwise return false |
| 1746 | * adreno_dev: The adreno device |
| 1747 | */ |
| 1748 | #if BITS_PER_LONG == 64 |
| 1749 | static inline bool adreno_support_64bit(struct adreno_device *adreno_dev) |
| 1750 | { |
| 1751 | return ADRENO_FEATURE(adreno_dev, ADRENO_64BIT); |
| 1752 | } |
| 1753 | #else |
| 1754 | static inline bool adreno_support_64bit(struct adreno_device *adreno_dev) |
| 1755 | { |
| 1756 | return false; |
| 1757 | } |
| 1758 | #endif /*BITS_PER_LONG*/ |
| 1759 | |
| 1760 | static inline void adreno_ringbuffer_set_global( |
| 1761 | struct adreno_device *adreno_dev, int name) |
| 1762 | { |
| 1763 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 1764 | |
| 1765 | kgsl_sharedmem_writel(device, |
| 1766 | &adreno_dev->ringbuffers[0].pagetable_desc, |
| 1767 | PT_INFO_OFFSET(current_global_ptname), name); |
| 1768 | } |
| 1769 | |
| 1770 | static inline void adreno_ringbuffer_set_pagetable(struct adreno_ringbuffer *rb, |
| 1771 | struct kgsl_pagetable *pt) |
| 1772 | { |
| 1773 | struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb); |
| 1774 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 1775 | unsigned long flags; |
| 1776 | |
| 1777 | spin_lock_irqsave(&rb->preempt_lock, flags); |
| 1778 | |
| 1779 | kgsl_sharedmem_writel(device, &rb->pagetable_desc, |
| 1780 | PT_INFO_OFFSET(current_rb_ptname), pt->name); |
| 1781 | |
| 1782 | kgsl_sharedmem_writeq(device, &rb->pagetable_desc, |
| 1783 | PT_INFO_OFFSET(ttbr0), kgsl_mmu_pagetable_get_ttbr0(pt)); |
| 1784 | |
| 1785 | kgsl_sharedmem_writel(device, &rb->pagetable_desc, |
| 1786 | PT_INFO_OFFSET(contextidr), |
| 1787 | kgsl_mmu_pagetable_get_contextidr(pt)); |
| 1788 | |
| 1789 | spin_unlock_irqrestore(&rb->preempt_lock, flags); |
| 1790 | } |
| 1791 | |
Abhilash Kumar | f1af104 | 2017-07-14 13:13:44 +0530 | [diff] [blame] | 1792 | static inline bool is_power_counter_overflow(struct adreno_device *adreno_dev, |
| 1793 | unsigned int reg, unsigned int prev_val, unsigned int *perfctr_pwr_hi) |
| 1794 | { |
| 1795 | unsigned int val; |
| 1796 | bool ret = false; |
| 1797 | |
| 1798 | /* |
| 1799 | * If prev_val is zero, it is first read after perf counter reset. |
| 1800 | * So set perfctr_pwr_hi register to zero. |
| 1801 | */ |
| 1802 | if (prev_val == 0) { |
| 1803 | *perfctr_pwr_hi = 0; |
| 1804 | return ret; |
| 1805 | } |
| 1806 | adreno_readreg(adreno_dev, ADRENO_REG_RBBM_PERFCTR_RBBM_0_HI, &val); |
| 1807 | if (val != *perfctr_pwr_hi) { |
| 1808 | *perfctr_pwr_hi = val; |
| 1809 | ret = true; |
| 1810 | } |
| 1811 | return ret; |
| 1812 | } |
| 1813 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1814 | static inline unsigned int counter_delta(struct kgsl_device *device, |
| 1815 | unsigned int reg, unsigned int *counter) |
| 1816 | { |
Abhilash Kumar | f1af104 | 2017-07-14 13:13:44 +0530 | [diff] [blame] | 1817 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1818 | unsigned int val; |
| 1819 | unsigned int ret = 0; |
Abhilash Kumar | f1af104 | 2017-07-14 13:13:44 +0530 | [diff] [blame] | 1820 | bool overflow = true; |
| 1821 | static unsigned int perfctr_pwr_hi; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1822 | |
| 1823 | /* Read the value */ |
| 1824 | kgsl_regread(device, reg, &val); |
| 1825 | |
Abhilash Kumar | f1af104 | 2017-07-14 13:13:44 +0530 | [diff] [blame] | 1826 | if (adreno_is_a5xx(adreno_dev) && reg == adreno_getreg |
| 1827 | (adreno_dev, ADRENO_REG_RBBM_PERFCTR_RBBM_0_LO)) |
| 1828 | overflow = is_power_counter_overflow(adreno_dev, reg, |
| 1829 | *counter, &perfctr_pwr_hi); |
| 1830 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1831 | /* Return 0 for the first read */ |
| 1832 | if (*counter != 0) { |
Abhilash Kumar | f1af104 | 2017-07-14 13:13:44 +0530 | [diff] [blame] | 1833 | if (val >= *counter) { |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1834 | ret = val - *counter; |
Abhilash Kumar | f1af104 | 2017-07-14 13:13:44 +0530 | [diff] [blame] | 1835 | } else if (overflow == true) { |
| 1836 | ret = (0xFFFFFFFF - *counter) + val; |
| 1837 | } else { |
| 1838 | /* |
| 1839 | * Since KGSL got abnormal value from the counter, |
| 1840 | * We will drop the value from being accumulated. |
| 1841 | */ |
| 1842 | pr_warn_once("KGSL: Abnormal value :0x%x (0x%x) from perf counter : 0x%x\n", |
| 1843 | val, *counter, reg); |
| 1844 | return 0; |
| 1845 | } |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1846 | } |
| 1847 | |
| 1848 | *counter = val; |
| 1849 | return ret; |
| 1850 | } |
Carter Cooper | 05f2a6b | 2017-03-20 11:43:11 -0600 | [diff] [blame] | 1851 | |
| 1852 | static inline int adreno_perfcntr_active_oob_get( |
| 1853 | struct adreno_device *adreno_dev) |
| 1854 | { |
| 1855 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1856 | int ret; |
| 1857 | |
| 1858 | ret = kgsl_active_count_get(KGSL_DEVICE(adreno_dev)); |
| 1859 | if (ret) |
| 1860 | return ret; |
| 1861 | |
| 1862 | if (gpudev->oob_set) { |
| 1863 | ret = gpudev->oob_set(adreno_dev, OOB_PERFCNTR_SET_MASK, |
| 1864 | OOB_PERFCNTR_CHECK_MASK, |
| 1865 | OOB_PERFCNTR_CLEAR_MASK); |
| 1866 | if (ret) |
| 1867 | kgsl_active_count_put(KGSL_DEVICE(adreno_dev)); |
| 1868 | } |
| 1869 | |
| 1870 | return ret; |
| 1871 | } |
| 1872 | |
| 1873 | static inline void adreno_perfcntr_active_oob_put( |
| 1874 | struct adreno_device *adreno_dev) |
| 1875 | { |
| 1876 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1877 | |
| 1878 | if (gpudev->oob_clear) |
| 1879 | gpudev->oob_clear(adreno_dev, OOB_PERFCNTR_CLEAR_MASK); |
| 1880 | |
| 1881 | kgsl_active_count_put(KGSL_DEVICE(adreno_dev)); |
| 1882 | } |
| 1883 | |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 1884 | static inline bool adreno_has_gbif(struct adreno_device *adreno_dev) |
| 1885 | { |
| 1886 | if (adreno_is_a615(adreno_dev)) |
| 1887 | return true; |
| 1888 | else |
| 1889 | return false; |
| 1890 | } |
| 1891 | |
| 1892 | /** |
| 1893 | * adreno_wait_for_vbif_halt_ack() - wait for VBIF acknowledgment |
| 1894 | * for given HALT request. |
| 1895 | * @ack_reg: register offset to wait for acknowledge |
| 1896 | */ |
| 1897 | static inline int adreno_wait_for_vbif_halt_ack(struct kgsl_device *device, |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 1898 | int ack_reg, unsigned int mask) |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 1899 | { |
| 1900 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 1901 | unsigned long wait_for_vbif; |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 1902 | unsigned int val; |
| 1903 | int ret = 0; |
| 1904 | |
| 1905 | /* wait for the transactions to clear */ |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 1906 | wait_for_vbif = jiffies + msecs_to_jiffies(VBIF_RESET_ACK_TIMEOUT); |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 1907 | while (1) { |
| 1908 | adreno_readreg(adreno_dev, ack_reg, |
| 1909 | &val); |
| 1910 | if ((val & mask) == mask) |
| 1911 | break; |
| 1912 | if (time_after(jiffies, wait_for_vbif)) { |
| 1913 | KGSL_DRV_ERR(device, |
| 1914 | "Wait limit reached for VBIF XIN Halt\n"); |
| 1915 | ret = -ETIMEDOUT; |
| 1916 | break; |
| 1917 | } |
| 1918 | } |
| 1919 | |
| 1920 | return ret; |
| 1921 | } |
| 1922 | |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1923 | /** |
| 1924 | * adreno_vbif_clear_pending_transactions() - Clear transactions in VBIF pipe |
| 1925 | * @device: Pointer to the device whose VBIF pipe is to be cleared |
| 1926 | */ |
| 1927 | static inline int adreno_vbif_clear_pending_transactions( |
| 1928 | struct kgsl_device *device) |
| 1929 | { |
| 1930 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 1931 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1932 | unsigned int mask = gpudev->vbif_xin_halt_ctrl0_mask; |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1933 | int ret = 0; |
| 1934 | |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 1935 | if (adreno_has_gbif(adreno_dev)) { |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 1936 | /* |
| 1937 | * Halt GBIF GX first and then CX part. |
| 1938 | * Need to release CX Halt explicitly in case of SW_RESET. |
| 1939 | * GX Halt release will be taken care by SW_RESET internally. |
| 1940 | */ |
| 1941 | adreno_writereg(adreno_dev, ADRENO_REG_RBBM_GPR0_CNTL, |
| 1942 | GBIF_HALT_REQUEST); |
| 1943 | ret = adreno_wait_for_vbif_halt_ack(device, |
| 1944 | ADRENO_REG_RBBM_VBIF_GX_RESET_STATUS, |
| 1945 | VBIF_RESET_ACK_MASK); |
| 1946 | if (ret) |
| 1947 | return ret; |
| 1948 | |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 1949 | adreno_writereg(adreno_dev, ADRENO_REG_GBIF_HALT, mask); |
| 1950 | ret = adreno_wait_for_vbif_halt_ack(device, |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 1951 | ADRENO_REG_GBIF_HALT_ACK, mask); |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 1952 | } else { |
| 1953 | adreno_writereg(adreno_dev, ADRENO_REG_VBIF_XIN_HALT_CTRL0, |
| 1954 | mask); |
| 1955 | ret = adreno_wait_for_vbif_halt_ack(device, |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 1956 | ADRENO_REG_VBIF_XIN_HALT_CTRL1, mask); |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 1957 | adreno_writereg(adreno_dev, ADRENO_REG_VBIF_XIN_HALT_CTRL0, 0); |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1958 | } |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1959 | return ret; |
| 1960 | } |
| 1961 | |
Harshdeep Dhatt | 8f78d5f | 2017-11-01 14:24:36 -0600 | [diff] [blame] | 1962 | void adreno_gmu_fenced_write(struct adreno_device *adreno_dev, |
| 1963 | enum adreno_regs offset, unsigned int val, |
| 1964 | unsigned int fence_mask); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1965 | #endif /*__ADRENO_H */ |