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Alan Coxda9bb1d2006-01-18 17:44:13 -08001#
2# EDAC Kconfig
Doug Thompson4577ca52009-04-02 16:58:43 -07003# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
Alan Coxda9bb1d2006-01-18 17:44:13 -08004# Licensed and distributed under the GPL
5#
Alan Coxda9bb1d2006-01-18 17:44:13 -08006
Jan Engelhardt751cb5e2007-07-15 23:39:27 -07007menuconfig EDAC
GeunSik Lime24aca62009-06-17 16:28:02 -07008 bool "EDAC (Error Detection And Correction) reporting"
Martin Schwidefskye25df122007-05-10 15:45:57 +02009 depends on HAS_IOMEM
Andrew Morton4c6a1c12007-07-26 10:41:10 -070010 depends on X86 || PPC
Alan Coxda9bb1d2006-01-18 17:44:13 -080011 help
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
Douglas Thompson8cb2a392007-07-19 01:50:12 -070014 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
Alan Coxda9bb1d2006-01-18 17:44:13 -080017
Tim Small57c432b2006-03-09 17:33:50 -080018 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
20
21 <http://bluesmoke.sourceforge.net/>
22
23 and:
24
25 <http://buttersideup.com/edacwiki>
26
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
29
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070030if EDAC
Alan Coxda9bb1d2006-01-18 17:44:13 -080031
32comment "Reporting subsystems"
Alan Coxda9bb1d2006-01-18 17:44:13 -080033
34config EDAC_DEBUG
35 bool "Debugging"
Alan Coxda9bb1d2006-01-18 17:44:13 -080036 help
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
41
Hitoshi Mitakecc18e3c2009-04-02 16:58:43 -070042config EDAC_DEBUG_VERBOSE
43 bool "More verbose debugging"
44 depends on EDAC_DEBUG
45 help
46 This option makes debugging information more verbose.
47 Source file name and line number where debugging message
48 printed will be added to debugging message.
49
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020050 config EDAC_DECODE_MCE
51 tristate "Decode MCEs in human-readable form (only on AMD for now)"
52 depends on CPU_SUP_AMD && X86_MCE
53 default y
54 ---help---
55 Enable this option if you want to decode Machine Check Exceptions
56 occuring on your machine in human-readable form.
57
58 You should definitely say Y here in case you want to decode MCEs
59 which occur really early upon boot, before the module infrastructure
60 has been initialized.
61
Alan Coxda9bb1d2006-01-18 17:44:13 -080062config EDAC_MM_EDAC
63 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
Alan Coxda9bb1d2006-01-18 17:44:13 -080064 help
65 Some systems are able to detect and correct errors in main
66 memory. EDAC can report statistics on memory error
67 detection and correction (EDAC - or commonly referred to ECC
68 errors). EDAC will also try to decode where these errors
69 occurred so that a particular failing memory module can be
70 replaced. If unsure, select 'Y'.
71
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -030072config EDAC_MCE
Mauro Carvalho Chehab963c5ba2009-07-09 22:04:30 -030073 bool
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -030074
Doug Thompson7d6034d2009-04-27 20:01:01 +020075config EDAC_AMD64
76 tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020077 depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
Doug Thompson7d6034d2009-04-27 20:01:01 +020078 help
Borislav Petkov3d373292009-05-20 20:18:46 +020079 Support for error detection and correction on the AMD 64
80 Families of Memory Controllers (K8, F10h and F11h)
Doug Thompson7d6034d2009-04-27 20:01:01 +020081
82config EDAC_AMD64_ERROR_INJECTION
83 bool "Sysfs Error Injection facilities"
84 depends on EDAC_AMD64
85 help
86 Recent Opterons (Family 10h and later) provide for Memory Error
87 Injection into the ECC detection circuits. The amd64_edac module
88 allows the operator/user to inject Uncorrectable and Correctable
89 errors into DRAM.
90
91 When enabled, in each of the respective memory controller directories
92 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
93
94 - inject_section (0..3, 16-byte section of 64-byte cacheline),
95 - inject_word (0..8, 16-bit word of 16-byte section),
96 - inject_ecc_vector (hex ecc vector: select bits of inject word)
97
98 In addition, there are two control files, inject_read and inject_write,
99 which trigger the DRAM ECC Read and Write respectively.
Alan Coxda9bb1d2006-01-18 17:44:13 -0800100
101config EDAC_AMD76X
102 tristate "AMD 76x (760, 762, 768)"
Dave Jones90cbc452006-02-03 03:04:11 -0800103 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800104 help
105 Support for error detection and correction on the AMD 76x
106 series of chipsets used with the Athlon processor.
107
108config EDAC_E7XXX
109 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800110 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800111 help
112 Support for error detection and correction on the Intel
113 E7205, E7500, E7501 and E7505 server chipsets.
114
115config EDAC_E752X
Andrei Konovalov5135b792008-04-29 01:03:13 -0700116 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
Randy Dunlapda960a62006-03-31 02:30:34 -0800117 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
Alan Coxda9bb1d2006-01-18 17:44:13 -0800118 help
119 Support for error detection and correction on the Intel
120 E7520, E7525, E7320 server chipsets.
121
Tim Small5a2c6752007-07-19 01:49:42 -0700122config EDAC_I82443BXGX
123 tristate "Intel 82443BX/GX (440BX/GX)"
124 depends on EDAC_MM_EDAC && PCI && X86_32
Andrew Morton28f96eea2007-07-19 01:49:45 -0700125 depends on BROKEN
Tim Small5a2c6752007-07-19 01:49:42 -0700126 help
127 Support for error detection and correction on the Intel
128 82443BX/GX memory controllers (440BX/GX chipsets).
129
Alan Coxda9bb1d2006-01-18 17:44:13 -0800130config EDAC_I82875P
131 tristate "Intel 82875p (D82875P, E7210)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800132 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800133 help
134 Support for error detection and correction on the Intel
135 DP82785P and E7210 server chipsets.
136
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700137config EDAC_I82975X
138 tristate "Intel 82975x (D82975x)"
139 depends on EDAC_MM_EDAC && PCI && X86
140 help
141 Support for error detection and correction on the Intel
142 DP82975x server chipsets.
143
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700144config EDAC_I3000
145 tristate "Intel 3000/3010"
Jason Uhlenkottf5c04542008-02-07 00:15:01 -0800146 depends on EDAC_MM_EDAC && PCI && X86
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700147 help
148 Support for error detection and correction on the Intel
149 3000 and 3010 server chipsets.
150
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700151config EDAC_I3200
152 tristate "Intel 3200"
153 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
154 help
155 Support for error detection and correction on the Intel
156 3200 and 3210 server chipsets.
157
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700158config EDAC_X38
159 tristate "Intel X38"
160 depends on EDAC_MM_EDAC && PCI && X86
161 help
162 Support for error detection and correction on the Intel
163 X38 server chipsets.
164
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800165config EDAC_I5400
166 tristate "Intel 5400 (Seaburg) chipsets"
167 depends on EDAC_MM_EDAC && PCI && X86
168 help
169 Support for error detection and correction the Intel
170 i5400 MCH chipset (Seaburg).
171
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300172config EDAC_I7CORE
173 tristate "Intel i7 Core (Nehalem) processors"
174 depends on EDAC_MM_EDAC && PCI && X86
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300175 select EDAC_MCE
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300176 help
177 Support for error detection and correction the Intel
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300178 i7 Core (Nehalem) Integrated Memory Controller that exists on
179 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
180 and Xeon 55xx processors.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300181
Alan Coxda9bb1d2006-01-18 17:44:13 -0800182config EDAC_I82860
183 tristate "Intel 82860"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800184 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800185 help
186 Support for error detection and correction on the Intel
187 82860 chipset.
188
189config EDAC_R82600
190 tristate "Radisys 82600 embedded chipset"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800191 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800192 help
193 Support for error detection and correction on the Radisys
194 82600 embedded chipset.
195
Eric Wolleseneb607052007-07-19 01:49:39 -0700196config EDAC_I5000
197 tristate "Intel Greencreek/Blackford chipset"
198 depends on EDAC_MM_EDAC && X86 && PCI
199 help
200 Support for error detection and correction the Intel
201 Greekcreek/Blackford chipsets.
202
Arthur Jones8f421c592008-07-25 01:49:04 -0700203config EDAC_I5100
204 tristate "Intel San Clemente MCH"
205 depends on EDAC_MM_EDAC && X86 && PCI
206 help
207 Support for error detection and correction the Intel
208 San Clemente MCH.
209
Dave Jianga9a753d2008-02-07 00:14:55 -0800210config EDAC_MPC85XX
Ira W. Snyderb4846252009-09-23 15:57:25 -0700211 tristate "Freescale MPC83xx / MPC85xx"
Anton Vorontsov1cd85212010-07-20 13:24:27 -0700212 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
Dave Jianga9a753d2008-02-07 00:14:55 -0800213 help
214 Support for error detection and correction on the Freescale
Ira W. Snyderb4846252009-09-23 15:57:25 -0700215 MPC8349, MPC8560, MPC8540, MPC8548
Dave Jianga9a753d2008-02-07 00:14:55 -0800216
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800217config EDAC_MV64X60
218 tristate "Marvell MV64x60"
219 depends on EDAC_MM_EDAC && MV64X60
220 help
221 Support for error detection and correction on the Marvell
222 MV64360 and MV64460 chipsets.
223
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700224config EDAC_PASEMI
225 tristate "PA Semi PWRficient"
226 depends on EDAC_MM_EDAC && PCI
Doug Thompsonddcc3052007-07-26 10:41:16 -0700227 depends on PPC_PASEMI
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700228 help
229 Support for error detection and correction on PA Semi
230 PWRficient.
231
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800232config EDAC_CELL
233 tristate "Cell Broadband Engine memory controller"
Benjamin Krilldef434c2008-11-27 16:15:44 +0100234 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800235 help
236 Support for error detection and correction on the
237 Cell Broadband Engine internal memory controller
238 on platform without a hypervisor
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700239
Grant Ericksondba7a772009-04-02 16:58:45 -0700240config EDAC_PPC4XX
241 tristate "PPC4xx IBM DDR2 Memory Controller"
242 depends on EDAC_MM_EDAC && 4xx
243 help
244 This enables support for EDAC on the ECC memory used
245 with the IBM DDR2 memory controller found in various
246 PowerPC 4xx embedded processors such as the 405EX[r],
247 440SP, 440SPe, 460EX, 460GT and 460SX.
248
Harry Ciaoe8765582009-04-02 16:58:51 -0700249config EDAC_AMD8131
250 tristate "AMD8131 HyperTransport PCI-X Tunnel"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700251 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciaoe8765582009-04-02 16:58:51 -0700252 help
253 Support for error detection and correction on the
254 AMD8131 HyperTransport PCI-X Tunnel chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700255 Note, add more Kconfig dependency if it's adopted
256 on some machine other than Maple.
Harry Ciaoe8765582009-04-02 16:58:51 -0700257
Harry Ciao58b4ce62009-04-02 16:58:51 -0700258config EDAC_AMD8111
259 tristate "AMD8111 HyperTransport I/O Hub"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700260 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciao58b4ce62009-04-02 16:58:51 -0700261 help
262 Support for error detection and correction on the
263 AMD8111 HyperTransport I/O Hub chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700264 Note, add more Kconfig dependency if it's adopted
265 on some machine other than Maple.
Harry Ciao58b4ce62009-04-02 16:58:51 -0700266
Harry Ciao2a9036a2009-06-17 16:27:58 -0700267config EDAC_CPC925
268 tristate "IBM CPC925 Memory Controller (PPC970FX)"
269 depends on EDAC_MM_EDAC && PPC64
270 help
271 Support for error detection and correction on the
272 IBM CPC925 Bridge and Memory Controller, which is
273 a companion chip to the PowerPC 970 family of
274 processors.
275
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700276endif # EDAC