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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Ralf Baechle70342282013-01-22 12:59:30 +01002 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
Ralf Baechlec539ef72012-01-11 15:37:16 +01007 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 2011 Wind River Systems,
9 * written by Ralf Baechle (ralf@linux-mips.org)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 */
Ralf Baechlec539ef72012-01-11 15:37:16 +010011#include <linux/bug.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/kernel.h>
13#include <linux/mm.h>
14#include <linux/bootmem.h>
Paul Gortmakercae39d12011-07-28 18:46:31 -040015#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/init.h>
17#include <linux/types.h>
18#include <linux/pci.h>
John Crispina48cf372012-05-04 10:50:13 +020019#include <linux/of_address.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
Ralf Baechlec539ef72012-01-11 15:37:16 +010021#include <asm/cpu-info.h>
22
Ralf Baechle982f6ff2009-09-17 02:25:07 +020023unsigned long PCIBIOS_MIN_IO;
Paul Burtonf8091a82016-10-05 18:18:11 +010024EXPORT_SYMBOL(PCIBIOS_MIN_IO);
25
Ralf Baechle982f6ff2009-09-17 02:25:07 +020026unsigned long PCIBIOS_MIN_MEM;
Paul Burtonf8091a82016-10-05 18:18:11 +010027EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Paul Burtonf474ba92016-10-05 18:18:09 +010029static int __init pcibios_set_cache_line_size(void)
Ralf Baechlec539ef72012-01-11 15:37:16 +010030{
31 struct cpuinfo_mips *c = &current_cpu_data;
32 unsigned int lsize;
33
34 /*
35 * Set PCI cacheline size to that of the highest level in the
36 * cache hierarchy.
37 */
38 lsize = c->dcache.linesz;
39 lsize = c->scache.linesz ? : lsize;
40 lsize = c->tcache.linesz ? : lsize;
41
42 BUG_ON(!lsize);
43
44 pci_dfl_cache_line_size = lsize >> 2;
45
46 pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
Paul Burtonf474ba92016-10-05 18:18:09 +010047 return 0;
Ralf Baechlec539ef72012-01-11 15:37:16 +010048}
Paul Burtonf474ba92016-10-05 18:18:09 +010049arch_initcall(pcibios_set_cache_line_size);
Ralf Baechlec539ef72012-01-11 15:37:16 +010050
Bjorn Helgaas8221a012016-06-17 14:43:34 -050051void pci_resource_to_user(const struct pci_dev *dev, int bar,
52 const struct resource *rsrc, resource_size_t *start,
53 resource_size_t *end)
54{
55 phys_addr_t size = resource_size(rsrc);
56
57 *start = fixup_bigphys_addr(rsrc->start, size);
58 *end = rsrc->start + size;
59}
60
Ralf Baechle98873f52008-12-09 17:58:46 +000061int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
62 enum pci_mmap_state mmap_state, int write_combine)
63{
64 unsigned long prot;
65
66 /*
67 * I/O space can be accessed via normal processor loads and stores on
68 * this platform but for now we elect not to do this and portable
69 * drivers should not do this anyway.
70 */
71 if (mmap_state == pci_mmap_io)
72 return -EINVAL;
73
74 /*
75 * Ignore write-combine; for now only return uncached mappings.
76 */
77 prot = pgprot_val(vma->vm_page_prot);
78 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
79 vma->vm_page_prot = __pgprot(prot);
80
81 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
82 vma->vm_end - vma->vm_start, vma->vm_page_prot);
83}