Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 1999 - 2010 Intel Corporation. |
| 3 | * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/sched.h> |
| 24 | #include <linux/pci.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/types.h> |
| 28 | #include <linux/errno.h> |
| 29 | #include <linux/netdevice.h> |
| 30 | #include <linux/skbuff.h> |
| 31 | #include <linux/can.h> |
| 32 | #include <linux/can/dev.h> |
| 33 | #include <linux/can/error.h> |
| 34 | |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 35 | #define PCH_ENABLE 1 /* The enable flag */ |
| 36 | #define PCH_DISABLE 0 /* The disable flag */ |
Tomoya | 0a80410 | 2010-11-17 14:06:25 +0000 | [diff] [blame] | 37 | #define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ |
| 38 | #define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ |
| 39 | #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) |
| 40 | #define PCH_CTRL_CCE BIT(6) |
| 41 | #define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ |
| 42 | #define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ |
| 43 | #define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ |
| 44 | |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 45 | #define PCH_CMASK_RX_TX_SET 0x00f3 |
| 46 | #define PCH_CMASK_RX_TX_GET 0x0073 |
| 47 | #define PCH_CMASK_ALL 0xff |
Tomoya | 0a80410 | 2010-11-17 14:06:25 +0000 | [diff] [blame] | 48 | #define PCH_CMASK_NEWDAT BIT(2) |
| 49 | #define PCH_CMASK_CLRINTPND BIT(3) |
| 50 | #define PCH_CMASK_CTRL BIT(4) |
| 51 | #define PCH_CMASK_ARB BIT(5) |
| 52 | #define PCH_CMASK_MASK BIT(6) |
| 53 | #define PCH_CMASK_RDWR BIT(7) |
| 54 | #define PCH_IF_MCONT_NEWDAT BIT(15) |
| 55 | #define PCH_IF_MCONT_MSGLOST BIT(14) |
| 56 | #define PCH_IF_MCONT_INTPND BIT(13) |
| 57 | #define PCH_IF_MCONT_UMASK BIT(12) |
| 58 | #define PCH_IF_MCONT_TXIE BIT(11) |
| 59 | #define PCH_IF_MCONT_RXIE BIT(10) |
| 60 | #define PCH_IF_MCONT_RMTEN BIT(9) |
| 61 | #define PCH_IF_MCONT_TXRQXT BIT(8) |
| 62 | #define PCH_IF_MCONT_EOB BIT(7) |
| 63 | #define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) |
| 64 | #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) |
| 65 | #define PCH_ID2_DIR BIT(13) |
| 66 | #define PCH_ID2_XTD BIT(14) |
| 67 | #define PCH_ID_MSGVAL BIT(15) |
| 68 | #define PCH_IF_CREQ_BUSY BIT(15) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 69 | |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 70 | #define PCH_STATUS_INT 0x8000 |
| 71 | #define PCH_REC 0x00007f00 |
| 72 | #define PCH_TEC 0x000000ff |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 73 | |
Tomoya | 0a80410 | 2010-11-17 14:06:25 +0000 | [diff] [blame] | 74 | #define PCH_TX_OK BIT(3) |
| 75 | #define PCH_RX_OK BIT(4) |
| 76 | #define PCH_EPASSIV BIT(5) |
| 77 | #define PCH_EWARN BIT(6) |
| 78 | #define PCH_BUS_OFF BIT(7) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 79 | |
| 80 | /* bit position of certain controller bits. */ |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 81 | #define PCH_BIT_BRP 0 |
| 82 | #define PCH_BIT_SJW 6 |
| 83 | #define PCH_BIT_TSEG1 8 |
| 84 | #define PCH_BIT_TSEG2 12 |
| 85 | #define PCH_BIT_BRPE_BRPE 6 |
| 86 | #define PCH_MSK_BITT_BRP 0x3f |
| 87 | #define PCH_MSK_BRPE_BRPE 0x3c0 |
| 88 | #define PCH_MSK_CTRL_IE_SIE_EIE 0x07 |
| 89 | #define PCH_COUNTER_LIMIT 10 |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 90 | |
| 91 | #define PCH_CAN_CLK 50000000 /* 50MHz */ |
| 92 | |
| 93 | /* Define the number of message object. |
| 94 | * PCH CAN communications are done via Message RAM. |
| 95 | * The Message RAM consists of 32 message objects. */ |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 96 | #define PCH_RX_OBJ_NUM 26 |
| 97 | #define PCH_TX_OBJ_NUM 6 |
| 98 | #define PCH_RX_OBJ_START 1 |
| 99 | #define PCH_RX_OBJ_END PCH_RX_OBJ_NUM |
| 100 | #define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) |
| 101 | #define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 102 | |
| 103 | #define PCH_FIFO_THRESH 16 |
| 104 | |
Tomoya | 76d94b2 | 2010-12-12 20:24:07 +0000 | [diff] [blame] | 105 | /* TxRqst2 show status of MsgObjNo.17~32 */ |
| 106 | #define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\ |
| 107 | (PCH_RX_OBJ_END - 16)) |
| 108 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 109 | enum pch_ifreg { |
| 110 | PCH_RX_IFREG, |
| 111 | PCH_TX_IFREG, |
| 112 | }; |
| 113 | |
Tomoya | d68f683 | 2010-11-29 18:16:15 +0000 | [diff] [blame] | 114 | enum pch_can_err { |
| 115 | PCH_STUF_ERR = 1, |
| 116 | PCH_FORM_ERR, |
| 117 | PCH_ACK_ERR, |
| 118 | PCH_BIT1_ERR, |
| 119 | PCH_BIT0_ERR, |
| 120 | PCH_CRC_ERR, |
| 121 | PCH_LEC_ALL, |
| 122 | }; |
| 123 | |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 124 | enum pch_can_mode { |
| 125 | PCH_CAN_ENABLE, |
| 126 | PCH_CAN_DISABLE, |
| 127 | PCH_CAN_ALL, |
| 128 | PCH_CAN_NONE, |
| 129 | PCH_CAN_STOP, |
| 130 | PCH_CAN_RUN |
| 131 | }; |
| 132 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 133 | struct pch_can_if_regs { |
| 134 | u32 creq; |
| 135 | u32 cmask; |
| 136 | u32 mask1; |
| 137 | u32 mask2; |
| 138 | u32 id1; |
| 139 | u32 id2; |
| 140 | u32 mcont; |
Tomoya | 8ac9702 | 2010-12-12 20:24:09 +0000 | [diff] [blame] | 141 | u32 data[4]; |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 142 | u32 rsv[13]; |
| 143 | }; |
| 144 | |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 145 | struct pch_can_regs { |
| 146 | u32 cont; |
| 147 | u32 stat; |
| 148 | u32 errc; |
| 149 | u32 bitt; |
| 150 | u32 intr; |
| 151 | u32 opt; |
| 152 | u32 brpe; |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 153 | u32 reserve; |
| 154 | struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ |
| 155 | u32 reserve1[8]; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 156 | u32 treq1; |
| 157 | u32 treq2; |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 158 | u32 reserve2[6]; |
| 159 | u32 data1; |
| 160 | u32 data2; |
| 161 | u32 reserve3[6]; |
| 162 | u32 canipend1; |
| 163 | u32 canipend2; |
| 164 | u32 reserve4[6]; |
| 165 | u32 canmval1; |
| 166 | u32 canmval2; |
| 167 | u32 reserve5[37]; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 168 | u32 srst; |
| 169 | }; |
| 170 | |
| 171 | struct pch_can_priv { |
| 172 | struct can_priv can; |
| 173 | unsigned int can_num; |
| 174 | struct pci_dev *dev; |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 175 | int tx_enable[PCH_TX_OBJ_END]; |
| 176 | int rx_enable[PCH_TX_OBJ_END]; |
| 177 | int rx_link[PCH_TX_OBJ_END]; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 178 | unsigned int int_enables; |
| 179 | unsigned int int_stat; |
| 180 | struct net_device *ndev; |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 181 | unsigned int msg_obj[PCH_TX_OBJ_END]; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 182 | struct pch_can_regs __iomem *regs; |
| 183 | struct napi_struct napi; |
| 184 | unsigned int tx_obj; /* Point next Tx Obj index */ |
| 185 | unsigned int use_msi; |
| 186 | }; |
| 187 | |
| 188 | static struct can_bittiming_const pch_can_bittiming_const = { |
| 189 | .name = KBUILD_MODNAME, |
| 190 | .tseg1_min = 1, |
| 191 | .tseg1_max = 16, |
| 192 | .tseg2_min = 1, |
| 193 | .tseg2_max = 8, |
| 194 | .sjw_max = 4, |
| 195 | .brp_min = 1, |
| 196 | .brp_max = 1024, /* 6bit + extended 4bit */ |
| 197 | .brp_inc = 1, |
| 198 | }; |
| 199 | |
| 200 | static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = { |
| 201 | {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, |
| 202 | {0,} |
| 203 | }; |
| 204 | MODULE_DEVICE_TABLE(pci, pch_pci_tbl); |
| 205 | |
Marc Kleine-Budde | 526de53 | 2010-10-30 16:27:48 -0700 | [diff] [blame] | 206 | static inline void pch_can_bit_set(void __iomem *addr, u32 mask) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 207 | { |
| 208 | iowrite32(ioread32(addr) | mask, addr); |
| 209 | } |
| 210 | |
Marc Kleine-Budde | 526de53 | 2010-10-30 16:27:48 -0700 | [diff] [blame] | 211 | static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 212 | { |
| 213 | iowrite32(ioread32(addr) & ~mask, addr); |
| 214 | } |
| 215 | |
| 216 | static void pch_can_set_run_mode(struct pch_can_priv *priv, |
| 217 | enum pch_can_mode mode) |
| 218 | { |
| 219 | switch (mode) { |
| 220 | case PCH_CAN_RUN: |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 221 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 222 | break; |
| 223 | |
| 224 | case PCH_CAN_STOP: |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 225 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 226 | break; |
| 227 | |
| 228 | default: |
| 229 | dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__); |
| 230 | break; |
| 231 | } |
| 232 | } |
| 233 | |
| 234 | static void pch_can_set_optmode(struct pch_can_priv *priv) |
| 235 | { |
| 236 | u32 reg_val = ioread32(&priv->regs->opt); |
| 237 | |
| 238 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 239 | reg_val |= PCH_OPT_SILENT; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 240 | |
| 241 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 242 | reg_val |= PCH_OPT_LBACK; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 243 | |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 244 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 245 | iowrite32(reg_val, &priv->regs->opt); |
| 246 | } |
| 247 | |
| 248 | static void pch_can_set_int_custom(struct pch_can_priv *priv) |
| 249 | { |
| 250 | /* Clearing the IE, SIE and EIE bits of Can control register. */ |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 251 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 252 | |
| 253 | /* Appropriately setting them. */ |
| 254 | pch_can_bit_set(&priv->regs->cont, |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 255 | ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | /* This function retrieves interrupt enabled for the CAN device. */ |
| 259 | static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables) |
| 260 | { |
| 261 | /* Obtaining the status of IE, SIE and EIE interrupt bits. */ |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 262 | *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | static void pch_can_set_int_enables(struct pch_can_priv *priv, |
| 266 | enum pch_can_mode interrupt_no) |
| 267 | { |
| 268 | switch (interrupt_no) { |
| 269 | case PCH_CAN_ENABLE: |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 270 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 271 | break; |
| 272 | |
| 273 | case PCH_CAN_DISABLE: |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 274 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 275 | break; |
| 276 | |
| 277 | case PCH_CAN_ALL: |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 278 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 279 | break; |
| 280 | |
| 281 | case PCH_CAN_NONE: |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 282 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 283 | break; |
| 284 | |
| 285 | default: |
| 286 | dev_err(&priv->ndev->dev, "Invalid interrupt number.\n"); |
| 287 | break; |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) |
| 292 | { |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 293 | u32 counter = PCH_COUNTER_LIMIT; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 294 | u32 ifx_creq; |
| 295 | |
| 296 | iowrite32(num, creq_addr); |
| 297 | while (counter) { |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 298 | ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 299 | if (!ifx_creq) |
| 300 | break; |
| 301 | counter--; |
| 302 | udelay(1); |
| 303 | } |
| 304 | if (!counter) |
| 305 | pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); |
| 306 | } |
| 307 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 308 | static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, |
| 309 | u32 set, enum pch_ifreg dir) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 310 | { |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 311 | u32 ie; |
| 312 | |
| 313 | if (dir) |
| 314 | ie = PCH_IF_MCONT_TXIE; |
| 315 | else |
| 316 | ie = PCH_IF_MCONT_RXIE; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 317 | |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 318 | /* Reading the receive buffer data from RAM to Interface1 registers */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 319 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); |
| 320 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 321 | |
| 322 | /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */ |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 323 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 324 | &priv->regs->ifregs[dir].cmask); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 325 | |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 326 | if (set == PCH_ENABLE) { |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 327 | /* Setting the MsgVal and RxIE bits */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 328 | pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); |
| 329 | pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 330 | |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 331 | } else if (set == PCH_DISABLE) { |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 332 | /* Resetting the MsgVal and RxIE bits */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 333 | pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); |
| 334 | pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 335 | } |
| 336 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 337 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 338 | } |
| 339 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 340 | static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 341 | { |
| 342 | int i; |
| 343 | |
| 344 | /* Traversing to obtain the object configured as receivers. */ |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 345 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) |
| 346 | pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 347 | } |
| 348 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 349 | static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 350 | { |
| 351 | int i; |
| 352 | |
| 353 | /* Traversing to obtain the object configured as transmit object. */ |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 354 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
| 355 | pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 356 | } |
| 357 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 358 | static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, |
| 359 | enum pch_ifreg dir) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 360 | { |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 361 | u32 ie, enable; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 362 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 363 | if (dir) |
| 364 | ie = PCH_IF_MCONT_RXIE; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 365 | else |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 366 | ie = PCH_IF_MCONT_TXIE; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 367 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 368 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); |
| 369 | pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 370 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 371 | if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && |
| 372 | ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) { |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 373 | enable = 1; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 374 | } else { |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 375 | enable = 0; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 376 | } |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 377 | return enable; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 378 | } |
| 379 | |
| 380 | static int pch_can_int_pending(struct pch_can_priv *priv) |
| 381 | { |
| 382 | return ioread32(&priv->regs->intr) & 0xffff; |
| 383 | } |
| 384 | |
| 385 | static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, |
| 386 | u32 buffer_num, u32 set) |
| 387 | { |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 388 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
| 389 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); |
| 390 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, |
| 391 | &priv->regs->ifregs[0].cmask); |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 392 | if (set == PCH_ENABLE) |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 393 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, |
| 394 | PCH_IF_MCONT_EOB); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 395 | else |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 396 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 397 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 398 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 399 | } |
| 400 | |
| 401 | static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, |
| 402 | u32 buffer_num, u32 *link) |
| 403 | { |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 404 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
| 405 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 406 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 407 | if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 408 | *link = PCH_DISABLE; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 409 | else |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 410 | *link = PCH_ENABLE; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 411 | } |
| 412 | |
| 413 | static void pch_can_clear_buffers(struct pch_can_priv *priv) |
| 414 | { |
| 415 | int i; |
| 416 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 417 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 418 | iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); |
| 419 | iowrite32(0xffff, &priv->regs->ifregs[0].mask1); |
| 420 | iowrite32(0xffff, &priv->regs->ifregs[0].mask2); |
| 421 | iowrite32(0x0, &priv->regs->ifregs[0].id1); |
| 422 | iowrite32(0x0, &priv->regs->ifregs[0].id2); |
| 423 | iowrite32(0x0, &priv->regs->ifregs[0].mcont); |
Tomoya | 8ac9702 | 2010-12-12 20:24:09 +0000 | [diff] [blame] | 424 | iowrite32(0x0, &priv->regs->ifregs[0].data[0]); |
| 425 | iowrite32(0x0, &priv->regs->ifregs[0].data[1]); |
| 426 | iowrite32(0x0, &priv->regs->ifregs[0].data[2]); |
| 427 | iowrite32(0x0, &priv->regs->ifregs[0].data[3]); |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 428 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | |
| 429 | PCH_CMASK_ARB | PCH_CMASK_CTRL, |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 430 | &priv->regs->ifregs[0].cmask); |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 431 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 432 | } |
| 433 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 434 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 435 | iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask); |
| 436 | iowrite32(0xffff, &priv->regs->ifregs[1].mask1); |
| 437 | iowrite32(0xffff, &priv->regs->ifregs[1].mask2); |
| 438 | iowrite32(0x0, &priv->regs->ifregs[1].id1); |
| 439 | iowrite32(0x0, &priv->regs->ifregs[1].id2); |
| 440 | iowrite32(0x0, &priv->regs->ifregs[1].mcont); |
Tomoya | 8ac9702 | 2010-12-12 20:24:09 +0000 | [diff] [blame] | 441 | iowrite32(0x0, &priv->regs->ifregs[1].data[0]); |
| 442 | iowrite32(0x0, &priv->regs->ifregs[1].data[1]); |
| 443 | iowrite32(0x0, &priv->regs->ifregs[1].data[2]); |
| 444 | iowrite32(0x0, &priv->regs->ifregs[1].data[3]); |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 445 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | |
| 446 | PCH_CMASK_ARB | PCH_CMASK_CTRL, |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 447 | &priv->regs->ifregs[1].cmask); |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 448 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 449 | } |
| 450 | } |
| 451 | |
| 452 | static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) |
| 453 | { |
| 454 | int i; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 455 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 456 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
| 457 | iowrite32(PCH_CMASK_RX_TX_GET, |
| 458 | &priv->regs->ifregs[0].cmask); |
| 459 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 460 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 461 | iowrite32(0x0, &priv->regs->ifregs[0].id1); |
| 462 | iowrite32(0x0, &priv->regs->ifregs[0].id2); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 463 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 464 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, |
| 465 | PCH_IF_MCONT_UMASK); |
| 466 | |
| 467 | /* Set FIFO mode set to 0 except last Rx Obj*/ |
| 468 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, |
| 469 | PCH_IF_MCONT_EOB); |
| 470 | /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ |
| 471 | if (i == PCH_RX_OBJ_END) |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 472 | pch_can_bit_set(&priv->regs->ifregs[0].mcont, |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 473 | PCH_IF_MCONT_EOB); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 474 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 475 | iowrite32(0, &priv->regs->ifregs[0].mask1); |
| 476 | pch_can_bit_clear(&priv->regs->ifregs[0].mask2, |
| 477 | 0x1fff | PCH_MASK2_MDIR_MXTD); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 478 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 479 | /* Setting CMASK for writing */ |
| 480 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | |
| 481 | PCH_CMASK_ARB | PCH_CMASK_CTRL, |
| 482 | &priv->regs->ifregs[0].cmask); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 483 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 484 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); |
| 485 | } |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 486 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 487 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { |
| 488 | iowrite32(PCH_CMASK_RX_TX_GET, |
| 489 | &priv->regs->ifregs[1].cmask); |
| 490 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 491 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 492 | /* Resetting DIR bit for reception */ |
| 493 | iowrite32(0x0, &priv->regs->ifregs[1].id1); |
| 494 | iowrite32(0x0, &priv->regs->ifregs[1].id2); |
| 495 | pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 496 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 497 | /* Setting EOB bit for transmitter */ |
| 498 | iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 499 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 500 | pch_can_bit_set(&priv->regs->ifregs[1].mcont, |
| 501 | PCH_IF_MCONT_UMASK); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 502 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 503 | iowrite32(0, &priv->regs->ifregs[1].mask1); |
| 504 | pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 505 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 506 | /* Setting CMASK for writing */ |
| 507 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | |
| 508 | PCH_CMASK_ARB | PCH_CMASK_CTRL, |
| 509 | &priv->regs->ifregs[1].cmask); |
| 510 | |
| 511 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 512 | } |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 513 | } |
| 514 | |
| 515 | static void pch_can_init(struct pch_can_priv *priv) |
| 516 | { |
| 517 | /* Stopping the Can device. */ |
| 518 | pch_can_set_run_mode(priv, PCH_CAN_STOP); |
| 519 | |
| 520 | /* Clearing all the message object buffers. */ |
| 521 | pch_can_clear_buffers(priv); |
| 522 | |
| 523 | /* Configuring the respective message object as either rx/tx object. */ |
| 524 | pch_can_config_rx_tx_buffers(priv); |
| 525 | |
| 526 | /* Enabling the interrupts. */ |
| 527 | pch_can_set_int_enables(priv, PCH_CAN_ALL); |
| 528 | } |
| 529 | |
| 530 | static void pch_can_release(struct pch_can_priv *priv) |
| 531 | { |
| 532 | /* Stooping the CAN device. */ |
| 533 | pch_can_set_run_mode(priv, PCH_CAN_STOP); |
| 534 | |
| 535 | /* Disabling the interrupts. */ |
| 536 | pch_can_set_int_enables(priv, PCH_CAN_NONE); |
| 537 | |
| 538 | /* Disabling all the receive object. */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 539 | pch_can_set_rx_all(priv, 0); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 540 | |
| 541 | /* Disabling all the transmit object. */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 542 | pch_can_set_tx_all(priv, 0); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 543 | } |
| 544 | |
| 545 | /* This function clears interrupt(s) from the CAN device. */ |
| 546 | static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) |
| 547 | { |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 548 | if (mask == PCH_STATUS_INT) { |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 549 | ioread32(&priv->regs->stat); |
| 550 | return; |
| 551 | } |
| 552 | |
| 553 | /* Clear interrupt for transmit object */ |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 554 | if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { |
| 555 | /* Setting CMASK for clearing the reception interrupts. */ |
| 556 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, |
| 557 | &priv->regs->ifregs[0].cmask); |
| 558 | |
| 559 | /* Clearing the Dir bit. */ |
| 560 | pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); |
| 561 | |
| 562 | /* Clearing NewDat & IntPnd */ |
| 563 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, |
| 564 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); |
| 565 | |
| 566 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask); |
| 567 | } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 568 | /* Setting CMASK for clearing interrupts for |
| 569 | frame transmission. */ |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 570 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 571 | &priv->regs->ifregs[1].cmask); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 572 | |
| 573 | /* Resetting the ID registers. */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 574 | pch_can_bit_set(&priv->regs->ifregs[1].id2, |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 575 | PCH_ID2_DIR | (0x7ff << 2)); |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 576 | iowrite32(0x0, &priv->regs->ifregs[1].id1); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 577 | |
| 578 | /* Claring NewDat, TxRqst & IntPnd */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 579 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 580 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | |
| 581 | PCH_IF_MCONT_TXRQXT); |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 582 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 583 | } |
| 584 | } |
| 585 | |
| 586 | static int pch_can_get_buffer_status(struct pch_can_priv *priv) |
| 587 | { |
| 588 | return (ioread32(&priv->regs->treq1) & 0xffff) | |
| 589 | ((ioread32(&priv->regs->treq2) & 0xffff) << 16); |
| 590 | } |
| 591 | |
| 592 | static void pch_can_reset(struct pch_can_priv *priv) |
| 593 | { |
| 594 | /* write to sw reset register */ |
| 595 | iowrite32(1, &priv->regs->srst); |
| 596 | iowrite32(0, &priv->regs->srst); |
| 597 | } |
| 598 | |
| 599 | static void pch_can_error(struct net_device *ndev, u32 status) |
| 600 | { |
| 601 | struct sk_buff *skb; |
| 602 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 603 | struct can_frame *cf; |
Tomoya | d68f683 | 2010-11-29 18:16:15 +0000 | [diff] [blame] | 604 | u32 errc, lec; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 605 | struct net_device_stats *stats = &(priv->ndev->stats); |
| 606 | enum can_state state = priv->can.state; |
| 607 | |
| 608 | skb = alloc_can_err_skb(ndev, &cf); |
| 609 | if (!skb) |
| 610 | return; |
| 611 | |
| 612 | if (status & PCH_BUS_OFF) { |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 613 | pch_can_set_tx_all(priv, 0); |
| 614 | pch_can_set_rx_all(priv, 0); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 615 | state = CAN_STATE_BUS_OFF; |
| 616 | cf->can_id |= CAN_ERR_BUSOFF; |
| 617 | can_bus_off(ndev); |
| 618 | pch_can_set_run_mode(priv, PCH_CAN_RUN); |
| 619 | dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); |
| 620 | } |
| 621 | |
| 622 | /* Warning interrupt. */ |
| 623 | if (status & PCH_EWARN) { |
| 624 | state = CAN_STATE_ERROR_WARNING; |
| 625 | priv->can.can_stats.error_warning++; |
| 626 | cf->can_id |= CAN_ERR_CRTL; |
| 627 | errc = ioread32(&priv->regs->errc); |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 628 | if (((errc & PCH_REC) >> 8) > 96) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 629 | cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 630 | if ((errc & PCH_TEC) > 96) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 631 | cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; |
| 632 | dev_warn(&ndev->dev, |
| 633 | "%s -> Error Counter is more than 96.\n", __func__); |
| 634 | } |
| 635 | /* Error passive interrupt. */ |
| 636 | if (status & PCH_EPASSIV) { |
| 637 | priv->can.can_stats.error_passive++; |
| 638 | state = CAN_STATE_ERROR_PASSIVE; |
| 639 | cf->can_id |= CAN_ERR_CRTL; |
| 640 | errc = ioread32(&priv->regs->errc); |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 641 | if (((errc & PCH_REC) >> 8) > 127) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 642 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 643 | if ((errc & PCH_TEC) > 127) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 644 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; |
| 645 | dev_err(&ndev->dev, |
| 646 | "%s -> CAN controller is ERROR PASSIVE .\n", __func__); |
| 647 | } |
| 648 | |
Tomoya | d68f683 | 2010-11-29 18:16:15 +0000 | [diff] [blame] | 649 | lec = status & PCH_LEC_ALL; |
| 650 | switch (lec) { |
| 651 | case PCH_STUF_ERR: |
| 652 | cf->data[2] |= CAN_ERR_PROT_STUFF; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 653 | priv->can.can_stats.bus_error++; |
| 654 | stats->rx_errors++; |
Tomoya | d68f683 | 2010-11-29 18:16:15 +0000 | [diff] [blame] | 655 | break; |
| 656 | case PCH_FORM_ERR: |
| 657 | cf->data[2] |= CAN_ERR_PROT_FORM; |
| 658 | priv->can.can_stats.bus_error++; |
| 659 | stats->rx_errors++; |
| 660 | break; |
| 661 | case PCH_ACK_ERR: |
| 662 | cf->can_id |= CAN_ERR_ACK; |
| 663 | priv->can.can_stats.bus_error++; |
| 664 | stats->rx_errors++; |
| 665 | break; |
| 666 | case PCH_BIT1_ERR: |
| 667 | case PCH_BIT0_ERR: |
| 668 | cf->data[2] |= CAN_ERR_PROT_BIT; |
| 669 | priv->can.can_stats.bus_error++; |
| 670 | stats->rx_errors++; |
| 671 | break; |
| 672 | case PCH_CRC_ERR: |
| 673 | cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | |
| 674 | CAN_ERR_PROT_LOC_CRC_DEL; |
| 675 | priv->can.can_stats.bus_error++; |
| 676 | stats->rx_errors++; |
| 677 | break; |
| 678 | case PCH_LEC_ALL: /* Written by CPU. No error status */ |
| 679 | break; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 680 | } |
| 681 | |
| 682 | priv->can.state = state; |
| 683 | netif_rx(skb); |
| 684 | |
| 685 | stats->rx_packets++; |
| 686 | stats->rx_bytes += cf->can_dlc; |
| 687 | } |
| 688 | |
| 689 | static irqreturn_t pch_can_interrupt(int irq, void *dev_id) |
| 690 | { |
| 691 | struct net_device *ndev = (struct net_device *)dev_id; |
| 692 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 693 | |
| 694 | pch_can_set_int_enables(priv, PCH_CAN_NONE); |
| 695 | |
| 696 | napi_schedule(&priv->napi); |
| 697 | |
| 698 | return IRQ_HANDLED; |
| 699 | } |
| 700 | |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 701 | static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id) |
| 702 | { |
| 703 | if (obj_id < PCH_FIFO_THRESH) { |
| 704 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | |
| 705 | PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); |
| 706 | |
| 707 | /* Clearing the Dir bit. */ |
| 708 | pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); |
| 709 | |
| 710 | /* Clearing NewDat & IntPnd */ |
| 711 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, |
| 712 | PCH_IF_MCONT_INTPND); |
| 713 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id); |
| 714 | } else if (obj_id > PCH_FIFO_THRESH) { |
| 715 | pch_can_int_clr(priv, obj_id); |
| 716 | } else if (obj_id == PCH_FIFO_THRESH) { |
| 717 | int cnt; |
| 718 | for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) |
| 719 | pch_can_int_clr(priv, cnt + 1); |
| 720 | } |
| 721 | } |
| 722 | |
| 723 | static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id) |
| 724 | { |
| 725 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 726 | struct net_device_stats *stats = &(priv->ndev->stats); |
| 727 | struct sk_buff *skb; |
| 728 | struct can_frame *cf; |
| 729 | |
| 730 | netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n"); |
| 731 | pch_can_bit_clear(&priv->regs->ifregs[0].mcont, |
| 732 | PCH_IF_MCONT_MSGLOST); |
| 733 | iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, |
| 734 | &priv->regs->ifregs[0].cmask); |
| 735 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id); |
| 736 | |
| 737 | skb = alloc_can_err_skb(ndev, &cf); |
| 738 | if (!skb) |
| 739 | return; |
| 740 | |
| 741 | cf->can_id |= CAN_ERR_CRTL; |
| 742 | cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; |
| 743 | stats->rx_over_errors++; |
| 744 | stats->rx_errors++; |
| 745 | |
| 746 | netif_receive_skb(skb); |
| 747 | } |
| 748 | |
| 749 | static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 750 | { |
| 751 | u32 reg; |
| 752 | canid_t id; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 753 | int rcv_pkts = 0; |
| 754 | struct sk_buff *skb; |
| 755 | struct can_frame *cf; |
| 756 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 757 | struct net_device_stats *stats = &(priv->ndev->stats); |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 758 | int i; |
| 759 | u32 id2; |
Tomoya | 8ac9702 | 2010-12-12 20:24:09 +0000 | [diff] [blame] | 760 | u16 data_reg; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 761 | |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 762 | do { |
| 763 | /* Reading the messsage object from the Message RAM */ |
| 764 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); |
| 765 | pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_num); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 766 | |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 767 | /* Reading the MCONT register. */ |
| 768 | reg = ioread32(&priv->regs->ifregs[0].mcont); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 769 | |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 770 | if (reg & PCH_IF_MCONT_EOB) |
| 771 | break; |
| 772 | |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 773 | /* If MsgLost bit set. */ |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 774 | if (reg & PCH_IF_MCONT_MSGLOST) { |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 775 | pch_can_rx_msg_lost(ndev, obj_num); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 776 | rcv_pkts++; |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 777 | quota--; |
| 778 | obj_num++; |
| 779 | continue; |
| 780 | } else if (!(reg & PCH_IF_MCONT_NEWDAT)) { |
| 781 | obj_num++; |
| 782 | continue; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 783 | } |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 784 | |
| 785 | skb = alloc_can_skb(priv->ndev, &cf); |
| 786 | if (!skb) |
| 787 | return -ENOMEM; |
| 788 | |
| 789 | /* Get Received data */ |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 790 | id2 = ioread32(&priv->regs->ifregs[0].id2); |
| 791 | if (id2 & PCH_ID2_XTD) { |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 792 | id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 793 | id |= (((id2) & 0x1fff) << 16); |
| 794 | cf->can_id = id | CAN_EFF_FLAG; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 795 | } else { |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 796 | id = (id2 >> 2) & CAN_SFF_MASK; |
| 797 | cf->can_id = id; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 798 | } |
| 799 | |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 800 | if (id2 & PCH_ID2_DIR) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 801 | cf->can_id |= CAN_RTR_FLAG; |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 802 | |
| 803 | cf->can_dlc = get_can_dlc((ioread32(&priv->regs-> |
| 804 | ifregs[0].mcont)) & 0xF); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 805 | |
Tomoya | 8ac9702 | 2010-12-12 20:24:09 +0000 | [diff] [blame] | 806 | for (i = 0; i < cf->can_dlc; i += 2) { |
| 807 | data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]); |
| 808 | cf->data[i] = data_reg; |
| 809 | cf->data[i + 1] = data_reg >> 8; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 810 | } |
| 811 | |
| 812 | netif_receive_skb(skb); |
| 813 | rcv_pkts++; |
| 814 | stats->rx_packets++; |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 815 | quota--; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 816 | stats->rx_bytes += cf->can_dlc; |
| 817 | |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 818 | pch_fifo_thresh(priv, obj_num); |
| 819 | obj_num++; |
| 820 | } while (quota > 0); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 821 | |
| 822 | return rcv_pkts; |
| 823 | } |
Tomoya | e489cce | 2010-12-12 20:24:08 +0000 | [diff] [blame] | 824 | |
| 825 | static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat) |
| 826 | { |
| 827 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 828 | struct net_device_stats *stats = &(priv->ndev->stats); |
| 829 | u32 dlc; |
| 830 | |
| 831 | can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); |
| 832 | iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, |
| 833 | &priv->regs->ifregs[1].cmask); |
| 834 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat); |
| 835 | dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) & |
| 836 | PCH_IF_MCONT_DLC); |
| 837 | stats->tx_bytes += dlc; |
| 838 | stats->tx_packets++; |
| 839 | if (int_stat == PCH_TX_OBJ_END) |
| 840 | netif_wake_queue(ndev); |
| 841 | } |
| 842 | |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 843 | static int pch_can_rx_poll(struct napi_struct *napi, int quota) |
| 844 | { |
| 845 | struct net_device *ndev = napi->dev; |
| 846 | struct pch_can_priv *priv = netdev_priv(ndev); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 847 | u32 int_stat; |
| 848 | int rcv_pkts = 0; |
| 849 | u32 reg_stat; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 850 | |
| 851 | int_stat = pch_can_int_pending(priv); |
| 852 | if (!int_stat) |
Tomoya | e489cce | 2010-12-12 20:24:08 +0000 | [diff] [blame] | 853 | goto end; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 854 | |
Tomoya | e489cce | 2010-12-12 20:24:08 +0000 | [diff] [blame] | 855 | if ((int_stat == PCH_STATUS_INT) && (quota > 0)) { |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 856 | reg_stat = ioread32(&priv->regs->stat); |
| 857 | if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { |
Tomoya | e489cce | 2010-12-12 20:24:08 +0000 | [diff] [blame] | 858 | if (reg_stat & PCH_BUS_OFF || |
| 859 | (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) { |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 860 | pch_can_error(ndev, reg_stat); |
Tomoya | e489cce | 2010-12-12 20:24:08 +0000 | [diff] [blame] | 861 | quota--; |
| 862 | } |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 863 | } |
| 864 | |
Tomoya | e489cce | 2010-12-12 20:24:08 +0000 | [diff] [blame] | 865 | if (reg_stat & PCH_TX_OK) |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 866 | pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 867 | |
| 868 | if (reg_stat & PCH_RX_OK) |
| 869 | pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK); |
| 870 | |
| 871 | int_stat = pch_can_int_pending(priv); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 872 | } |
| 873 | |
Tomoya | e489cce | 2010-12-12 20:24:08 +0000 | [diff] [blame] | 874 | if (quota == 0) |
| 875 | goto end; |
| 876 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 877 | if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { |
Tomoya | 1d5b4b2 | 2010-12-12 20:24:10 +0000 | [diff] [blame^] | 878 | rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota); |
Tomoya | e489cce | 2010-12-12 20:24:08 +0000 | [diff] [blame] | 879 | quota -= rcv_pkts; |
| 880 | if (quota < 0) |
| 881 | goto end; |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 882 | } else if ((int_stat >= PCH_TX_OBJ_START) && |
| 883 | (int_stat <= PCH_TX_OBJ_END)) { |
| 884 | /* Handle transmission interrupt */ |
Tomoya | e489cce | 2010-12-12 20:24:08 +0000 | [diff] [blame] | 885 | pch_can_tx_complete(ndev, int_stat); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 886 | } |
| 887 | |
Tomoya | e489cce | 2010-12-12 20:24:08 +0000 | [diff] [blame] | 888 | end: |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 889 | napi_complete(napi); |
| 890 | pch_can_set_int_enables(priv, PCH_CAN_ALL); |
| 891 | |
| 892 | return rcv_pkts; |
| 893 | } |
| 894 | |
| 895 | static int pch_set_bittiming(struct net_device *ndev) |
| 896 | { |
| 897 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 898 | const struct can_bittiming *bt = &priv->can.bittiming; |
| 899 | u32 canbit; |
| 900 | u32 bepe; |
| 901 | u32 brp; |
| 902 | |
| 903 | /* Setting the CCE bit for accessing the Can Timing register. */ |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 904 | pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 905 | |
| 906 | brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1; |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 907 | canbit = brp & PCH_MSK_BITT_BRP; |
| 908 | canbit |= (bt->sjw - 1) << PCH_BIT_SJW; |
| 909 | canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1; |
| 910 | canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2; |
| 911 | bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 912 | iowrite32(canbit, &priv->regs->bitt); |
| 913 | iowrite32(bepe, &priv->regs->brpe); |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 914 | pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 915 | |
| 916 | return 0; |
| 917 | } |
| 918 | |
| 919 | static void pch_can_start(struct net_device *ndev) |
| 920 | { |
| 921 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 922 | |
| 923 | if (priv->can.state != CAN_STATE_STOPPED) |
| 924 | pch_can_reset(priv); |
| 925 | |
| 926 | pch_set_bittiming(ndev); |
| 927 | pch_can_set_optmode(priv); |
| 928 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 929 | pch_can_set_tx_all(priv, 1); |
| 930 | pch_can_set_rx_all(priv, 1); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 931 | |
| 932 | /* Setting the CAN to run mode. */ |
| 933 | pch_can_set_run_mode(priv, PCH_CAN_RUN); |
| 934 | |
| 935 | priv->can.state = CAN_STATE_ERROR_ACTIVE; |
| 936 | |
| 937 | return; |
| 938 | } |
| 939 | |
| 940 | static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) |
| 941 | { |
| 942 | int ret = 0; |
| 943 | |
| 944 | switch (mode) { |
| 945 | case CAN_MODE_START: |
| 946 | pch_can_start(ndev); |
| 947 | netif_wake_queue(ndev); |
| 948 | break; |
| 949 | default: |
| 950 | ret = -EOPNOTSUPP; |
| 951 | break; |
| 952 | } |
| 953 | |
| 954 | return ret; |
| 955 | } |
| 956 | |
| 957 | static int pch_can_open(struct net_device *ndev) |
| 958 | { |
| 959 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 960 | int retval; |
| 961 | |
| 962 | retval = pci_enable_msi(priv->dev); |
| 963 | if (retval) { |
| 964 | dev_info(&ndev->dev, "PCH CAN opened without MSI\n"); |
| 965 | priv->use_msi = 0; |
| 966 | } else { |
| 967 | dev_info(&ndev->dev, "PCH CAN opened with MSI\n"); |
| 968 | priv->use_msi = 1; |
| 969 | } |
| 970 | |
| 971 | /* Regsitering the interrupt. */ |
| 972 | retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, |
| 973 | ndev->name, ndev); |
| 974 | if (retval) { |
| 975 | dev_err(&ndev->dev, "request_irq failed.\n"); |
| 976 | goto req_irq_err; |
| 977 | } |
| 978 | |
| 979 | /* Open common can device */ |
| 980 | retval = open_candev(ndev); |
| 981 | if (retval) { |
| 982 | dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval); |
| 983 | goto err_open_candev; |
| 984 | } |
| 985 | |
| 986 | pch_can_init(priv); |
| 987 | pch_can_start(ndev); |
| 988 | napi_enable(&priv->napi); |
| 989 | netif_start_queue(ndev); |
| 990 | |
| 991 | return 0; |
| 992 | |
| 993 | err_open_candev: |
| 994 | free_irq(priv->dev->irq, ndev); |
| 995 | req_irq_err: |
| 996 | if (priv->use_msi) |
| 997 | pci_disable_msi(priv->dev); |
| 998 | |
| 999 | pch_can_release(priv); |
| 1000 | |
| 1001 | return retval; |
| 1002 | } |
| 1003 | |
| 1004 | static int pch_close(struct net_device *ndev) |
| 1005 | { |
| 1006 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 1007 | |
| 1008 | netif_stop_queue(ndev); |
| 1009 | napi_disable(&priv->napi); |
| 1010 | pch_can_release(priv); |
| 1011 | free_irq(priv->dev->irq, ndev); |
| 1012 | if (priv->use_msi) |
| 1013 | pci_disable_msi(priv->dev); |
| 1014 | close_candev(ndev); |
| 1015 | priv->can.state = CAN_STATE_STOPPED; |
| 1016 | return 0; |
| 1017 | } |
| 1018 | |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1019 | static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) |
| 1020 | { |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1021 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 1022 | struct can_frame *cf = (struct can_frame *)skb->data; |
| 1023 | int tx_buffer_avail = 0; |
Tomoya | 8ac9702 | 2010-12-12 20:24:09 +0000 | [diff] [blame] | 1024 | int i; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1025 | |
| 1026 | if (can_dropped_invalid_skb(ndev, skb)) |
| 1027 | return NETDEV_TX_OK; |
| 1028 | |
Tomoya | 76d94b2 | 2010-12-12 20:24:07 +0000 | [diff] [blame] | 1029 | if (priv->tx_obj == PCH_TX_OBJ_END) { |
| 1030 | if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK) |
| 1031 | netif_stop_queue(ndev); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1032 | |
Tomoya | 76d94b2 | 2010-12-12 20:24:07 +0000 | [diff] [blame] | 1033 | tx_buffer_avail = priv->tx_obj; |
| 1034 | priv->tx_obj = PCH_TX_OBJ_START; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1035 | } else { |
| 1036 | tx_buffer_avail = priv->tx_obj; |
Tomoya | 76d94b2 | 2010-12-12 20:24:07 +0000 | [diff] [blame] | 1037 | priv->tx_obj++; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1038 | } |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1039 | |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1040 | /* Reading the Msg Obj from the Msg RAM to the Interface register. */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1041 | iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); |
| 1042 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1043 | |
| 1044 | /* Setting the CMASK register. */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1045 | pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1046 | |
| 1047 | /* If ID extended is set. */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1048 | pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff); |
| 1049 | pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1050 | if (cf->can_id & CAN_EFF_FLAG) { |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1051 | pch_can_bit_set(&priv->regs->ifregs[1].id1, |
| 1052 | cf->can_id & 0xffff); |
| 1053 | pch_can_bit_set(&priv->regs->ifregs[1].id2, |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 1054 | ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1055 | } else { |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1056 | pch_can_bit_set(&priv->regs->ifregs[1].id1, 0); |
| 1057 | pch_can_bit_set(&priv->regs->ifregs[1].id2, |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1058 | (cf->can_id & CAN_SFF_MASK) << 2); |
| 1059 | } |
| 1060 | |
| 1061 | /* If remote frame has to be transmitted.. */ |
| 1062 | if (cf->can_id & CAN_RTR_FLAG) |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1063 | pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1064 | |
Tomoya | 8ac9702 | 2010-12-12 20:24:09 +0000 | [diff] [blame] | 1065 | /* Copy data to register */ |
| 1066 | for (i = 0; i < cf->can_dlc; i += 2) { |
| 1067 | iowrite16(cf->data[i] | (cf->data[i + 1] << 8), |
| 1068 | &priv->regs->ifregs[1].data[i / 2]); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1069 | } |
| 1070 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 1071 | can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1072 | |
| 1073 | /* Updating the size of the data. */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1074 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f); |
| 1075 | pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1076 | |
| 1077 | /* Clearing IntPend, NewDat & TxRqst */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1078 | pch_can_bit_clear(&priv->regs->ifregs[1].mcont, |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 1079 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | |
| 1080 | PCH_IF_MCONT_TXRQXT); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1081 | |
| 1082 | /* Setting NewDat, TxRqst bits */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1083 | pch_can_bit_set(&priv->regs->ifregs[1].mcont, |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 1084 | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1085 | |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1086 | pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1087 | |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1088 | return NETDEV_TX_OK; |
| 1089 | } |
| 1090 | |
| 1091 | static const struct net_device_ops pch_can_netdev_ops = { |
| 1092 | .ndo_open = pch_can_open, |
| 1093 | .ndo_stop = pch_close, |
| 1094 | .ndo_start_xmit = pch_xmit, |
| 1095 | }; |
| 1096 | |
| 1097 | static void __devexit pch_can_remove(struct pci_dev *pdev) |
| 1098 | { |
| 1099 | struct net_device *ndev = pci_get_drvdata(pdev); |
| 1100 | struct pch_can_priv *priv = netdev_priv(ndev); |
| 1101 | |
| 1102 | unregister_candev(priv->ndev); |
| 1103 | free_candev(priv->ndev); |
| 1104 | pci_iounmap(pdev, priv->regs); |
| 1105 | pci_release_regions(pdev); |
| 1106 | pci_disable_device(pdev); |
| 1107 | pci_set_drvdata(pdev, NULL); |
| 1108 | pch_can_reset(priv); |
| 1109 | } |
| 1110 | |
| 1111 | #ifdef CONFIG_PM |
| 1112 | static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) |
| 1113 | { |
| 1114 | int i; /* Counter variable. */ |
| 1115 | int retval; /* Return value. */ |
| 1116 | u32 buf_stat; /* Variable for reading the transmit buffer status. */ |
| 1117 | u32 counter = 0xFFFFFF; |
| 1118 | |
| 1119 | struct net_device *dev = pci_get_drvdata(pdev); |
| 1120 | struct pch_can_priv *priv = netdev_priv(dev); |
| 1121 | |
| 1122 | /* Stop the CAN controller */ |
| 1123 | pch_can_set_run_mode(priv, PCH_CAN_STOP); |
| 1124 | |
| 1125 | /* Indicate that we are aboutto/in suspend */ |
| 1126 | priv->can.state = CAN_STATE_SLEEPING; |
| 1127 | |
| 1128 | /* Waiting for all transmission to complete. */ |
| 1129 | while (counter) { |
| 1130 | buf_stat = pch_can_get_buffer_status(priv); |
| 1131 | if (!buf_stat) |
| 1132 | break; |
| 1133 | counter--; |
| 1134 | udelay(1); |
| 1135 | } |
| 1136 | if (!counter) |
| 1137 | dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); |
| 1138 | |
| 1139 | /* Save interrupt configuration and then disable them */ |
| 1140 | pch_can_get_int_enables(priv, &(priv->int_enables)); |
| 1141 | pch_can_set_int_enables(priv, PCH_CAN_DISABLE); |
| 1142 | |
| 1143 | /* Save Tx buffer enable state */ |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 1144 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
| 1145 | priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1146 | |
| 1147 | /* Disable all Transmit buffers */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1148 | pch_can_set_tx_all(priv, 0); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1149 | |
| 1150 | /* Save Rx buffer enable state */ |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 1151 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
| 1152 | priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG); |
| 1153 | pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1154 | } |
| 1155 | |
| 1156 | /* Disable all Receive buffers */ |
Tomoya | 8339a7e | 2010-11-29 18:11:52 +0000 | [diff] [blame] | 1157 | pch_can_set_rx_all(priv, 0); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1158 | retval = pci_save_state(pdev); |
| 1159 | if (retval) { |
| 1160 | dev_err(&pdev->dev, "pci_save_state failed.\n"); |
| 1161 | } else { |
| 1162 | pci_enable_wake(pdev, PCI_D3hot, 0); |
| 1163 | pci_disable_device(pdev); |
| 1164 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
| 1165 | } |
| 1166 | |
| 1167 | return retval; |
| 1168 | } |
| 1169 | |
| 1170 | static int pch_can_resume(struct pci_dev *pdev) |
| 1171 | { |
| 1172 | int i; /* Counter variable. */ |
| 1173 | int retval; /* Return variable. */ |
| 1174 | struct net_device *dev = pci_get_drvdata(pdev); |
| 1175 | struct pch_can_priv *priv = netdev_priv(dev); |
| 1176 | |
| 1177 | pci_set_power_state(pdev, PCI_D0); |
| 1178 | pci_restore_state(pdev); |
| 1179 | retval = pci_enable_device(pdev); |
| 1180 | if (retval) { |
| 1181 | dev_err(&pdev->dev, "pci_enable_device failed.\n"); |
| 1182 | return retval; |
| 1183 | } |
| 1184 | |
| 1185 | pci_enable_wake(pdev, PCI_D3hot, 0); |
| 1186 | |
| 1187 | priv->can.state = CAN_STATE_ERROR_ACTIVE; |
| 1188 | |
| 1189 | /* Disabling all interrupts. */ |
| 1190 | pch_can_set_int_enables(priv, PCH_CAN_DISABLE); |
| 1191 | |
| 1192 | /* Setting the CAN device in Stop Mode. */ |
| 1193 | pch_can_set_run_mode(priv, PCH_CAN_STOP); |
| 1194 | |
| 1195 | /* Configuring the transmit and receive buffers. */ |
| 1196 | pch_can_config_rx_tx_buffers(priv); |
| 1197 | |
| 1198 | /* Restore the CAN state */ |
| 1199 | pch_set_bittiming(dev); |
| 1200 | |
| 1201 | /* Listen/Active */ |
| 1202 | pch_can_set_optmode(priv); |
| 1203 | |
| 1204 | /* Enabling the transmit buffer. */ |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 1205 | for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) |
| 1206 | pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1207 | |
| 1208 | /* Configuring the receive buffer and enabling them. */ |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 1209 | for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { |
| 1210 | /* Restore buffer link */ |
| 1211 | pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1212 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 1213 | /* Restore buffer enables */ |
| 1214 | pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1215 | } |
| 1216 | |
| 1217 | /* Enable CAN Interrupts */ |
| 1218 | pch_can_set_int_custom(priv); |
| 1219 | |
| 1220 | /* Restore Run Mode */ |
| 1221 | pch_can_set_run_mode(priv, PCH_CAN_RUN); |
| 1222 | |
| 1223 | return retval; |
| 1224 | } |
| 1225 | #else |
| 1226 | #define pch_can_suspend NULL |
| 1227 | #define pch_can_resume NULL |
| 1228 | #endif |
| 1229 | |
| 1230 | static int pch_can_get_berr_counter(const struct net_device *dev, |
| 1231 | struct can_berr_counter *bec) |
| 1232 | { |
| 1233 | struct pch_can_priv *priv = netdev_priv(dev); |
| 1234 | |
Tomoya | 086b565 | 2010-11-17 01:13:16 +0000 | [diff] [blame] | 1235 | bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC; |
| 1236 | bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1237 | |
| 1238 | return 0; |
| 1239 | } |
| 1240 | |
| 1241 | static int __devinit pch_can_probe(struct pci_dev *pdev, |
| 1242 | const struct pci_device_id *id) |
| 1243 | { |
| 1244 | struct net_device *ndev; |
| 1245 | struct pch_can_priv *priv; |
| 1246 | int rc; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1247 | void __iomem *addr; |
| 1248 | |
| 1249 | rc = pci_enable_device(pdev); |
| 1250 | if (rc) { |
| 1251 | dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); |
| 1252 | goto probe_exit_endev; |
| 1253 | } |
| 1254 | |
| 1255 | rc = pci_request_regions(pdev, KBUILD_MODNAME); |
| 1256 | if (rc) { |
| 1257 | dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); |
| 1258 | goto probe_exit_pcireq; |
| 1259 | } |
| 1260 | |
| 1261 | addr = pci_iomap(pdev, 1, 0); |
| 1262 | if (!addr) { |
| 1263 | rc = -EIO; |
| 1264 | dev_err(&pdev->dev, "Failed pci_iomap\n"); |
| 1265 | goto probe_exit_ipmap; |
| 1266 | } |
| 1267 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 1268 | ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1269 | if (!ndev) { |
| 1270 | rc = -ENOMEM; |
| 1271 | dev_err(&pdev->dev, "Failed alloc_candev\n"); |
| 1272 | goto probe_exit_alloc_candev; |
| 1273 | } |
| 1274 | |
| 1275 | priv = netdev_priv(ndev); |
| 1276 | priv->ndev = ndev; |
| 1277 | priv->regs = addr; |
| 1278 | priv->dev = pdev; |
| 1279 | priv->can.bittiming_const = &pch_can_bittiming_const; |
| 1280 | priv->can.do_set_mode = pch_can_do_set_mode; |
| 1281 | priv->can.do_get_berr_counter = pch_can_get_berr_counter; |
| 1282 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | |
| 1283 | CAN_CTRLMODE_LOOPBACK; |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 1284 | priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1285 | |
| 1286 | ndev->irq = pdev->irq; |
| 1287 | ndev->flags |= IFF_ECHO; |
| 1288 | |
| 1289 | pci_set_drvdata(pdev, ndev); |
| 1290 | SET_NETDEV_DEV(ndev, &pdev->dev); |
| 1291 | ndev->netdev_ops = &pch_can_netdev_ops; |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1292 | priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1293 | |
Tomoya | 15ffc8f | 2010-11-29 18:15:02 +0000 | [diff] [blame] | 1294 | netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1295 | |
| 1296 | rc = register_candev(ndev); |
| 1297 | if (rc) { |
| 1298 | dev_err(&pdev->dev, "Failed register_candev %d\n", rc); |
| 1299 | goto probe_exit_reg_candev; |
| 1300 | } |
| 1301 | |
| 1302 | return 0; |
| 1303 | |
| 1304 | probe_exit_reg_candev: |
| 1305 | free_candev(ndev); |
| 1306 | probe_exit_alloc_candev: |
| 1307 | pci_iounmap(pdev, addr); |
| 1308 | probe_exit_ipmap: |
| 1309 | pci_release_regions(pdev); |
| 1310 | probe_exit_pcireq: |
| 1311 | pci_disable_device(pdev); |
| 1312 | probe_exit_endev: |
| 1313 | return rc; |
| 1314 | } |
| 1315 | |
Marc Kleine-Budde | bdfa3d8 | 2010-10-30 16:28:16 -0700 | [diff] [blame] | 1316 | static struct pci_driver pch_can_pci_driver = { |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1317 | .name = "pch_can", |
| 1318 | .id_table = pch_pci_tbl, |
| 1319 | .probe = pch_can_probe, |
| 1320 | .remove = __devexit_p(pch_can_remove), |
| 1321 | .suspend = pch_can_suspend, |
| 1322 | .resume = pch_can_resume, |
| 1323 | }; |
| 1324 | |
| 1325 | static int __init pch_can_pci_init(void) |
| 1326 | { |
Marc Kleine-Budde | bdfa3d8 | 2010-10-30 16:28:16 -0700 | [diff] [blame] | 1327 | return pci_register_driver(&pch_can_pci_driver); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1328 | } |
| 1329 | module_init(pch_can_pci_init); |
| 1330 | |
| 1331 | static void __exit pch_can_pci_exit(void) |
| 1332 | { |
Marc Kleine-Budde | bdfa3d8 | 2010-10-30 16:28:16 -0700 | [diff] [blame] | 1333 | pci_unregister_driver(&pch_can_pci_driver); |
Masayuki Ohtake | b21d18b | 2010-10-15 03:00:28 +0000 | [diff] [blame] | 1334 | } |
| 1335 | module_exit(pch_can_pci_exit); |
| 1336 | |
| 1337 | MODULE_DESCRIPTION("Controller Area Network Driver"); |
| 1338 | MODULE_LICENSE("GPL v2"); |
| 1339 | MODULE_VERSION("0.94"); |