Andy Yan | b21f4b6 | 2014-12-05 14:26:31 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | */ |
| 9 | |
| 10 | #ifndef __DW_HDMI__ |
| 11 | #define __DW_HDMI__ |
| 12 | |
| 13 | #include <drm/drmP.h> |
| 14 | |
Russell King | b5814ff | 2015-03-27 12:50:58 +0000 | [diff] [blame] | 15 | struct dw_hdmi; |
| 16 | |
Andy Yan | b21f4b6 | 2014-12-05 14:26:31 +0800 | [diff] [blame] | 17 | enum { |
| 18 | DW_HDMI_RES_8, |
| 19 | DW_HDMI_RES_10, |
| 20 | DW_HDMI_RES_12, |
| 21 | DW_HDMI_RES_MAX, |
| 22 | }; |
| 23 | |
| 24 | enum dw_hdmi_devtype { |
| 25 | IMX6Q_HDMI, |
| 26 | IMX6DL_HDMI, |
Andy Yan | 12b9f20 | 2015-01-07 15:48:27 +0800 | [diff] [blame] | 27 | RK3288_HDMI, |
Andy Yan | b21f4b6 | 2014-12-05 14:26:31 +0800 | [diff] [blame] | 28 | }; |
| 29 | |
| 30 | struct dw_hdmi_mpll_config { |
| 31 | unsigned long mpixelclock; |
| 32 | struct { |
| 33 | u16 cpce; |
| 34 | u16 gmp; |
| 35 | } res[DW_HDMI_RES_MAX]; |
| 36 | }; |
| 37 | |
| 38 | struct dw_hdmi_curr_ctrl { |
| 39 | unsigned long mpixelclock; |
| 40 | u16 curr[DW_HDMI_RES_MAX]; |
| 41 | }; |
| 42 | |
Yakir Yang | 034705a | 2015-03-31 23:56:10 -0400 | [diff] [blame] | 43 | struct dw_hdmi_phy_config { |
Andy Yan | b21f4b6 | 2014-12-05 14:26:31 +0800 | [diff] [blame] | 44 | unsigned long mpixelclock; |
| 45 | u16 sym_ctr; /*clock symbol and transmitter control*/ |
| 46 | u16 term; /*transmission termination value*/ |
Yakir Yang | 034705a | 2015-03-31 23:56:10 -0400 | [diff] [blame] | 47 | u16 vlev_ctr; /* voltage level control */ |
Andy Yan | b21f4b6 | 2014-12-05 14:26:31 +0800 | [diff] [blame] | 48 | }; |
| 49 | |
| 50 | struct dw_hdmi_plat_data { |
| 51 | enum dw_hdmi_devtype dev_type; |
| 52 | const struct dw_hdmi_mpll_config *mpll_cfg; |
| 53 | const struct dw_hdmi_curr_ctrl *cur_ctr; |
Yakir Yang | 034705a | 2015-03-31 23:56:10 -0400 | [diff] [blame] | 54 | const struct dw_hdmi_phy_config *phy_config; |
Andy Yan | b21f4b6 | 2014-12-05 14:26:31 +0800 | [diff] [blame] | 55 | enum drm_mode_status (*mode_valid)(struct drm_connector *connector, |
| 56 | struct drm_display_mode *mode); |
| 57 | }; |
| 58 | |
| 59 | void dw_hdmi_unbind(struct device *dev, struct device *master, void *data); |
| 60 | int dw_hdmi_bind(struct device *dev, struct device *master, |
| 61 | void *data, struct drm_encoder *encoder, |
| 62 | struct resource *iores, int irq, |
| 63 | const struct dw_hdmi_plat_data *plat_data); |
Russell King | b5814ff | 2015-03-27 12:50:58 +0000 | [diff] [blame] | 64 | |
| 65 | void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); |
Russell King | b90120a | 2015-03-27 12:59:58 +0000 | [diff] [blame] | 66 | void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); |
| 67 | void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); |
Russell King | b5814ff | 2015-03-27 12:50:58 +0000 | [diff] [blame] | 68 | |
Andy Yan | b21f4b6 | 2014-12-05 14:26:31 +0800 | [diff] [blame] | 69 | #endif /* __IMX_HDMI_H__ */ |