blob: bae79f3c4d28d5e23ca3a94c05a99f5d0c017183 [file] [log] [blame]
Andy Yanb21f4b62014-12-05 14:26:31 +08001/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DW_HDMI__
11#define __DW_HDMI__
12
13#include <drm/drmP.h>
14
Russell Kingb5814ff2015-03-27 12:50:58 +000015struct dw_hdmi;
16
Andy Yanb21f4b62014-12-05 14:26:31 +080017enum {
18 DW_HDMI_RES_8,
19 DW_HDMI_RES_10,
20 DW_HDMI_RES_12,
21 DW_HDMI_RES_MAX,
22};
23
24enum dw_hdmi_devtype {
25 IMX6Q_HDMI,
26 IMX6DL_HDMI,
Andy Yan12b9f202015-01-07 15:48:27 +080027 RK3288_HDMI,
Andy Yanb21f4b62014-12-05 14:26:31 +080028};
29
30struct dw_hdmi_mpll_config {
31 unsigned long mpixelclock;
32 struct {
33 u16 cpce;
34 u16 gmp;
35 } res[DW_HDMI_RES_MAX];
36};
37
38struct dw_hdmi_curr_ctrl {
39 unsigned long mpixelclock;
40 u16 curr[DW_HDMI_RES_MAX];
41};
42
Yakir Yang034705a2015-03-31 23:56:10 -040043struct dw_hdmi_phy_config {
Andy Yanb21f4b62014-12-05 14:26:31 +080044 unsigned long mpixelclock;
45 u16 sym_ctr; /*clock symbol and transmitter control*/
46 u16 term; /*transmission termination value*/
Yakir Yang034705a2015-03-31 23:56:10 -040047 u16 vlev_ctr; /* voltage level control */
Andy Yanb21f4b62014-12-05 14:26:31 +080048};
49
50struct dw_hdmi_plat_data {
51 enum dw_hdmi_devtype dev_type;
52 const struct dw_hdmi_mpll_config *mpll_cfg;
53 const struct dw_hdmi_curr_ctrl *cur_ctr;
Yakir Yang034705a2015-03-31 23:56:10 -040054 const struct dw_hdmi_phy_config *phy_config;
Andy Yanb21f4b62014-12-05 14:26:31 +080055 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
56 struct drm_display_mode *mode);
57};
58
59void dw_hdmi_unbind(struct device *dev, struct device *master, void *data);
60int dw_hdmi_bind(struct device *dev, struct device *master,
61 void *data, struct drm_encoder *encoder,
62 struct resource *iores, int irq,
63 const struct dw_hdmi_plat_data *plat_data);
Russell Kingb5814ff2015-03-27 12:50:58 +000064
65void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
Russell Kingb90120a2015-03-27 12:59:58 +000066void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
67void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
Russell Kingb5814ff2015-03-27 12:50:58 +000068
Andy Yanb21f4b62014-12-05 14:26:31 +080069#endif /* __IMX_HDMI_H__ */