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Sudip Mukherjee81dee672015-03-03 16:21:06 +05301#ifndef DDK750_DISPLAY_H__
2#define DDK750_DISPLAY_H__
3
4/* panel path select
Elizabeth Ferdman35e4d8c2016-09-28 14:33:51 -07005 * 80000[29:28]
6 */
Sudip Mukherjee81dee672015-03-03 16:21:06 +05307
8#define PNL_2_OFFSET 0
9#define PNL_2_MASK (3 << PNL_2_OFFSET)
10#define PNL_2_USAGE (PNL_2_MASK << 16)
Rehas Sachdevaf1f5b432016-09-19 19:26:32 +053011#define PNL_2_PRI ((0 << PNL_2_OFFSET) | PNL_2_USAGE)
12#define PNL_2_SEC ((2 << PNL_2_OFFSET) | PNL_2_USAGE)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053013
14
15/* primary timing & plane enable bit
Elizabeth Ferdman35e4d8c2016-09-28 14:33:51 -070016 * 1: 80000[8] & 80000[2] on
17 * 0: both off
18 */
Sudip Mukherjee81dee672015-03-03 16:21:06 +053019#define PRI_TP_OFFSET 4
Amitoj Kaur Chawlaa5eabae2015-10-17 21:20:00 +053020#define PRI_TP_MASK BIT(PRI_TP_OFFSET)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053021#define PRI_TP_USAGE (PRI_TP_MASK << 16)
Rehas Sachdevaf1f5b432016-09-19 19:26:32 +053022#define PRI_TP_ON ((0x1 << PRI_TP_OFFSET) | PRI_TP_USAGE)
23#define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) | PRI_TP_USAGE)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053024
25
26/* panel sequency status
Elizabeth Ferdman35e4d8c2016-09-28 14:33:51 -070027 * 80000[27:24]
28 */
Sudip Mukherjee81dee672015-03-03 16:21:06 +053029#define PNL_SEQ_OFFSET 6
Amitoj Kaur Chawlaa5eabae2015-10-17 21:20:00 +053030#define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053031#define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16)
Rehas Sachdevaf1f5b432016-09-19 19:26:32 +053032#define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
33#define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053034
35/* dual digital output
Elizabeth Ferdman35e4d8c2016-09-28 14:33:51 -070036 * 80000[19]
37 */
Sudip Mukherjee81dee672015-03-03 16:21:06 +053038#define DUAL_TFT_OFFSET 8
Amitoj Kaur Chawlaa5eabae2015-10-17 21:20:00 +053039#define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053040#define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16)
Rehas Sachdevaf1f5b432016-09-19 19:26:32 +053041#define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
42#define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053043
44/* secondary timing & plane enable bit
Elizabeth Ferdman35e4d8c2016-09-28 14:33:51 -070045 * 1:80200[8] & 80200[2] on
46 * 0: both off
47 */
Sudip Mukherjee81dee672015-03-03 16:21:06 +053048#define SEC_TP_OFFSET 5
Amitoj Kaur Chawlaa5eabae2015-10-17 21:20:00 +053049#define SEC_TP_MASK BIT(SEC_TP_OFFSET)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053050#define SEC_TP_USAGE (SEC_TP_MASK << 16)
Rehas Sachdevaf1f5b432016-09-19 19:26:32 +053051#define SEC_TP_ON ((0x1 << SEC_TP_OFFSET) | SEC_TP_USAGE)
52#define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053053
54/* crt path select
Elizabeth Ferdman35e4d8c2016-09-28 14:33:51 -070055 * 80200[19:18]
56 */
Sudip Mukherjee81dee672015-03-03 16:21:06 +053057#define CRT_2_OFFSET 2
58#define CRT_2_MASK (3 << CRT_2_OFFSET)
59#define CRT_2_USAGE (CRT_2_MASK << 16)
Rehas Sachdevaf1f5b432016-09-19 19:26:32 +053060#define CRT_2_PRI ((0x0 << CRT_2_OFFSET) | CRT_2_USAGE)
61#define CRT_2_SEC ((0x2 << CRT_2_OFFSET) | CRT_2_USAGE)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053062
63
64/* DAC affect both DVI and DSUB
Elizabeth Ferdman35e4d8c2016-09-28 14:33:51 -070065 * 4[20]
66 */
Sudip Mukherjee81dee672015-03-03 16:21:06 +053067#define DAC_OFFSET 7
Amitoj Kaur Chawlaa5eabae2015-10-17 21:20:00 +053068#define DAC_MASK BIT(DAC_OFFSET)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053069#define DAC_USAGE (DAC_MASK << 16)
Rehas Sachdevaf1f5b432016-09-19 19:26:32 +053070#define DAC_ON ((0x0 << DAC_OFFSET) | DAC_USAGE)
71#define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053072
73/* DPMS only affect D-SUB head
Elizabeth Ferdman35e4d8c2016-09-28 14:33:51 -070074 * 0[31:30]
75 */
Sudip Mukherjee81dee672015-03-03 16:21:06 +053076#define DPMS_OFFSET 9
77#define DPMS_MASK (3 << DPMS_OFFSET)
78#define DPMS_USAGE (DPMS_MASK << 16)
Rehas Sachdevaf1f5b432016-09-19 19:26:32 +053079#define DPMS_OFF ((3 << DPMS_OFFSET) | DPMS_USAGE)
80#define DPMS_ON ((0 << DPMS_OFFSET) | DPMS_USAGE)
Sudip Mukherjee81dee672015-03-03 16:21:06 +053081
82
83
Elizabeth Ferdman35e4d8c2016-09-28 14:33:51 -070084/* LCD1 means panel path TFT1 & panel path DVI (so enable DAC)
85 * CRT means crt path DSUB
86 */
Juston Lib63f3dc2015-07-14 21:14:37 -070087typedef enum _disp_output_t {
Rehas Sachdevaf1f5b432016-09-19 19:26:32 +053088 do_LCD1_PRI = PNL_2_PRI | PRI_TP_ON | PNL_SEQ_ON | DAC_ON,
89 do_LCD1_SEC = PNL_2_SEC | SEC_TP_ON | PNL_SEQ_ON | DAC_ON,
90 do_LCD2_PRI = CRT_2_PRI | PRI_TP_ON | DUAL_TFT_ON,
91 do_LCD2_SEC = CRT_2_SEC | SEC_TP_ON | DUAL_TFT_ON,
Elizabeth Ferdman35e4d8c2016-09-28 14:33:51 -070092 /* do_DSUB_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON|DAC_ON,
93 * do_DSUB_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON|DAC_ON,
94 */
Rehas Sachdevaf1f5b432016-09-19 19:26:32 +053095 do_CRT_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON | DAC_ON,
96 do_CRT_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON | DAC_ON,
Sudip Mukherjee81dee672015-03-03 16:21:06 +053097}
98disp_output_t;
Sudip Mukherjee81dee672015-03-03 16:21:06 +053099
100void ddk750_setLogicalDispOut(disp_output_t);
Sudip Mukherjee81dee672015-03-03 16:21:06 +0530101
102#endif