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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* arch/arm/mach-lh7a40x/irq-kev7a400.c
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/interrupt.h>
12#include <linux/init.h>
13
14#include <asm/irq.h>
15#include <asm/mach/irq.h>
16#include <asm/mach/hardware.h>
17#include <asm/mach/irqs.h>
18
19
20 /* KEV7a400 CPLD IRQ handling */
21
22static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */
23
24static void
25lh7a400_ack_cpld_irq (u32 irq)
26{
27 CPLD_CL_INT = 1 << (irq - IRQ_KEV7A400_CPLD);
28}
29
30static void
31lh7a400_mask_cpld_irq (u32 irq)
32{
33 CPLD_IRQ_mask &= ~(1 << (irq - IRQ_KEV7A400_CPLD));
34 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
35}
36
37static void
38lh7a400_unmask_cpld_irq (u32 irq)
39{
40 CPLD_IRQ_mask |= 1 << (irq - IRQ_KEV7A400_CPLD);
41 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
42}
43
44static struct
45irqchip lh7a400_cpld_chip = {
46 .ack = lh7a400_ack_cpld_irq,
47 .mask = lh7a400_mask_cpld_irq,
48 .unmask = lh7a400_unmask_cpld_irq,
49};
50
51static void
52lh7a400_cpld_handler (unsigned int irq, struct irqdesc *desc,
53 struct pt_regs *regs)
54{
55 u32 mask = CPLD_LATCHED_INTS;
56 irq = IRQ_KEV_7A400_CPLD;
57 for (; mask; mask >>= 1, ++irq) {
58 if (mask & 1)
59 desc[irq].handle (irq, desc, regs);
60 }
61}
62
63 /* IRQ initialization */
64
65void __init
66lh7a400_init_board_irq (void)
67{
68 int irq;
69
70 for (irq = IRQ_KEV7A400_CPLD;
71 irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) {
72 set_irq_chip (irq, &lh7a400_cpld_chip);
73 set_irq_handler (irq, do_edge_IRQ);
74 set_irq_flags (irq, IRQF_VALID);
75 }
76 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
77
78 /* Clear all CPLD interrupts */
79 CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */
80
81 /* *** FIXME CF enabled in ide-probe.c */
82
83 GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */
84 barrier();
85 GPIO_INTTYPE1
86 = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */
87 GPIO_INTTYPE2 = 0; /* Falling edge & low-level */
88 GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */
89 GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */
90
91 init_FIQ();
92}