blob: 09b361443fc2c990faae75372bf58a350cfccae2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* unaligned.c: unalignment fixup handler for CPUs on which it is supported (FR451 only)
2 *
3 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/config.h>
13#include <linux/sched.h>
14#include <linux/signal.h>
15#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/types.h>
18#include <linux/user.h>
19#include <linux/string.h>
20#include <linux/linkage.h>
21#include <linux/init.h>
22
23#include <asm/setup.h>
24#include <asm/system.h>
25#include <asm/uaccess.h>
26
27#if 0
28#define kdebug(fmt, ...) printk("FDPIC "fmt"\n" ,##__VA_ARGS__ )
29#else
30#define kdebug(fmt, ...) do {} while(0)
31#endif
32
33#define _MA_SIGNED 0x01
34#define _MA_HALF 0x02
35#define _MA_WORD 0x04
36#define _MA_DWORD 0x08
37#define _MA_SZ_MASK 0x0e
38#define _MA_LOAD 0x10
39#define _MA_STORE 0x20
40#define _MA_UPDATE 0x40
41#define _MA_IMM 0x80
42
43#define _MA_LDxU _MA_LOAD | _MA_UPDATE
44#define _MA_LDxI _MA_LOAD | _MA_IMM
45#define _MA_STxU _MA_STORE | _MA_UPDATE
46#define _MA_STxI _MA_STORE | _MA_IMM
47
48static const uint8_t tbl_LDGRk_reg[0x40] = {
49 [0x02] = _MA_LOAD | _MA_HALF | _MA_SIGNED, /* LDSH @(GRi,GRj),GRk */
50 [0x03] = _MA_LOAD | _MA_HALF, /* LDUH @(GRi,GRj),GRk */
51 [0x04] = _MA_LOAD | _MA_WORD, /* LD @(GRi,GRj),GRk */
52 [0x05] = _MA_LOAD | _MA_DWORD, /* LDD @(GRi,GRj),GRk */
53 [0x12] = _MA_LDxU | _MA_HALF | _MA_SIGNED, /* LDSHU @(GRi,GRj),GRk */
54 [0x13] = _MA_LDxU | _MA_HALF, /* LDUHU @(GRi,GRj),GRk */
55 [0x14] = _MA_LDxU | _MA_WORD, /* LDU @(GRi,GRj),GRk */
56 [0x15] = _MA_LDxU | _MA_DWORD, /* LDDU @(GRi,GRj),GRk */
57};
58
59static const uint8_t tbl_STGRk_reg[0x40] = {
60 [0x01] = _MA_STORE | _MA_HALF, /* STH @(GRi,GRj),GRk */
61 [0x02] = _MA_STORE | _MA_WORD, /* ST @(GRi,GRj),GRk */
62 [0x03] = _MA_STORE | _MA_DWORD, /* STD @(GRi,GRj),GRk */
63 [0x11] = _MA_STxU | _MA_HALF, /* STHU @(GRi,GRj),GRk */
64 [0x12] = _MA_STxU | _MA_WORD, /* STU @(GRi,GRj),GRk */
65 [0x13] = _MA_STxU | _MA_DWORD, /* STDU @(GRi,GRj),GRk */
66};
67
68static const uint8_t tbl_LDSTGRk_imm[0x80] = {
69 [0x31] = _MA_LDxI | _MA_HALF | _MA_SIGNED, /* LDSHI @(GRi,d12),GRk */
70 [0x32] = _MA_LDxI | _MA_WORD, /* LDI @(GRi,d12),GRk */
71 [0x33] = _MA_LDxI | _MA_DWORD, /* LDDI @(GRi,d12),GRk */
72 [0x36] = _MA_LDxI | _MA_HALF, /* LDUHI @(GRi,d12),GRk */
73 [0x51] = _MA_STxI | _MA_HALF, /* STHI @(GRi,d12),GRk */
74 [0x52] = _MA_STxI | _MA_WORD, /* STI @(GRi,d12),GRk */
75 [0x53] = _MA_STxI | _MA_DWORD, /* STDI @(GRi,d12),GRk */
76};
77
78
79/*****************************************************************************/
80/*
81 * see if we can handle the exception by fixing up a misaligned memory access
82 */
83int handle_misalignment(unsigned long esr0, unsigned long ear0, unsigned long epcr0)
84{
85 unsigned long insn, addr, *greg;
86 int GRi, GRj, GRk, D12, op;
87
88 union {
89 uint64_t _64;
90 uint32_t _32[2];
91 uint16_t _16;
92 uint8_t _8[8];
93 } x;
94
95 if (!(esr0 & ESR0_EAV) || !(epcr0 & EPCR0_V) || !(ear0 & 7))
96 return -EAGAIN;
97
98 epcr0 &= EPCR0_PC;
99
100 if (__frame->pc != epcr0) {
101 kdebug("MISALIGN: Execution not halted on excepting instruction\n");
102 BUG();
103 }
104
105 if (__get_user(insn, (unsigned long *) epcr0) < 0)
106 return -EFAULT;
107
108 /* determine the instruction type first */
109 switch ((insn >> 18) & 0x7f) {
110 case 0x2:
111 /* LDx @(GRi,GRj),GRk */
112 op = tbl_LDGRk_reg[(insn >> 6) & 0x3f];
113 break;
114
115 case 0x3:
116 /* STx GRk,@(GRi,GRj) */
117 op = tbl_STGRk_reg[(insn >> 6) & 0x3f];
118 break;
119
120 default:
121 op = tbl_LDSTGRk_imm[(insn >> 18) & 0x7f];
122 break;
123 }
124
125 if (!op)
126 return -EAGAIN;
127
128 kdebug("MISALIGN: pc=%08lx insn=%08lx ad=%08lx op=%02x\n", epcr0, insn, ear0, op);
129
130 memset(&x, 0xba, 8);
131
132 /* validate the instruction parameters */
133 greg = (unsigned long *) &__frame->tbr;
134
135 GRi = (insn >> 12) & 0x3f;
136 GRk = (insn >> 25) & 0x3f;
137
138 if (GRi > 31 || GRk > 31)
139 return -ENOENT;
140
141 if (op & _MA_DWORD && GRk & 1)
142 return -EINVAL;
143
144 if (op & _MA_IMM) {
145 D12 = insn & 0xfff;
146 asm ("slli %0,#20,%0 ! srai %0,#20,%0" : "=r"(D12) : "0"(D12)); /* sign extend */
147 addr = (GRi ? greg[GRi] : 0) + D12;
148 }
149 else {
150 GRj = (insn >> 0) & 0x3f;
151 if (GRj > 31)
152 return -ENOENT;
153 addr = (GRi ? greg[GRi] : 0) + (GRj ? greg[GRj] : 0);
154 }
155
156 if (addr != ear0) {
157 kdebug("MISALIGN: Calculated addr (%08lx) does not match EAR0 (%08lx)\n",
158 addr, ear0);
159 return -EFAULT;
160 }
161
162 /* check the address is okay */
163 if (user_mode(__frame) && ___range_ok(ear0, 8) < 0)
164 return -EFAULT;
165
166 /* perform the memory op */
167 if (op & _MA_STORE) {
168 /* perform a store */
169 x._32[0] = 0;
170 if (GRk != 0) {
171 if (op & _MA_HALF) {
172 x._16 = greg[GRk];
173 }
174 else {
175 x._32[0] = greg[GRk];
176 }
177 }
178 if (op & _MA_DWORD)
179 x._32[1] = greg[GRk + 1];
180
181 kdebug("MISALIGN: Store GR%d { %08x:%08x } -> %08lx (%dB)\n",
182 GRk, x._32[1], x._32[0], addr, op & _MA_SZ_MASK);
183
184 if (__memcpy_user((void *) addr, &x, op & _MA_SZ_MASK) != 0)
185 return -EFAULT;
186 }
187 else {
188 /* perform a load */
189 if (__memcpy_user(&x, (void *) addr, op & _MA_SZ_MASK) != 0)
190 return -EFAULT;
191
192 if (op & _MA_HALF) {
193 if (op & _MA_SIGNED)
194 asm ("slli %0,#16,%0 ! srai %0,#16,%0"
195 : "=r"(x._32[0]) : "0"(x._16));
196 else
197 asm ("sethi #0,%0"
198 : "=r"(x._32[0]) : "0"(x._16));
199 }
200
201 kdebug("MISALIGN: Load %08lx (%dB) -> GR%d, { %08x:%08x }\n",
202 addr, op & _MA_SZ_MASK, GRk, x._32[1], x._32[0]);
203
204 if (GRk != 0)
205 greg[GRk] = x._32[0];
206 if (op & _MA_DWORD)
207 greg[GRk + 1] = x._32[1];
208 }
209
210 /* update the base pointer if required */
211 if (op & _MA_UPDATE)
212 greg[GRi] = addr;
213
214 /* well... we've done that insn */
215 __frame->pc = __frame->pc + 4;
216
217 return 0;
218} /* end handle_misalignment() */