blob: be52c5ac4e054692478d845505b654adf5d869b6 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
3 */
4
5#include <linux/pci.h>
6#include <linux/init.h>
7#include "pci.h"
8
9
10static void __devinit pci_fixup_i450nx(struct pci_dev *d)
11{
12 /*
13 * i450NX -- Find and scan all secondary buses on all PXB's.
14 */
15 int pxb, reg;
16 u8 busno, suba, subb;
17
18 printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
19 reg = 0xd0;
20 for(pxb=0; pxb<2; pxb++) {
21 pci_read_config_byte(d, reg++, &busno);
22 pci_read_config_byte(d, reg++, &suba);
23 pci_read_config_byte(d, reg++, &subb);
24 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
25 if (busno)
26 pci_scan_bus(busno, &pci_root_ops, NULL); /* Bus A */
27 if (suba < subb)
28 pci_scan_bus(suba+1, &pci_root_ops, NULL); /* Bus B */
29 }
30 pcibios_last_bus = -1;
31}
32DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
33
34static void __devinit pci_fixup_i450gx(struct pci_dev *d)
35{
36 /*
37 * i450GX and i450KX -- Find and scan all secondary buses.
38 * (called separately for each PCI bridge found)
39 */
40 u8 busno;
41 pci_read_config_byte(d, 0x4a, &busno);
42 printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno);
43 pci_scan_bus(busno, &pci_root_ops, NULL);
44 pcibios_last_bus = -1;
45}
46DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
47
48static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
49{
50 /*
51 * UM8886BF IDE controller sets region type bits incorrectly,
52 * therefore they look like memory despite of them being I/O.
53 */
54 int i;
55
56 printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d));
57 for(i=0; i<4; i++)
58 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
59}
60DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
61
62static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
63{
64 /*
65 * NCR 53C810 returns class code 0 (at least on some systems).
66 * Fix class to be PCI_CLASS_STORAGE_SCSI
67 */
68 if (!d->class) {
69 printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d));
70 d->class = PCI_CLASS_STORAGE_SCSI << 8;
71 }
72}
73DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
74
75static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
76{
77 int i;
78
79 /*
80 * PCI IDE controllers use non-standard I/O port decoding, respect it.
81 */
82 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
83 return;
84 DBG("PCI: IDE base address fixup for %s\n", pci_name(d));
85 for(i=0; i<4; i++) {
86 struct resource *r = &d->resource[i];
87 if ((r->start & ~0x80) == 0x374) {
88 r->start |= 2;
89 r->end = r->start;
90 }
91 }
92}
93DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
94
95static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
96{
97 int i;
98
99 /*
100 * Runs the fixup only for the first IDE controller
101 * (Shai Fultheim - shai@ftcon.com)
102 */
103 static int called = 0;
104 if (called)
105 return;
106 called = 1;
107
108 /*
109 * There exist PCI IDE controllers which have utter garbage
110 * in first four base registers. Ignore that.
111 */
112 DBG("PCI: IDE base address trash cleared for %s\n", pci_name(d));
113 for(i=0; i<4; i++)
114 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
115}
116DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, pci_fixup_ide_trash);
118DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11, pci_fixup_ide_trash);
119DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_9, pci_fixup_ide_trash);
120
121static void __devinit pci_fixup_latency(struct pci_dev *d)
122{
123 /*
124 * SiS 5597 and 5598 chipsets require latency timer set to
125 * at most 32 to avoid lockups.
126 */
127 DBG("PCI: Setting max latency to 32\n");
128 pcibios_max_latency = 32;
129}
130DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
131DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
132
133static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
134{
135 /*
136 * PIIX4 ACPI device: hardwired IRQ9
137 */
138 d->irq = 9;
139}
140DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
141
142/*
143 * Addresses issues with problems in the memory write queue timer in
144 * certain VIA Northbridges. This bugfix is per VIA's specifications,
145 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
146 * to trigger a bug in its integrated ProSavage video card, which
147 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
148 * until VIA can provide us with definitive information on why screen
149 * corruption occurs, and what exactly those bits do.
150 *
151 * VIA 8363,8622,8361 Northbridges:
152 * - bits 5, 6, 7 at offset 0x55 need to be turned off
153 * VIA 8367 (KT266x) Northbridges:
154 * - bits 5, 6, 7 at offset 0x95 need to be turned off
155 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
156 * - bits 6, 7 at offset 0x55 need to be turned off
157 */
158
159#define VIA_8363_KL133_REVISION_ID 0x81
160#define VIA_8363_KM133_REVISION_ID 0x84
161
162static void __devinit pci_fixup_via_northbridge_bug(struct pci_dev *d)
163{
164 u8 v;
165 u8 revision;
166 int where = 0x55;
167 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
168
169 pci_read_config_byte(d, PCI_REVISION_ID, &revision);
170
171 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
172 /* fix pci bus latency issues resulted by NB bios error
173 it appears on bug free^Wreduced kt266x's bios forces
174 NB latency to zero */
175 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
176
177 where = 0x95; /* the memory write queue timer register is
178 different for the KT266x's: 0x95 not 0x55 */
179 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
180 (revision == VIA_8363_KL133_REVISION_ID ||
181 revision == VIA_8363_KM133_REVISION_ID)) {
182 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
183 causes screen corruption on the KL133/KM133 */
184 }
185
186 pci_read_config_byte(d, where, &v);
187 if (v & ~mask) {
188 printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
189 d->device, revision, where, v, mask, v & mask);
190 v &= mask;
191 pci_write_config_byte(d, where, v);
192 }
193}
194DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
195DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
196DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
197DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
198
199/*
200 * For some reasons Intel decided that certain parts of their
201 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
202 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
203 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
204 * to Intel terminology. These devices do forward all addresses from
205 * system to PCI bus no matter what are their window settings, so they are
206 * "transparent" (or subtractive decoding) from programmers point of view.
207 */
208static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
209{
210 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
211 (dev->device & 0xff00) == 0x2400)
212 dev->transparent = 1;
213}
214DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
215
216/*
217 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
218 *
219 * From information provided by "Allen Martin" <AMartin@nvidia.com>:
220 *
221 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
222 * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
223 * This allows the state-machine and timer to return to a proper state within
224 * 80 ns of the CONNECT and probe appearing together. Since the CPU will not
225 * issue another HALT within 80 ns of the initial HALT, the failure condition
226 * is avoided.
227 */
228static void __init pci_fixup_nforce2(struct pci_dev *dev)
229{
230 u32 val;
231
232 /*
233 * Chip Old value New value
234 * C17 0x1F0FFF01 0x1F01FF01
235 * C18D 0x9F0FFF01 0x9F01FF01
236 *
237 * Northbridge chip version may be determined by
238 * reading the PCI revision ID (0xC1 or greater is C18D).
239 */
240 pci_read_config_dword(dev, 0x6c, &val);
241
242 /*
243 * Apply fixup if needed, but don't touch disconnect state
244 */
245 if ((val & 0x00FF0000) != 0x00010000) {
246 printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
247 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
248 }
249}
250DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
251
252/* Max PCI Express root ports */
253#define MAX_PCIEROOT 6
254static int quirk_aspm_offset[MAX_PCIEROOT << 3];
255
256#define GET_INDEX(a, b) (((a - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + b)
257
258static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
259{
260 return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
261}
262
263/*
264 * Replace the original pci bus ops for write with a new one that will filter
265 * the request to insure ASPM cannot be enabled.
266 */
267static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
268{
269 u8 offset;
270
271 offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
272
273 if ((offset) && (where == offset))
274 value = value & 0xfffffffc;
275
276 return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
277}
278
279static struct pci_ops quirk_pcie_aspm_ops = {
280 .read = quirk_pcie_aspm_read,
281 .write = quirk_pcie_aspm_write,
282};
283
284/*
285 * Prevents PCI Express ASPM (Active State Power Management) being enabled.
286 *
287 * Save the register offset, where the ASPM control bits are located,
288 * for each PCI Express device that is in the device list of
289 * the root port in an array for fast indexing. Replace the bus ops
290 * with the modified one.
291 */
292static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
293{
294 int cap_base, i;
295 struct pci_bus *pbus;
296 struct pci_dev *dev;
297
298 if ((pbus = pdev->subordinate) == NULL)
299 return;
300
301 /*
302 * Check if the DID of pdev matches one of the six root ports. This
303 * check is needed in the case this function is called directly by the
304 * hot-plug driver.
305 */
306 if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
307 (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
308 return;
309
310 if (list_empty(&pbus->devices)) {
311 /*
312 * If no device is attached to the root port at power-up or
313 * after hot-remove, the pbus->devices is empty and this code
314 * will set the offsets to zero and the bus ops to parent's bus
315 * ops, which is unmodified.
316 */
317 for (i= GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
318 quirk_aspm_offset[i] = 0;
319
320 pbus->ops = pbus->parent->ops;
321 } else {
322 /*
323 * If devices are attached to the root port at power-up or
324 * after hot-add, the code loops through the device list of
325 * each root port to save the register offsets and replace the
326 * bus ops.
327 */
328 list_for_each_entry(dev, &pbus->devices, bus_list) {
329 /* There are 0 to 8 devices attached to this bus */
330 cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
331 quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)]= cap_base + 0x10;
332 }
333 pbus->ops = &quirk_pcie_aspm_ops;
334 }
335}
336DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk );
337DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk );
338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk );
339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk );
340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk );
341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk );
342
343/*
344 * Fixup to mark boot BIOS video selected by BIOS before it changes
345 *
346 * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
347 *
348 * The standard boot ROM sequence for an x86 machine uses the BIOS
349 * to select an initial video card for boot display. This boot video
350 * card will have it's BIOS copied to C0000 in system RAM.
351 * IORESOURCE_ROM_SHADOW is used to associate the boot video
352 * card with this copy. On laptops this copy has to be used since
353 * the main ROM may be compressed or combined with another image.
354 * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
355 * is marked here since the boot video device will be the only enabled
356 * video device at this point.
357 */
358
359static void __devinit pci_fixup_video(struct pci_dev *pdev)
360{
361 struct pci_dev *bridge;
362 struct pci_bus *bus;
363 u16 config;
364
365 if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
366 return;
367
368 /* Is VGA routed to us? */
369 bus = pdev->bus;
370 while (bus) {
371 bridge = bus->self;
372 if (bridge) {
373 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
374 &config);
375 if (!(config & PCI_BRIDGE_CTL_VGA))
376 return;
377 }
378 bus = bus->parent;
379 }
380 pci_read_config_word(pdev, PCI_COMMAND, &config);
381 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
382 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
383 printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev));
384 }
385}
386DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);