Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Carsten Langgaard, carstenl@mips.com |
| 3 | * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. |
| 4 | * Copyright (C) 2001 Ralf Baechle |
| 5 | * |
| 6 | * This program is free software; you can distribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License (Version 2) as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 13 | * for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 17 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 18 | * |
| 19 | * Routines for generic manipulation of the interrupts found on the MIPS |
| 20 | * Malta board. |
| 21 | * The interrupt controller is located in the South Bridge a PIIX4 device |
| 22 | * with two internal 82C95 interrupt controllers. |
| 23 | */ |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/irq.h> |
| 26 | #include <linux/sched.h> |
| 27 | #include <linux/slab.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/kernel_stat.h> |
| 30 | #include <linux/random.h> |
| 31 | |
| 32 | #include <asm/i8259.h> |
| 33 | #include <asm/io.h> |
| 34 | #include <asm/mips-boards/malta.h> |
| 35 | #include <asm/mips-boards/maltaint.h> |
| 36 | #include <asm/mips-boards/piix4.h> |
| 37 | #include <asm/gt64120.h> |
| 38 | #include <asm/mips-boards/generic.h> |
| 39 | #include <asm/mips-boards/msc01_pci.h> |
| 40 | |
| 41 | extern asmlinkage void mipsIRQ(void); |
| 42 | |
| 43 | static DEFINE_SPINLOCK(mips_irq_lock); |
| 44 | |
| 45 | static inline int mips_pcibios_iack(void) |
| 46 | { |
| 47 | int irq; |
| 48 | u32 dummy; |
| 49 | |
| 50 | /* |
| 51 | * Determine highest priority pending interrupt by performing |
| 52 | * a PCI Interrupt Acknowledge cycle. |
| 53 | */ |
| 54 | switch(mips_revision_corid) { |
| 55 | case MIPS_REVISION_CORID_CORE_MSC: |
| 56 | case MIPS_REVISION_CORID_CORE_FPGA2: |
| 57 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
| 58 | MSC_READ(MSC01_PCI_IACK, irq); |
| 59 | irq &= 0xff; |
| 60 | break; |
| 61 | case MIPS_REVISION_CORID_QED_RM5261: |
| 62 | case MIPS_REVISION_CORID_CORE_LV: |
| 63 | case MIPS_REVISION_CORID_CORE_FPGA: |
| 64 | case MIPS_REVISION_CORID_CORE_FPGAR2: |
| 65 | irq = GT_READ(GT_PCI0_IACK_OFS); |
| 66 | irq &= 0xff; |
| 67 | break; |
| 68 | case MIPS_REVISION_CORID_BONITO64: |
| 69 | case MIPS_REVISION_CORID_CORE_20K: |
| 70 | case MIPS_REVISION_CORID_CORE_EMUL_BON: |
| 71 | /* The following will generate a PCI IACK cycle on the |
| 72 | * Bonito controller. It's a little bit kludgy, but it |
| 73 | * was the easiest way to implement it in hardware at |
| 74 | * the given time. |
| 75 | */ |
| 76 | BONITO_PCIMAP_CFG = 0x20000; |
| 77 | |
| 78 | /* Flush Bonito register block */ |
| 79 | dummy = BONITO_PCIMAP_CFG; |
| 80 | iob(); /* sync */ |
| 81 | |
| 82 | irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg); |
| 83 | iob(); /* sync */ |
| 84 | irq &= 0xff; |
| 85 | BONITO_PCIMAP_CFG = 0; |
| 86 | break; |
| 87 | default: |
| 88 | printk("Unknown Core card, don't know the system controller.\n"); |
| 89 | return -1; |
| 90 | } |
| 91 | return irq; |
| 92 | } |
| 93 | |
| 94 | static inline int get_int(int *irq) |
| 95 | { |
| 96 | unsigned long flags; |
| 97 | |
| 98 | spin_lock_irqsave(&mips_irq_lock, flags); |
| 99 | |
| 100 | *irq = mips_pcibios_iack(); |
| 101 | |
| 102 | /* |
| 103 | * IRQ7 is used to detect spurious interrupts. |
| 104 | * The interrupt acknowledge cycle returns IRQ7, if no |
| 105 | * interrupts is requested. |
| 106 | * We can differentiate between this situation and a |
| 107 | * "Normal" IRQ7 by reading the ISR. |
| 108 | */ |
| 109 | if (*irq == 7) |
| 110 | { |
| 111 | outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, |
| 112 | PIIX4_ICTLR1_OCW3); |
| 113 | if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) { |
| 114 | spin_unlock_irqrestore(&mips_irq_lock, flags); |
| 115 | printk("We got a spurious interrupt from PIIX4.\n"); |
| 116 | atomic_inc(&irq_err_count); |
| 117 | return -1; /* Spurious interrupt. */ |
| 118 | } |
| 119 | } |
| 120 | |
| 121 | spin_unlock_irqrestore(&mips_irq_lock, flags); |
| 122 | |
| 123 | return 0; |
| 124 | } |
| 125 | |
| 126 | void malta_hw0_irqdispatch(struct pt_regs *regs) |
| 127 | { |
| 128 | int irq; |
| 129 | |
| 130 | if (get_int(&irq)) |
| 131 | return; /* interrupt has already been cleared */ |
| 132 | |
| 133 | do_IRQ(irq, regs); |
| 134 | } |
| 135 | |
| 136 | void corehi_irqdispatch(struct pt_regs *regs) |
| 137 | { |
| 138 | unsigned int data,datahi; |
| 139 | |
| 140 | /* Mask out corehi interrupt. */ |
| 141 | clear_c0_status(IE_IRQ3); |
| 142 | |
| 143 | printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); |
| 144 | printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n" |
| 145 | , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr); |
| 146 | switch(mips_revision_corid) { |
| 147 | case MIPS_REVISION_CORID_CORE_MSC: |
| 148 | case MIPS_REVISION_CORID_CORE_FPGA2: |
| 149 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
| 150 | break; |
| 151 | case MIPS_REVISION_CORID_QED_RM5261: |
| 152 | case MIPS_REVISION_CORID_CORE_LV: |
| 153 | case MIPS_REVISION_CORID_CORE_FPGA: |
| 154 | case MIPS_REVISION_CORID_CORE_FPGAR2: |
| 155 | data = GT_READ(GT_INTRCAUSE_OFS); |
| 156 | printk("GT_INTRCAUSE = %08x\n", data); |
| 157 | data = GT_READ(GT_CPUERR_ADDRLO_OFS); |
| 158 | datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); |
| 159 | printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, data); |
| 160 | break; |
| 161 | case MIPS_REVISION_CORID_BONITO64: |
| 162 | case MIPS_REVISION_CORID_CORE_20K: |
| 163 | case MIPS_REVISION_CORID_CORE_EMUL_BON: |
| 164 | data = BONITO_INTISR; |
| 165 | printk("BONITO_INTISR = %08x\n", data); |
| 166 | data = BONITO_INTEN; |
| 167 | printk("BONITO_INTEN = %08x\n", data); |
| 168 | data = BONITO_INTPOL; |
| 169 | printk("BONITO_INTPOL = %08x\n", data); |
| 170 | data = BONITO_INTEDGE; |
| 171 | printk("BONITO_INTEDGE = %08x\n", data); |
| 172 | data = BONITO_INTSTEER; |
| 173 | printk("BONITO_INTSTEER = %08x\n", data); |
| 174 | data = BONITO_PCICMD; |
| 175 | printk("BONITO_PCICMD = %08x\n", data); |
| 176 | break; |
| 177 | } |
| 178 | |
| 179 | /* We die here*/ |
| 180 | die("CoreHi interrupt", regs); |
| 181 | } |
| 182 | |
| 183 | void __init arch_init_irq(void) |
| 184 | { |
| 185 | set_except_vector(0, mipsIRQ); |
| 186 | init_i8259_irqs(); |
| 187 | } |