Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Toshiba rbtx4927 specific setup |
| 3 | * |
| 4 | * Author: MontaVista Software, Inc. |
| 5 | * source@mvista.com |
| 6 | * |
| 7 | * Copyright 2001-2002 MontaVista Software Inc. |
| 8 | * |
| 9 | * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) |
| 10 | * Copyright (C) 2000 RidgeRun, Inc. |
| 11 | * Author: RidgeRun, Inc. |
| 12 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com |
| 13 | * |
| 14 | * Copyright 2001 MontaVista Software Inc. |
| 15 | * Author: jsun@mvista.com or jsun@junsun.net |
| 16 | * |
| 17 | * Copyright 2002 MontaVista Software Inc. |
| 18 | * Author: Michael Pruznick, michael_pruznick@mvista.com |
| 19 | * |
| 20 | * Copyright (C) 2000-2001 Toshiba Corporation |
| 21 | * |
| 22 | * Copyright (C) 2004 MontaVista Software Inc. |
| 23 | * Author: Manish Lachwani, mlachwani@mvista.com |
| 24 | * |
| 25 | * This program is free software; you can redistribute it and/or modify it |
| 26 | * under the terms of the GNU General Public License as published by the |
| 27 | * Free Software Foundation; either version 2 of the License, or (at your |
| 28 | * option) any later version. |
| 29 | * |
| 30 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 31 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 32 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 33 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 34 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 35 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 36 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 37 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR |
| 38 | * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE |
| 39 | * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 40 | * |
| 41 | * You should have received a copy of the GNU General Public License along |
| 42 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 43 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 44 | */ |
| 45 | #include <linux/config.h> |
| 46 | #include <linux/init.h> |
| 47 | #include <linux/kernel.h> |
| 48 | #include <linux/types.h> |
| 49 | #include <linux/mm.h> |
| 50 | #include <linux/swap.h> |
| 51 | #include <linux/ioport.h> |
| 52 | #include <linux/sched.h> |
| 53 | #include <linux/interrupt.h> |
| 54 | #include <linux/pci.h> |
| 55 | #include <linux/timex.h> |
| 56 | #include <asm/bootinfo.h> |
| 57 | #include <asm/page.h> |
| 58 | #include <asm/io.h> |
| 59 | #include <asm/irq.h> |
| 60 | #include <asm/processor.h> |
| 61 | #include <asm/ptrace.h> |
| 62 | #include <asm/reboot.h> |
| 63 | #include <asm/time.h> |
| 64 | #include <linux/bootmem.h> |
| 65 | #include <linux/blkdev.h> |
| 66 | #ifdef CONFIG_RTC_DS1742 |
| 67 | #include <linux/ds1742rtc.h> |
| 68 | #endif |
| 69 | #ifdef CONFIG_TOSHIBA_FPCIB0 |
| 70 | #include <asm/tx4927/smsc_fdc37m81x.h> |
| 71 | #endif |
| 72 | #include <asm/tx4927/toshiba_rbtx4927.h> |
| 73 | #ifdef CONFIG_PCI |
| 74 | #include <asm/tx4927/tx4927_pci.h> |
| 75 | #endif |
| 76 | #ifdef CONFIG_BLK_DEV_IDEPCI |
| 77 | #include <linux/hdreg.h> |
| 78 | #include <linux/ide.h> |
| 79 | #endif |
| 80 | |
| 81 | #undef TOSHIBA_RBTX4927_SETUP_DEBUG |
| 82 | |
| 83 | #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG |
| 84 | #define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000 |
| 85 | |
| 86 | #define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 ) |
| 87 | #define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 ) |
| 88 | #define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 ) |
| 89 | |
| 90 | #define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 ) |
| 91 | #define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 ) |
| 92 | #define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 ) |
| 93 | #define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 ) |
| 94 | #define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 ) |
| 95 | #define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 ) |
| 96 | #define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 ) |
| 97 | #define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 ) |
| 98 | |
| 99 | #define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff |
| 100 | #endif |
| 101 | |
| 102 | #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG |
| 103 | static const u32 toshiba_rbtx4927_setup_debug_flag = |
| 104 | (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO | |
| 105 | TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR | |
| 106 | TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP | |
| 107 | TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP |
| 108 | | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 | |
| 109 | TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66); |
| 110 | #endif |
| 111 | |
| 112 | #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG |
| 113 | #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \ |
| 114 | if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \ |
| 115 | { \ |
| 116 | char tmp[100]; \ |
| 117 | sprintf( tmp, str ); \ |
| 118 | printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ |
| 119 | } |
| 120 | #else |
| 121 | #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) |
| 122 | #endif |
| 123 | |
| 124 | /* These functions are used for rebooting or halting the machine*/ |
| 125 | extern void toshiba_rbtx4927_restart(char *command); |
| 126 | extern void toshiba_rbtx4927_halt(void); |
| 127 | extern void toshiba_rbtx4927_power_off(void); |
| 128 | |
| 129 | int tx4927_using_backplane = 0; |
| 130 | |
| 131 | extern void gt64120_time_init(void); |
| 132 | extern void toshiba_rbtx4927_irq_setup(void); |
| 133 | |
| 134 | #ifdef CONFIG_PCI |
| 135 | #define CONFIG_TX4927BUG_WORKAROUND |
| 136 | #undef TX4927_SUPPORT_COMMAND_IO |
| 137 | #undef TX4927_SUPPORT_PCI_66 |
| 138 | int tx4927_cpu_clock = 100000000; /* 100MHz */ |
| 139 | unsigned long mips_pci_io_base; |
| 140 | unsigned long mips_pci_io_size; |
| 141 | unsigned long mips_pci_mem_base; |
| 142 | unsigned long mips_pci_mem_size; |
| 143 | /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ |
| 144 | unsigned long mips_pci_io_pciaddr = 0; |
| 145 | unsigned long mips_memory_upper; |
| 146 | static int tx4927_ccfg_toeon = 1; |
| 147 | static int tx4927_pcic_trdyto = 0; /* default: disabled */ |
| 148 | unsigned long tx4927_ce_base[8]; |
| 149 | void tx4927_pci_setup(void); |
| 150 | void tx4927_reset_pci_pcic(void); |
| 151 | int tx4927_pci66 = 0; /* 0:auto */ |
| 152 | #endif |
| 153 | |
| 154 | char *toshiba_name = ""; |
| 155 | |
| 156 | #ifdef CONFIG_PCI |
| 157 | static void tx4927_pcierr_interrupt(int irq, void *dev_id, |
| 158 | struct pt_regs *regs) |
| 159 | { |
| 160 | #ifdef CONFIG_BLK_DEV_IDEPCI |
| 161 | /* ignore MasterAbort for ide probing... */ |
| 162 | if (irq == TX4927_IRQ_IRC_PCIERR && |
| 163 | ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) == |
| 164 | PCI_STATUS_REC_MASTER_ABORT) { |
| 165 | tx4927_pcicptr->pcistatus = |
| 166 | (tx4927_pcicptr-> |
| 167 | pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT |
| 168 | << 16); |
| 169 | |
| 170 | return; |
| 171 | } |
| 172 | #endif |
| 173 | printk("PCI error interrupt (irq 0x%x).\n", irq); |
| 174 | |
| 175 | printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n", |
| 176 | (unsigned short) (tx4927_pcicptr->pcistatus >> 16), |
| 177 | tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus); |
| 178 | printk("ccfg:%08lx, tear:%02lx_%08lx\n", |
| 179 | (unsigned long) tx4927_ccfgptr->ccfg, |
| 180 | (unsigned long) (tx4927_ccfgptr->tear >> 32), |
| 181 | (unsigned long) tx4927_ccfgptr->tear); |
| 182 | show_regs(regs); |
| 183 | } |
| 184 | |
| 185 | void __init toshiba_rbtx4927_pci_irq_init(void) |
| 186 | { |
| 187 | return; |
| 188 | } |
| 189 | |
| 190 | void tx4927_reset_pci_pcic(void) |
| 191 | { |
| 192 | /* Reset PCI Bus */ |
| 193 | *tx4927_pcireset_ptr = 1; |
| 194 | /* Reset PCIC */ |
| 195 | tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST; |
| 196 | udelay(10000); |
| 197 | /* clear PCIC reset */ |
| 198 | tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST; |
| 199 | *tx4927_pcireset_ptr = 0; |
| 200 | } |
| 201 | #endif /* CONFIG_PCI */ |
| 202 | |
| 203 | #ifdef CONFIG_PCI |
| 204 | void print_pci_status(void) |
| 205 | { |
| 206 | printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus); |
| 207 | printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus); |
| 208 | } |
| 209 | |
| 210 | extern struct pci_controller tx4927_controller; |
| 211 | |
| 212 | static struct pci_dev *fake_pci_dev(struct pci_controller *hose, |
| 213 | int top_bus, int busnr, int devfn) |
| 214 | { |
| 215 | static struct pci_dev dev; |
| 216 | static struct pci_bus bus; |
| 217 | |
| 218 | dev.sysdata = (void *)hose; |
| 219 | dev.devfn = devfn; |
| 220 | bus.number = busnr; |
| 221 | bus.ops = hose->pci_ops; |
| 222 | bus.parent = NULL; |
| 223 | dev.bus = &bus; |
| 224 | |
| 225 | return &dev; |
| 226 | } |
| 227 | |
| 228 | #define EARLY_PCI_OP(rw, size, type) \ |
| 229 | static int early_##rw##_config_##size(struct pci_controller *hose, \ |
| 230 | int top_bus, int bus, int devfn, int offset, type value) \ |
| 231 | { \ |
| 232 | return pci_##rw##_config_##size( \ |
| 233 | fake_pci_dev(hose, top_bus, bus, devfn), \ |
| 234 | offset, value); \ |
| 235 | } |
| 236 | |
| 237 | EARLY_PCI_OP(read, byte, u8 *) |
| 238 | EARLY_PCI_OP(read, word, u16 *) |
| 239 | EARLY_PCI_OP(read, dword, u32 *) |
| 240 | EARLY_PCI_OP(write, byte, u8) |
| 241 | EARLY_PCI_OP(write, word, u16) |
| 242 | EARLY_PCI_OP(write, dword, u32) |
| 243 | |
| 244 | static int __init tx4927_pcibios_init(void) |
| 245 | { |
| 246 | unsigned int id; |
| 247 | u32 pci_devfn; |
| 248 | int devfn_start = 0; |
| 249 | int devfn_stop = 0xff; |
| 250 | int busno = 0; /* One bus on the Toshiba */ |
| 251 | struct pci_controller *hose = &tx4927_controller; |
| 252 | |
| 253 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 254 | "-\n"); |
| 255 | |
| 256 | for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { |
| 257 | early_read_config_dword(hose, busno, busno, pci_devfn, |
| 258 | PCI_VENDOR_ID, &id); |
| 259 | |
| 260 | if (id == 0xffffffff) { |
| 261 | continue; |
| 262 | } |
| 263 | |
| 264 | if (id == 0x94601055) { |
| 265 | u8 v08_64; |
| 266 | u32 v32_b0; |
| 267 | u8 v08_e1; |
| 268 | char *s = " sb/isa --"; |
| 269 | |
| 270 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 271 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", |
| 272 | s); |
| 273 | |
| 274 | early_read_config_byte(hose, busno, busno, |
| 275 | pci_devfn, 0x64, &v08_64); |
| 276 | early_read_config_dword(hose, busno, busno, |
| 277 | pci_devfn, 0xb0, &v32_b0); |
| 278 | early_read_config_byte(hose, busno, busno, |
| 279 | pci_devfn, 0xe1, &v08_e1); |
| 280 | |
| 281 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 282 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 283 | ":%s beg 0x64 = 0x%02x\n", s, v08_64); |
| 284 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 285 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 286 | ":%s beg 0xb0 = 0x%02x\n", s, v32_b0); |
| 287 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 288 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 289 | ":%s beg 0xe1 = 0x%02x\n", s, v08_e1); |
| 290 | |
| 291 | /* serial irq control */ |
| 292 | v08_64 = 0xd0; |
| 293 | |
| 294 | /* serial irq pin */ |
| 295 | v32_b0 |= 0x00010000; |
| 296 | |
| 297 | /* ide irq on isa14 */ |
| 298 | v08_e1 &= 0xf0; |
| 299 | v08_e1 |= 0x0d; |
| 300 | |
| 301 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 302 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 303 | ":%s mid 0x64 = 0x%02x\n", s, v08_64); |
| 304 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 305 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 306 | ":%s mid 0xb0 = 0x%02x\n", s, v32_b0); |
| 307 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 308 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 309 | ":%s mid 0xe1 = 0x%02x\n", s, v08_e1); |
| 310 | |
| 311 | early_write_config_byte(hose, busno, busno, |
| 312 | pci_devfn, 0x64, v08_64); |
| 313 | early_write_config_dword(hose, busno, busno, |
| 314 | pci_devfn, 0xb0, v32_b0); |
| 315 | early_write_config_byte(hose, busno, busno, |
| 316 | pci_devfn, 0xe1, v08_e1); |
| 317 | |
| 318 | #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG |
| 319 | { |
| 320 | early_read_config_byte(hose, busno, busno, |
| 321 | pci_devfn, 0x64, |
| 322 | &v08_64); |
| 323 | early_read_config_dword(hose, busno, busno, |
| 324 | pci_devfn, 0xb0, |
| 325 | &v32_b0); |
| 326 | early_read_config_byte(hose, busno, busno, |
| 327 | pci_devfn, 0xe1, |
| 328 | &v08_e1); |
| 329 | |
| 330 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 331 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 332 | ":%s end 0x64 = 0x%02x\n", s, v08_64); |
| 333 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 334 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 335 | ":%s end 0xb0 = 0x%02x\n", s, v32_b0); |
| 336 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 337 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 338 | ":%s end 0xe1 = 0x%02x\n", s, v08_e1); |
| 339 | } |
| 340 | #endif |
| 341 | |
| 342 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 343 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n", |
| 344 | s); |
| 345 | } |
| 346 | |
| 347 | if (id == 0x91301055) { |
| 348 | u8 v08_04; |
| 349 | u8 v08_09; |
| 350 | u8 v08_41; |
| 351 | u8 v08_43; |
| 352 | u8 v08_5c; |
| 353 | char *s = " sb/ide --"; |
| 354 | |
| 355 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 356 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", |
| 357 | s); |
| 358 | |
| 359 | early_read_config_byte(hose, busno, busno, |
| 360 | pci_devfn, 0x04, &v08_04); |
| 361 | early_read_config_byte(hose, busno, busno, |
| 362 | pci_devfn, 0x09, &v08_09); |
| 363 | early_read_config_byte(hose, busno, busno, |
| 364 | pci_devfn, 0x41, &v08_41); |
| 365 | early_read_config_byte(hose, busno, busno, |
| 366 | pci_devfn, 0x43, &v08_43); |
| 367 | early_read_config_byte(hose, busno, busno, |
| 368 | pci_devfn, 0x5c, &v08_5c); |
| 369 | |
| 370 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 371 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 372 | ":%s beg 0x04 = 0x%02x\n", s, v08_04); |
| 373 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 374 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 375 | ":%s beg 0x09 = 0x%02x\n", s, v08_09); |
| 376 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 377 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 378 | ":%s beg 0x41 = 0x%02x\n", s, v08_41); |
| 379 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 380 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 381 | ":%s beg 0x43 = 0x%02x\n", s, v08_43); |
| 382 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 383 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 384 | ":%s beg 0x5c = 0x%02x\n", s, v08_5c); |
| 385 | |
| 386 | /* enable ide master/io */ |
| 387 | v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); |
| 388 | |
| 389 | /* enable ide native mode */ |
| 390 | v08_09 |= 0x05; |
| 391 | |
| 392 | /* enable primary ide */ |
| 393 | v08_41 |= 0x80; |
| 394 | |
| 395 | /* enable secondary ide */ |
| 396 | v08_43 |= 0x80; |
| 397 | |
| 398 | /* |
| 399 | * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! |
| 400 | * |
| 401 | * This line of code is intended to provide the user with a work |
| 402 | * around solution to the anomalies cited in SMSC's anomaly sheet |
| 403 | * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". |
| 404 | * |
| 405 | * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! |
| 406 | */ |
| 407 | v08_5c |= 0x01; |
| 408 | |
| 409 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 410 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 411 | ":%s mid 0x04 = 0x%02x\n", s, v08_04); |
| 412 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 413 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 414 | ":%s mid 0x09 = 0x%02x\n", s, v08_09); |
| 415 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 416 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 417 | ":%s mid 0x41 = 0x%02x\n", s, v08_41); |
| 418 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 419 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 420 | ":%s mid 0x43 = 0x%02x\n", s, v08_43); |
| 421 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 422 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 423 | ":%s mid 0x5c = 0x%02x\n", s, v08_5c); |
| 424 | |
| 425 | early_write_config_byte(hose, busno, busno, |
| 426 | pci_devfn, 0x5c, v08_5c); |
| 427 | early_write_config_byte(hose, busno, busno, |
| 428 | pci_devfn, 0x04, v08_04); |
| 429 | early_write_config_byte(hose, busno, busno, |
| 430 | pci_devfn, 0x09, v08_09); |
| 431 | early_write_config_byte(hose, busno, busno, |
| 432 | pci_devfn, 0x41, v08_41); |
| 433 | early_write_config_byte(hose, busno, busno, |
| 434 | pci_devfn, 0x43, v08_43); |
| 435 | |
| 436 | #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG |
| 437 | { |
| 438 | early_read_config_byte(hose, busno, busno, |
| 439 | pci_devfn, 0x04, |
| 440 | &v08_04); |
| 441 | early_read_config_byte(hose, busno, busno, |
| 442 | pci_devfn, 0x09, |
| 443 | &v08_09); |
| 444 | early_read_config_byte(hose, busno, busno, |
| 445 | pci_devfn, 0x41, |
| 446 | &v08_41); |
| 447 | early_read_config_byte(hose, busno, busno, |
| 448 | pci_devfn, 0x43, |
| 449 | &v08_43); |
| 450 | early_read_config_byte(hose, busno, busno, |
| 451 | pci_devfn, 0x5c, |
| 452 | &v08_5c); |
| 453 | |
| 454 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 455 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 456 | ":%s end 0x04 = 0x%02x\n", s, v08_04); |
| 457 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 458 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 459 | ":%s end 0x09 = 0x%02x\n", s, v08_09); |
| 460 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 461 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 462 | ":%s end 0x41 = 0x%02x\n", s, v08_41); |
| 463 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 464 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 465 | ":%s end 0x43 = 0x%02x\n", s, v08_43); |
| 466 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 467 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 468 | ":%s end 0x5c = 0x%02x\n", s, v08_5c); |
| 469 | } |
| 470 | #endif |
| 471 | |
| 472 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 473 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n", |
| 474 | s); |
| 475 | } |
| 476 | |
| 477 | } |
| 478 | |
| 479 | register_pci_controller(&tx4927_controller); |
| 480 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, |
| 481 | "+\n"); |
| 482 | |
| 483 | return 0; |
| 484 | } |
| 485 | |
| 486 | arch_initcall(tx4927_pcibios_init); |
| 487 | |
| 488 | extern struct resource pci_io_resource; |
| 489 | extern struct resource pci_mem_resource; |
| 490 | |
| 491 | void tx4927_pci_setup(void) |
| 492 | { |
| 493 | static int called = 0; |
| 494 | extern unsigned int tx4927_get_mem_size(void); |
| 495 | |
| 496 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n"); |
| 497 | |
| 498 | mips_memory_upper = tx4927_get_mem_size() << 20; |
| 499 | mips_memory_upper += KSEG0; |
| 500 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 501 | "0x%08lx=mips_memory_upper\n", |
| 502 | mips_memory_upper); |
| 503 | mips_pci_io_base = TX4927_PCIIO; |
| 504 | mips_pci_io_size = TX4927_PCIIO_SIZE; |
| 505 | mips_pci_mem_base = TX4927_PCIMEM; |
| 506 | mips_pci_mem_size = TX4927_PCIMEM_SIZE; |
| 507 | |
| 508 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 509 | "0x%08lx=mips_pci_io_base\n", |
| 510 | mips_pci_io_base); |
| 511 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 512 | "0x%08lx=mips_pci_io_size\n", |
| 513 | mips_pci_io_size); |
| 514 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 515 | "0x%08lx=mips_pci_mem_base\n", |
| 516 | mips_pci_mem_base); |
| 517 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 518 | "0x%08lx=mips_pci_mem_size\n", |
| 519 | mips_pci_mem_size); |
| 520 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 521 | "0x%08lx=pci_io_resource.start\n", |
| 522 | pci_io_resource.start); |
| 523 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 524 | "0x%08lx=pci_io_resource.end\n", |
| 525 | pci_io_resource.end); |
| 526 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 527 | "0x%08lx=pci_mem_resource.start\n", |
| 528 | pci_mem_resource.start); |
| 529 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 530 | "0x%08lx=pci_mem_resource.end\n", |
| 531 | pci_mem_resource.end); |
| 532 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 533 | "0x%08lx=mips_io_port_base", |
| 534 | mips_io_port_base); |
| 535 | |
| 536 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 537 | "setup pci_io_resource to 0x%08lx 0x%08lx\n", |
| 538 | pci_io_resource.start, |
| 539 | pci_io_resource.end); |
| 540 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 541 | "setup pci_mem_resource to 0x%08lx 0x%08lx\n", |
| 542 | pci_mem_resource.start, |
| 543 | pci_mem_resource.end); |
| 544 | |
| 545 | if (!called) { |
| 546 | printk |
| 547 | ("TX4927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", |
| 548 | (unsigned short) (tx4927_pcicptr->pciid >> 16), |
| 549 | (unsigned short) (tx4927_pcicptr->pciid & 0xffff), |
| 550 | (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), |
| 551 | (!(tx4927_ccfgptr-> |
| 552 | ccfg & TX4927_CCFG_PCIXARB)) ? "External" : |
| 553 | "Internal"); |
| 554 | called = 1; |
| 555 | } |
| 556 | printk("%s PCIC --%s PCICLK:",toshiba_name, |
| 557 | (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); |
| 558 | if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { |
| 559 | int pciclk = 0; |
| 560 | switch ((unsigned long) tx4927_ccfgptr-> |
| 561 | ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { |
| 562 | case TX4927_CCFG_PCIDIVMODE_2_5: |
| 563 | pciclk = tx4927_cpu_clock * 2 / 5; |
| 564 | break; |
| 565 | case TX4927_CCFG_PCIDIVMODE_3: |
| 566 | pciclk = tx4927_cpu_clock / 3; |
| 567 | break; |
| 568 | case TX4927_CCFG_PCIDIVMODE_5: |
| 569 | pciclk = tx4927_cpu_clock / 5; |
| 570 | break; |
| 571 | case TX4927_CCFG_PCIDIVMODE_6: |
| 572 | pciclk = tx4927_cpu_clock / 6; |
| 573 | break; |
| 574 | } |
| 575 | printk("Internal(%dMHz)", pciclk / 1000000); |
| 576 | } else { |
| 577 | int pciclk = 0; |
| 578 | int pciclk_setting = *tx4927_pci_clk_ptr; |
| 579 | switch (pciclk_setting & TX4927_PCI_CLK_MASK) { |
| 580 | case TX4927_PCI_CLK_33: |
| 581 | pciclk = 33333333; |
| 582 | break; |
| 583 | case TX4927_PCI_CLK_25: |
| 584 | pciclk = 25000000; |
| 585 | break; |
| 586 | case TX4927_PCI_CLK_66: |
| 587 | pciclk = 66666666; |
| 588 | break; |
| 589 | case TX4927_PCI_CLK_50: |
| 590 | pciclk = 50000000; |
| 591 | break; |
| 592 | } |
| 593 | printk("External(%dMHz)", pciclk / 1000000); |
| 594 | } |
| 595 | printk("\n"); |
| 596 | |
| 597 | |
| 598 | |
| 599 | /* GB->PCI mappings */ |
| 600 | tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; |
| 601 | tx4927_pcicptr->g2piogbase = mips_pci_io_base | |
| 602 | #ifdef __BIG_ENDIAN |
| 603 | TX4927_PCIC_G2PIOGBASE_ECHG |
| 604 | #else |
| 605 | TX4927_PCIC_G2PIOGBASE_BSDIS |
| 606 | #endif |
| 607 | ; |
| 608 | |
| 609 | tx4927_pcicptr->g2piopbase = 0; |
| 610 | |
| 611 | tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4; |
| 612 | tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base | |
| 613 | #ifdef __BIG_ENDIAN |
| 614 | TX4927_PCIC_G2PMnGBASE_ECHG |
| 615 | #else |
| 616 | TX4927_PCIC_G2PMnGBASE_BSDIS |
| 617 | #endif |
| 618 | ; |
| 619 | tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base; |
| 620 | |
| 621 | tx4927_pcicptr->g2pmmask[1] = 0; |
| 622 | tx4927_pcicptr->g2pmgbase[1] = 0; |
| 623 | tx4927_pcicptr->g2pmpbase[1] = 0; |
| 624 | tx4927_pcicptr->g2pmmask[2] = 0; |
| 625 | tx4927_pcicptr->g2pmgbase[2] = 0; |
| 626 | tx4927_pcicptr->g2pmpbase[2] = 0; |
| 627 | |
| 628 | |
| 629 | /* PCI->GB mappings (I/O 256B) */ |
| 630 | tx4927_pcicptr->p2giopbase = 0; /* 256B */ |
| 631 | |
| 632 | /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ |
| 633 | tx4927_pcicptr->p2gm0plbase = 0; |
| 634 | tx4927_pcicptr->p2gm0pubase = 0; |
| 635 | tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN | |
| 636 | #ifdef __BIG_ENDIAN |
| 637 | TX4927_PCIC_P2GMnGBASE_TECHG |
| 638 | #else |
| 639 | TX4927_PCIC_P2GMnGBASE_TBSDIS |
| 640 | #endif |
| 641 | ; |
| 642 | |
| 643 | /* PCI->GB mappings (MEM 16MB) -not used */ |
| 644 | tx4927_pcicptr->p2gm1plbase = 0xffffffff; |
| 645 | #ifdef CONFIG_TX4927BUG_WORKAROUND |
| 646 | /* |
| 647 | * TX4927-PCIC-BUG: P2GM1PUBASE must be 0 |
| 648 | * if P2GM0PUBASE was 0. |
| 649 | */ |
| 650 | tx4927_pcicptr->p2gm1pubase = 0; |
| 651 | #else |
| 652 | tx4927_pcicptr->p2gm1pubase = 0xffffffff; |
| 653 | #endif |
| 654 | tx4927_pcicptr->p2gmgbase[1] = 0; |
| 655 | |
| 656 | /* PCI->GB mappings (MEM 1MB) -not used */ |
| 657 | tx4927_pcicptr->p2gm2pbase = 0xffffffff; |
| 658 | tx4927_pcicptr->p2gmgbase[2] = 0; |
| 659 | |
| 660 | |
| 661 | /* Enable Initiator Memory 0 Space, I/O Space, Config */ |
| 662 | tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK; |
| 663 | tx4927_pcicptr->pciccfg |= |
| 664 | TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE | |
| 665 | TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR; |
| 666 | |
| 667 | |
| 668 | /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ |
| 669 | tx4927_pcicptr->pcicfg1 = 0; |
| 670 | |
| 671 | if (tx4927_pcic_trdyto >= 0) { |
| 672 | tx4927_pcicptr->g2ptocnt &= ~0xff; |
| 673 | tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); |
| 674 | } |
| 675 | |
| 676 | /* Clear All Local Bus Status */ |
| 677 | tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL; |
| 678 | /* Enable All Local Bus Interrupts */ |
| 679 | tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL; |
| 680 | /* Clear All Initiator Status */ |
| 681 | tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL; |
| 682 | /* Enable All Initiator Interrupts */ |
| 683 | tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL; |
| 684 | /* Clear All PCI Status Error */ |
| 685 | tx4927_pcicptr->pcistatus = |
| 686 | (tx4927_pcicptr->pcistatus & 0x0000ffff) | |
| 687 | (TX4927_PCIC_PCISTATUS_ALL << 16); |
| 688 | /* Enable All PCI Status Error Interrupts */ |
| 689 | tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL; |
| 690 | |
| 691 | /* PCIC Int => IRC IRQ16 */ |
| 692 | tx4927_pcicptr->pcicfg2 = |
| 693 | (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC; |
| 694 | |
| 695 | if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) { |
| 696 | /* XXX */ |
| 697 | } else { |
| 698 | /* Reset Bus Arbiter */ |
| 699 | tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA; |
| 700 | /* Enable Bus Arbiter */ |
| 701 | tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN; |
| 702 | } |
| 703 | |
| 704 | tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | |
| 705 | PCI_COMMAND_MEMORY | |
| 706 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; |
| 707 | |
| 708 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, |
| 709 | ":pci setup complete:\n"); |
| 710 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n"); |
| 711 | } |
| 712 | |
| 713 | #endif /* CONFIG_PCI */ |
| 714 | |
| 715 | void toshiba_rbtx4927_restart(char *command) |
| 716 | { |
| 717 | printk(KERN_NOTICE "System Rebooting...\n"); |
| 718 | |
| 719 | /* enable the s/w reset register */ |
| 720 | reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET); |
| 721 | |
| 722 | /* wait for enable to be seen */ |
| 723 | while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) & |
| 724 | RBTX4927_SW_RESET_ENABLE_SET) == 0x00); |
| 725 | |
| 726 | /* do a s/w reset */ |
| 727 | reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET); |
| 728 | |
| 729 | /* do something passive while waiting for reset */ |
| 730 | local_irq_disable(); |
| 731 | while (1) |
| 732 | asm_wait(); |
| 733 | |
| 734 | /* no return */ |
| 735 | } |
| 736 | |
| 737 | |
| 738 | void toshiba_rbtx4927_halt(void) |
| 739 | { |
| 740 | printk(KERN_NOTICE "System Halted\n"); |
| 741 | local_irq_disable(); |
| 742 | while (1) { |
| 743 | asm_wait(); |
| 744 | } |
| 745 | /* no return */ |
| 746 | } |
| 747 | |
| 748 | void toshiba_rbtx4927_power_off(void) |
| 749 | { |
| 750 | toshiba_rbtx4927_halt(); |
| 751 | /* no return */ |
| 752 | } |
| 753 | |
| 754 | void __init toshiba_rbtx4927_setup(void) |
| 755 | { |
| 756 | vu32 cp0_config; |
| 757 | char *argptr; |
| 758 | |
| 759 | printk("CPU is %s\n", toshiba_name); |
| 760 | |
| 761 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
| 762 | "-\n"); |
| 763 | |
| 764 | /* f/w leaves this on at startup */ |
| 765 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
| 766 | ":Clearing STO_ERL.\n"); |
| 767 | clear_c0_status(ST0_ERL); |
| 768 | |
| 769 | /* enable caches -- HCP5 does this, pmon does not */ |
| 770 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
| 771 | ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n"); |
| 772 | cp0_config = read_c0_config(); |
| 773 | cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); |
| 774 | write_c0_config(cp0_config); |
| 775 | |
| 776 | #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG |
| 777 | { |
| 778 | extern void dump_cp0(char *); |
| 779 | dump_cp0("toshiba_rbtx4927_early_fw_fixup"); |
| 780 | } |
| 781 | #endif |
| 782 | |
| 783 | /* setup irq stuff */ |
| 784 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
| 785 | ":Setting up tx4927 pic.\n"); |
| 786 | TX4927_WR(0xff1ff604, 0x00000400); /* irq trigger */ |
| 787 | TX4927_WR(0xff1ff608, 0x00000000); /* irq trigger */ |
| 788 | |
| 789 | /* setup serial stuff */ |
| 790 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
| 791 | ":Setting up tx4927 sio.\n"); |
| 792 | TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */ |
| 793 | TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */ |
| 794 | |
| 795 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
| 796 | "+\n"); |
| 797 | |
| 798 | set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); |
| 799 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
| 800 | ":mips_io_port_base=0x%08lx\n", |
| 801 | mips_io_port_base); |
| 802 | |
| 803 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
| 804 | ":Resource\n"); |
| 805 | ioport_resource.end = 0xffffffff; |
| 806 | iomem_resource.end = 0xffffffff; |
| 807 | |
| 808 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
| 809 | ":ResetRoutines\n"); |
| 810 | _machine_restart = toshiba_rbtx4927_restart; |
| 811 | _machine_halt = toshiba_rbtx4927_halt; |
| 812 | _machine_power_off = toshiba_rbtx4927_power_off; |
| 813 | |
| 814 | #ifdef CONFIG_PCI |
| 815 | |
| 816 | /* PCIC */ |
| 817 | /* |
| 818 | * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. |
| 819 | * PCIDIVMODE[12:11]'s initial value are given by S9[4:3] (ON:0, OFF:1). |
| 820 | * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) |
| 821 | * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) |
| 822 | * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) |
| 823 | * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) |
| 824 | * i.e. S9[3]: ON (83MHz), OFF (100MHz) |
| 825 | */ |
| 826 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, |
| 827 | "ccfg is %lx, DIV is %x\n", |
| 828 | (unsigned long) tx4927_ccfgptr-> |
| 829 | ccfg, TX4927_CCFG_PCIDIVMODE_MASK); |
| 830 | |
| 831 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, |
| 832 | "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n", |
| 833 | (unsigned long) tx4927_ccfgptr-> |
| 834 | ccfg & TX4927_CCFG_PCI66, |
| 835 | (unsigned long) tx4927_ccfgptr-> |
| 836 | ccfg & TX4927_CCFG_PCIMIDE, |
| 837 | (unsigned long) tx4927_ccfgptr-> |
| 838 | ccfg & TX4927_CCFG_PCIXARB); |
| 839 | |
| 840 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, |
| 841 | "PCIDIVMODE is %lx\n", |
| 842 | (unsigned long) tx4927_ccfgptr-> |
| 843 | ccfg & TX4927_CCFG_PCIDIVMODE_MASK); |
| 844 | |
| 845 | switch ((unsigned long) tx4927_ccfgptr-> |
| 846 | ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { |
| 847 | case TX4927_CCFG_PCIDIVMODE_2_5: |
| 848 | case TX4927_CCFG_PCIDIVMODE_5: |
| 849 | tx4927_cpu_clock = 166000000; /* 166MHz */ |
| 850 | break; |
| 851 | default: |
| 852 | tx4927_cpu_clock = 200000000; /* 200MHz */ |
| 853 | } |
| 854 | |
| 855 | /* CCFG */ |
| 856 | /* enable Timeout BusError */ |
| 857 | if (tx4927_ccfg_toeon) |
| 858 | tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; |
| 859 | |
| 860 | /* SDRAMC fixup */ |
| 861 | #ifdef CONFIG_TX4927BUG_WORKAROUND |
| 862 | /* |
| 863 | * TX4927-BUG: INF 01-01-18/ BUG 01-01-22 |
| 864 | * G-bus timeout error detection is incorrect |
| 865 | */ |
| 866 | if (tx4927_ccfg_toeon) |
| 867 | tx4927_sdramcptr->tr |= 0x02000000; /* RCD:3tck */ |
| 868 | #endif |
| 869 | |
| 870 | tx4927_pci_setup(); |
| 871 | if (tx4927_using_backplane == 1) |
| 872 | printk("backplane board IS installed\n"); |
| 873 | else |
| 874 | printk("No Backplane \n"); |
| 875 | |
| 876 | /* this is on ISA bus behind PCI bus, so need PCI up first */ |
| 877 | #ifdef CONFIG_TOSHIBA_FPCIB0 |
| 878 | { |
| 879 | if (tx4927_using_backplane) { |
| 880 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 881 | (TOSHIBA_RBTX4927_SETUP_SETUP, |
| 882 | ":fpcibo=yes\n"); |
| 883 | |
| 884 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 885 | (TOSHIBA_RBTX4927_SETUP_SETUP, |
| 886 | ":smsc_fdc37m81x_init()\n"); |
| 887 | smsc_fdc37m81x_init(0x3f0); |
| 888 | |
| 889 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 890 | (TOSHIBA_RBTX4927_SETUP_SETUP, |
| 891 | ":smsc_fdc37m81x_config_beg()\n"); |
| 892 | smsc_fdc37m81x_config_beg(); |
| 893 | |
| 894 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 895 | (TOSHIBA_RBTX4927_SETUP_SETUP, |
| 896 | ":smsc_fdc37m81x_config_set(KBD)\n"); |
| 897 | smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, |
| 898 | SMSC_FDC37M81X_KBD); |
| 899 | smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); |
| 900 | smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); |
| 901 | smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, |
| 902 | 1); |
| 903 | |
| 904 | smsc_fdc37m81x_config_end(); |
| 905 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 906 | (TOSHIBA_RBTX4927_SETUP_SETUP, |
| 907 | ":smsc_fdc37m81x_config_end()\n"); |
| 908 | } else { |
| 909 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 910 | (TOSHIBA_RBTX4927_SETUP_SETUP, |
| 911 | ":fpcibo=not_found\n"); |
| 912 | } |
| 913 | } |
| 914 | #else |
| 915 | { |
| 916 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 917 | (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n"); |
| 918 | } |
| 919 | #endif |
| 920 | |
| 921 | #endif /* CONFIG_PCI */ |
| 922 | |
| 923 | #ifdef CONFIG_SERIAL_TXX9_CONSOLE |
| 924 | argptr = prom_getcmdline(); |
| 925 | if (strstr(argptr, "console=") == NULL) { |
| 926 | strcat(argptr, " console=ttyS0,38400"); |
| 927 | } |
| 928 | #endif |
| 929 | |
| 930 | #ifdef CONFIG_ROOT_NFS |
| 931 | argptr = prom_getcmdline(); |
| 932 | if (strstr(argptr, "root=") == NULL) { |
| 933 | strcat(argptr, " root=/dev/nfs rw"); |
| 934 | } |
| 935 | #endif |
| 936 | |
| 937 | |
| 938 | #ifdef CONFIG_IP_PNP |
| 939 | argptr = prom_getcmdline(); |
| 940 | if (strstr(argptr, "ip=") == NULL) { |
| 941 | strcat(argptr, " ip=any"); |
| 942 | } |
| 943 | #endif |
| 944 | |
| 945 | |
| 946 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
| 947 | "+\n"); |
| 948 | } |
| 949 | |
| 950 | #ifdef CONFIG_RTC_DS1742 |
| 951 | extern unsigned long rtc_ds1742_get_time(void); |
| 952 | extern int rtc_ds1742_set_time(unsigned long); |
| 953 | extern void rtc_ds1742_wait(void); |
| 954 | #endif |
| 955 | |
| 956 | void __init |
| 957 | toshiba_rbtx4927_time_init(void) |
| 958 | { |
| 959 | u32 c1; |
| 960 | u32 c2; |
| 961 | |
| 962 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n"); |
| 963 | |
| 964 | #ifdef CONFIG_RTC_DS1742 |
| 965 | |
| 966 | rtc_get_time = rtc_ds1742_get_time; |
| 967 | rtc_set_time = rtc_ds1742_set_time; |
| 968 | |
| 969 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, |
| 970 | ":rtc_ds1742_init()-\n"); |
| 971 | rtc_ds1742_init(0xbc010000); |
| 972 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, |
| 973 | ":rtc_ds1742_init()+\n"); |
| 974 | |
| 975 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, |
| 976 | ":Calibrate mips_hpt_frequency-\n"); |
| 977 | rtc_ds1742_wait(); |
| 978 | |
| 979 | /* get the count */ |
| 980 | c1 = read_c0_count(); |
| 981 | |
| 982 | /* wait for the seconds to change again */ |
| 983 | rtc_ds1742_wait(); |
| 984 | |
| 985 | /* get the count again */ |
| 986 | c2 = read_c0_count(); |
| 987 | |
| 988 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, |
| 989 | ":Calibrate mips_hpt_frequency+\n"); |
| 990 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, |
| 991 | ":c1=%12u\n", c1); |
| 992 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, |
| 993 | ":c2=%12u\n", c2); |
| 994 | |
| 995 | /* this diff is as close as we are going to get to counter ticks per sec */ |
| 996 | mips_hpt_frequency = abs(c2 - c1); |
| 997 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, |
| 998 | ":f1=%12u\n", mips_hpt_frequency); |
| 999 | |
| 1000 | /* round to 1/10th of a MHz */ |
| 1001 | mips_hpt_frequency /= (100 * 1000); |
| 1002 | mips_hpt_frequency *= (100 * 1000); |
| 1003 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, |
| 1004 | ":f2=%12u\n", mips_hpt_frequency); |
| 1005 | |
| 1006 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO, |
| 1007 | ":mips_hpt_frequency=%uHz (%uMHz)\n", |
| 1008 | mips_hpt_frequency, |
| 1009 | mips_hpt_frequency / 1000000); |
| 1010 | #else |
| 1011 | mips_hpt_frequency = 100000000; |
| 1012 | #endif |
| 1013 | |
| 1014 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n"); |
| 1015 | |
| 1016 | } |
| 1017 | |
| 1018 | void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq) |
| 1019 | { |
| 1020 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP, |
| 1021 | "-\n"); |
| 1022 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP, |
| 1023 | "+\n"); |
| 1024 | } |