| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * arch/ppc/platforms/cpci405.c |
| 3 | * |
| 4 | * Board setup routines for the esd CPCI-405 cPCI Board. |
| 5 | * |
| 6 | * Author: Stefan Roese |
| 7 | * stefan.roese@esd-electronics.com |
| 8 | * |
| 9 | * Copyright 2001 esd electronic system design - hannover germany |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the |
| 13 | * Free Software Foundation; either version 2 of the License, or (at your |
| 14 | * option) any later version. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/config.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <asm/system.h> |
| 22 | #include <asm/pci-bridge.h> |
| 23 | #include <asm/machdep.h> |
| 24 | #include <asm/todc.h> |
| 25 | #include <asm/ocp.h> |
| 26 | |
| 27 | void *cpci405_nvram; |
| 28 | |
| 29 | /* |
| 30 | * Some IRQs unique to CPCI-405. |
| 31 | */ |
| 32 | int __init |
| 33 | ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) |
| 34 | { |
| 35 | static char pci_irq_table[][4] = |
| 36 | /* |
| 37 | * PCI IDSEL/INTPIN->INTLINE |
| 38 | * A B C D |
| 39 | */ |
| 40 | { |
| 41 | {28, 28, 28, 28}, /* IDSEL 15 - cPCI slot 8 */ |
| 42 | {29, 29, 29, 29}, /* IDSEL 16 - cPCI slot 7 */ |
| 43 | {30, 30, 30, 30}, /* IDSEL 17 - cPCI slot 6 */ |
| 44 | {27, 27, 27, 27}, /* IDSEL 18 - cPCI slot 5 */ |
| 45 | {28, 28, 28, 28}, /* IDSEL 19 - cPCI slot 4 */ |
| 46 | {29, 29, 29, 29}, /* IDSEL 20 - cPCI slot 3 */ |
| 47 | {30, 30, 30, 30}, /* IDSEL 21 - cPCI slot 2 */ |
| 48 | }; |
| 49 | const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4; |
| 50 | return PCI_IRQ_TABLE_LOOKUP; |
| 51 | }; |
| 52 | |
| 53 | void __init |
| 54 | cpci405_setup_arch(void) |
| 55 | { |
| 56 | ppc4xx_setup_arch(); |
| 57 | |
| 58 | ibm_ocp_set_emac(0, 0); |
| 59 | |
| 60 | TODC_INIT(TODC_TYPE_MK48T35, cpci405_nvram, cpci405_nvram, cpci405_nvram, 8); |
| 61 | } |
| 62 | |
| 63 | void __init |
| 64 | cpci405_map_io(void) |
| 65 | { |
| 66 | ppc4xx_map_io(); |
| 67 | cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE); |
| 68 | } |
| 69 | |
| 70 | void __init |
| 71 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, |
| 72 | unsigned long r6, unsigned long r7) |
| 73 | { |
| 74 | ppc4xx_init(r3, r4, r5, r6, r7); |
| 75 | |
| 76 | ppc_md.setup_arch = cpci405_setup_arch; |
| 77 | ppc_md.setup_io_mappings = cpci405_map_io; |
| 78 | |
| 79 | ppc_md.time_init = todc_time_init; |
| 80 | ppc_md.set_rtc_time = todc_set_rtc_time; |
| 81 | ppc_md.get_rtc_time = todc_get_rtc_time; |
| 82 | ppc_md.nvram_read_val = todc_direct_read_val; |
| 83 | ppc_md.nvram_write_val = todc_direct_write_val; |
| 84 | } |