Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 / . / arch / ppc / platforms / 4xx / ibm440gp.c
blob: 27615ef8309ccf1230421840e00e7b3a7f3646ae [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame^]1/*
2 * arch/ppc/platforms/4xx/ibm440gp.c
3 *
4 * PPC440GP I/O descriptions
5 *
6 * Matt Porter <mporter@mvista.com>
7 * Copyright 2002-2004 MontaVista Software Inc.
8 *
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18#include <linux/init.h>
19#include <linux/module.h>
20#include <platforms/4xx/ibm440gp.h>
21#include <asm/ocp.h>
22#include <asm/ppc4xx_pic.h>
23
24static struct ocp_func_emac_data ibm440gp_emac0_def = {
25 .rgmii_idx = -1, /* No RGMII */
26 .rgmii_mux = -1, /* No RGMII */
27 .zmii_idx = 0, /* ZMII device index */
28 .zmii_mux = 0, /* ZMII input of this EMAC */
29 .mal_idx = 0, /* MAL device index */
30 .mal_rx_chan = 0, /* MAL rx channel number */
31 .mal_tx_chan = 0, /* MAL tx channel number */
32 .wol_irq = 61, /* WOL interrupt number */
33 .mdio_idx = -1, /* No shared MDIO */
34 .tah_idx = -1, /* No TAH */
35};
36
37static struct ocp_func_emac_data ibm440gp_emac1_def = {
38 .rgmii_idx = -1, /* No RGMII */
39 .rgmii_mux = -1, /* No RGMII */
40 .zmii_idx = 0, /* ZMII device index */
41 .zmii_mux = 1, /* ZMII input of this EMAC */
42 .mal_idx = 0, /* MAL device index */
43 .mal_rx_chan = 1, /* MAL rx channel number */
44 .mal_tx_chan = 2, /* MAL tx channel number */
45 .wol_irq = 63, /* WOL interrupt number */
46 .mdio_idx = -1, /* No shared MDIO */
47 .tah_idx = -1, /* No TAH */
48};
49OCP_SYSFS_EMAC_DATA()
50
51static struct ocp_func_mal_data ibm440gp_mal0_def = {
52 .num_tx_chans = 4, /* Number of TX channels */
53 .num_rx_chans = 2, /* Number of RX channels */
54 .txeob_irq = 10, /* TX End Of Buffer IRQ */
55 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
56 .txde_irq = 33, /* TX Descriptor Error IRQ */
57 .rxde_irq = 34, /* RX Descriptor Error IRQ */
58 .serr_irq = 32, /* MAL System Error IRQ */
59};
60OCP_SYSFS_MAL_DATA()
61
62static struct ocp_func_iic_data ibm440gp_iic0_def = {
63 .fast_mode = 0, /* Use standad mode (100Khz) */
64};
65
66static struct ocp_func_iic_data ibm440gp_iic1_def = {
67 .fast_mode = 0, /* Use standad mode (100Khz) */
68};
69OCP_SYSFS_IIC_DATA()
70
71struct ocp_def core_ocp[] = {
72 { .vendor = OCP_VENDOR_IBM,
73 .function = OCP_FUNC_OPB,
74 .index = 0,
75 .paddr = 0x0000000140000000ULL,
76 .irq = OCP_IRQ_NA,
77 .pm = OCP_CPM_NA,
78 },
79 { .vendor = OCP_VENDOR_IBM,
80 .function = OCP_FUNC_16550,
81 .index = 0,
82 .paddr = PPC440GP_UART0_ADDR,
83 .irq = UART0_INT,
84 .pm = IBM_CPM_UART0,
85 },
86 { .vendor = OCP_VENDOR_IBM,
87 .function = OCP_FUNC_16550,
88 .index = 1,
89 .paddr = PPC440GP_UART1_ADDR,
90 .irq = UART1_INT,
91 .pm = IBM_CPM_UART1,
92 },
93 { .vendor = OCP_VENDOR_IBM,
94 .function = OCP_FUNC_IIC,
95 .index = 0,
96 .paddr = 0x0000000140000400ULL,
97 .irq = 2,
98 .pm = IBM_CPM_IIC0,
99 .additions = &ibm440gp_iic0_def,
100 .show = &ocp_show_iic_data
101 },
102 { .vendor = OCP_VENDOR_IBM,
103 .function = OCP_FUNC_IIC,
104 .index = 1,
105 .paddr = 0x0000000140000500ULL,
106 .irq = 3,
107 .pm = IBM_CPM_IIC1,
108 .additions = &ibm440gp_iic1_def,
109 .show = &ocp_show_iic_data
110 },
111 { .vendor = OCP_VENDOR_IBM,
112 .function = OCP_FUNC_GPIO,
113 .index = 0,
114 .paddr = 0x0000000140000700ULL,
115 .irq = OCP_IRQ_NA,
116 .pm = IBM_CPM_GPIO0,
117 },
118 { .vendor = OCP_VENDOR_IBM,
119 .function = OCP_FUNC_MAL,
120 .paddr = OCP_PADDR_NA,
121 .irq = OCP_IRQ_NA,
122 .pm = OCP_CPM_NA,
123 .additions = &ibm440gp_mal0_def,
124 .show = &ocp_show_mal_data,
125 },
126 { .vendor = OCP_VENDOR_IBM,
127 .function = OCP_FUNC_EMAC,
128 .index = 0,
129 .paddr = 0x0000000140000800ULL,
130 .irq = 60,
131 .pm = OCP_CPM_NA,
132 .additions = &ibm440gp_emac0_def,
133 .show = &ocp_show_emac_data,
134 },
135 { .vendor = OCP_VENDOR_IBM,
136 .function = OCP_FUNC_EMAC,
137 .index = 1,
138 .paddr = 0x0000000140000900ULL,
139 .irq = 62,
140 .pm = OCP_CPM_NA,
141 .additions = &ibm440gp_emac1_def,
142 .show = &ocp_show_emac_data,
143 },
144 { .vendor = OCP_VENDOR_IBM,
145 .function = OCP_FUNC_ZMII,
146 .paddr = 0x0000000140000780ULL,
147 .irq = OCP_IRQ_NA,
148 .pm = OCP_CPM_NA,
149 },
150 { .vendor = OCP_VENDOR_INVALID
151 }
152};
153
154/* Polarity and triggering settings for internal interrupt sources */
155struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
156 { .polarity = 0xfffffe03,
157 .triggering = 0x01c00000,
158 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
159 },
160 { .polarity = 0xffffc0ff,
161 .triggering = 0x00ff8000,
162 .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
163 },
164};