Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * arch/ppc/platform/85xx/mpc85xx_cds_common.c |
| 3 | * |
| 4 | * MPC85xx CDS board specific routines |
| 5 | * |
| 6 | * Maintainer: Kumar Gala <kumar.gala@freescale.com> |
| 7 | * |
| 8 | * Copyright 2004 Freescale Semiconductor, Inc |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License as published by the |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your |
| 13 | * option) any later version. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/config.h> |
| 17 | #include <linux/stddef.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/reboot.h> |
| 22 | #include <linux/pci.h> |
| 23 | #include <linux/kdev_t.h> |
| 24 | #include <linux/major.h> |
| 25 | #include <linux/console.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/irq.h> |
| 28 | #include <linux/seq_file.h> |
| 29 | #include <linux/serial.h> |
| 30 | #include <linux/module.h> |
| 31 | #include <linux/root_dev.h> |
| 32 | #include <linux/initrd.h> |
| 33 | #include <linux/tty.h> |
| 34 | #include <linux/serial_core.h> |
| 35 | #include <linux/fsl_devices.h> |
| 36 | |
| 37 | #include <asm/system.h> |
| 38 | #include <asm/pgtable.h> |
| 39 | #include <asm/page.h> |
| 40 | #include <asm/atomic.h> |
| 41 | #include <asm/time.h> |
| 42 | #include <asm/todc.h> |
| 43 | #include <asm/io.h> |
| 44 | #include <asm/machdep.h> |
| 45 | #include <asm/prom.h> |
| 46 | #include <asm/open_pic.h> |
| 47 | #include <asm/bootinfo.h> |
| 48 | #include <asm/pci-bridge.h> |
| 49 | #include <asm/mpc85xx.h> |
| 50 | #include <asm/irq.h> |
| 51 | #include <asm/immap_85xx.h> |
| 52 | #include <asm/immap_cpm2.h> |
| 53 | #include <asm/ppc_sys.h> |
| 54 | #include <asm/kgdb.h> |
| 55 | |
| 56 | #include <mm/mmu_decl.h> |
| 57 | #include <syslib/cpm2_pic.h> |
| 58 | #include <syslib/ppc85xx_common.h> |
| 59 | #include <syslib/ppc85xx_setup.h> |
| 60 | |
| 61 | |
| 62 | #ifndef CONFIG_PCI |
| 63 | unsigned long isa_io_base = 0; |
| 64 | unsigned long isa_mem_base = 0; |
| 65 | #endif |
| 66 | |
| 67 | extern unsigned long total_memory; /* in mm/init */ |
| 68 | |
| 69 | unsigned char __res[sizeof (bd_t)]; |
| 70 | |
| 71 | static int cds_pci_slot = 2; |
| 72 | static volatile u8 * cadmus; |
| 73 | |
| 74 | /* Internal interrupts are all Level Sensitive, and Positive Polarity */ |
| 75 | |
| 76 | static u_char mpc85xx_cds_openpic_initsenses[] __initdata = { |
| 77 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */ |
| 78 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */ |
| 79 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */ |
| 80 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */ |
| 81 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */ |
| 82 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */ |
| 83 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */ |
| 84 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */ |
| 85 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */ |
| 86 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */ |
| 87 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */ |
| 88 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */ |
| 89 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */ |
| 90 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */ |
| 91 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */ |
| 92 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */ |
| 93 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */ |
| 94 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */ |
| 95 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */ |
| 96 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */ |
| 97 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */ |
| 98 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */ |
| 99 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */ |
| 100 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */ |
| 101 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */ |
| 102 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */ |
| 103 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */ |
| 104 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */ |
| 105 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */ |
| 106 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */ |
| 107 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */ |
| 108 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */ |
| 109 | #if defined(CONFIG_PCI) |
| 110 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */ |
| 111 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */ |
| 112 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */ |
| 113 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */ |
| 114 | #else |
| 115 | 0x0, /* External 0: */ |
| 116 | 0x0, /* External 1: */ |
| 117 | 0x0, /* External 2: */ |
| 118 | 0x0, /* External 3: */ |
| 119 | #endif |
| 120 | 0x0, /* External 4: */ |
| 121 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */ |
| 122 | 0x0, /* External 6: */ |
| 123 | 0x0, /* External 7: */ |
| 124 | 0x0, /* External 8: */ |
| 125 | 0x0, /* External 9: */ |
| 126 | 0x0, /* External 10: */ |
| 127 | #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI) |
| 128 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */ |
| 129 | #else |
| 130 | 0x0, /* External 11: */ |
| 131 | #endif |
| 132 | }; |
| 133 | |
| 134 | /* ************************************************************************ */ |
| 135 | int |
| 136 | mpc85xx_cds_show_cpuinfo(struct seq_file *m) |
| 137 | { |
| 138 | uint pvid, svid, phid1; |
| 139 | uint memsize = total_memory; |
| 140 | bd_t *binfo = (bd_t *) __res; |
| 141 | unsigned int freq; |
| 142 | |
| 143 | /* get the core frequency */ |
| 144 | freq = binfo->bi_intfreq; |
| 145 | |
| 146 | pvid = mfspr(SPRN_PVR); |
| 147 | svid = mfspr(SPRN_SVR); |
| 148 | |
| 149 | seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); |
| 150 | seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]); |
| 151 | seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000); |
| 152 | seq_printf(m, "PVR\t\t: 0x%x\n", pvid); |
| 153 | seq_printf(m, "SVR\t\t: 0x%x\n", svid); |
| 154 | |
| 155 | /* Display cpu Pll setting */ |
| 156 | phid1 = mfspr(SPRN_HID1); |
| 157 | seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); |
| 158 | |
| 159 | /* Display the amount of memory */ |
| 160 | seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); |
| 161 | |
| 162 | return 0; |
| 163 | } |
| 164 | |
| 165 | #ifdef CONFIG_CPM2 |
| 166 | static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs) |
| 167 | { |
| 168 | while((irq = cpm2_get_irq(regs)) >= 0) |
| 169 | __do_IRQ(irq, regs); |
| 170 | } |
| 171 | |
| 172 | static struct irqaction cpm2_irqaction = { |
| 173 | .handler = cpm2_cascade, |
| 174 | .flags = SA_INTERRUPT, |
| 175 | .mask = CPU_MASK_NONE, |
| 176 | .name = "cpm2_cascade", |
| 177 | }; |
| 178 | #endif /* CONFIG_CPM2 */ |
| 179 | |
| 180 | void __init |
| 181 | mpc85xx_cds_init_IRQ(void) |
| 182 | { |
| 183 | bd_t *binfo = (bd_t *) __res; |
| 184 | |
| 185 | /* Determine the Physical Address of the OpenPIC regs */ |
| 186 | phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; |
| 187 | OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE); |
| 188 | OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses; |
| 189 | OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses); |
| 190 | |
| 191 | /* Skip reserved space and internal sources */ |
| 192 | openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); |
| 193 | /* Map PIC IRQs 0-11 */ |
| 194 | openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000); |
| 195 | |
| 196 | /* we let openpic interrupts starting from an offset, to |
| 197 | * leave space for cascading interrupts underneath. |
| 198 | */ |
| 199 | openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET); |
| 200 | |
| 201 | #ifdef CONFIG_CPM2 |
| 202 | /* Setup CPM2 PIC */ |
| 203 | cpm2_init_IRQ(); |
| 204 | |
| 205 | setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction); |
| 206 | #endif |
| 207 | |
| 208 | return; |
| 209 | } |
| 210 | |
| 211 | #ifdef CONFIG_PCI |
| 212 | /* |
| 213 | * interrupt routing |
| 214 | */ |
| 215 | int |
| 216 | mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) |
| 217 | { |
| 218 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); |
| 219 | |
| 220 | if (!hose->index) |
| 221 | { |
| 222 | /* Handle PCI1 interrupts */ |
| 223 | char pci_irq_table[][4] = |
| 224 | /* |
| 225 | * PCI IDSEL/INTPIN->INTLINE |
| 226 | * A B C D |
| 227 | */ |
| 228 | |
| 229 | /* Note IRQ assignment for slots is based on which slot the elysium is |
| 230 | * in -- in this setup elysium is in slot #2 (this PIRQA as first |
| 231 | * interrupt on slot */ |
| 232 | { |
| 233 | { 0, 1, 2, 3 }, /* 16 - PMC */ |
| 234 | { 3, 0, 0, 0 }, /* 17 P2P (Tsi320) */ |
| 235 | { 0, 1, 2, 3 }, /* 18 - Slot 1 */ |
| 236 | { 1, 2, 3, 0 }, /* 19 - Slot 2 */ |
| 237 | { 2, 3, 0, 1 }, /* 20 - Slot 3 */ |
| 238 | { 3, 0, 1, 2 }, /* 21 - Slot 4 */ |
| 239 | }; |
| 240 | |
| 241 | const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4; |
| 242 | int i, j; |
| 243 | |
| 244 | for (i = 0; i < 6; i++) |
| 245 | for (j = 0; j < 4; j++) |
| 246 | pci_irq_table[i][j] = |
| 247 | ((pci_irq_table[i][j] + 5 - |
| 248 | cds_pci_slot) & 0x3) + PIRQ0A; |
| 249 | |
| 250 | return PCI_IRQ_TABLE_LOOKUP; |
| 251 | } else { |
| 252 | /* Handle PCI2 interrupts (if we have one) */ |
| 253 | char pci_irq_table[][4] = |
| 254 | { |
| 255 | /* |
| 256 | * We only have one slot and one interrupt |
| 257 | * going to PIRQA - PIRQD */ |
| 258 | { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */ |
| 259 | }; |
| 260 | |
| 261 | const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4; |
| 262 | |
| 263 | return PCI_IRQ_TABLE_LOOKUP; |
| 264 | } |
| 265 | } |
| 266 | |
| 267 | #define ARCADIA_HOST_BRIDGE_IDSEL 17 |
| 268 | #define ARCADIA_2ND_BRIDGE_IDSEL 3 |
| 269 | |
| 270 | extern int mpc85xx_pci1_last_busno; |
| 271 | |
| 272 | int |
| 273 | mpc85xx_exclude_device(u_char bus, u_char devfn) |
| 274 | { |
| 275 | if (bus == 0 && PCI_SLOT(devfn) == 0) |
| 276 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 277 | #ifdef CONFIG_85xx_PCI2 |
| 278 | if (mpc85xx_pci1_last_busno) |
| 279 | if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0) |
| 280 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 281 | #endif |
| 282 | /* We explicitly do not go past the Tundra 320 Bridge */ |
| 283 | if (bus == 1) |
| 284 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 285 | if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) |
| 286 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 287 | else |
| 288 | return PCIBIOS_SUCCESSFUL; |
| 289 | } |
| 290 | #endif /* CONFIG_PCI */ |
| 291 | |
| 292 | TODC_ALLOC(); |
| 293 | |
| 294 | /* ************************************************************************ |
| 295 | * |
| 296 | * Setup the architecture |
| 297 | * |
| 298 | */ |
| 299 | static void __init |
| 300 | mpc85xx_cds_setup_arch(void) |
| 301 | { |
| 302 | bd_t *binfo = (bd_t *) __res; |
| 303 | unsigned int freq; |
| 304 | struct gianfar_platform_data *pdata; |
| 305 | |
| 306 | /* get the core frequency */ |
| 307 | freq = binfo->bi_intfreq; |
| 308 | |
| 309 | printk("mpc85xx_cds_setup_arch\n"); |
| 310 | |
| 311 | #ifdef CONFIG_CPM2 |
| 312 | cpm2_reset(); |
| 313 | #endif |
| 314 | |
| 315 | cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE); |
| 316 | cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1; |
| 317 | printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot); |
| 318 | |
| 319 | /* Setup TODC access */ |
| 320 | TODC_INIT(TODC_TYPE_DS1743, |
| 321 | 0, |
| 322 | 0, |
| 323 | ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE), |
| 324 | 8); |
| 325 | |
| 326 | /* Set loops_per_jiffy to a half-way reasonable value, |
| 327 | for use until calibrate_delay gets called. */ |
| 328 | loops_per_jiffy = freq / HZ; |
| 329 | |
| 330 | #ifdef CONFIG_PCI |
| 331 | /* setup PCI host bridges */ |
| 332 | mpc85xx_setup_hose(); |
| 333 | #endif |
| 334 | |
| 335 | #ifdef CONFIG_SERIAL_8250 |
| 336 | mpc85xx_early_serial_map(); |
| 337 | #endif |
| 338 | |
| 339 | #ifdef CONFIG_SERIAL_TEXT_DEBUG |
| 340 | /* Invalidate the entry we stole earlier the serial ports |
| 341 | * should be properly mapped */ |
| 342 | invalidate_tlbcam_entry(NUM_TLBCAMS - 1); |
| 343 | #endif |
| 344 | |
| 345 | /* setup the board related information for the enet controllers */ |
| 346 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); |
| 347 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
| 348 | pdata->interruptPHY = MPC85xx_IRQ_EXT5; |
| 349 | pdata->phyid = 0; |
| 350 | /* fixup phy address */ |
| 351 | pdata->phy_reg_addr += binfo->bi_immr_base; |
| 352 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); |
| 353 | |
| 354 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); |
| 355 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
| 356 | pdata->interruptPHY = MPC85xx_IRQ_EXT5; |
| 357 | pdata->phyid = 1; |
| 358 | /* fixup phy address */ |
| 359 | pdata->phy_reg_addr += binfo->bi_immr_base; |
| 360 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); |
| 361 | |
| 362 | |
| 363 | #ifdef CONFIG_BLK_DEV_INITRD |
| 364 | if (initrd_start) |
| 365 | ROOT_DEV = Root_RAM0; |
| 366 | else |
| 367 | #endif |
| 368 | #ifdef CONFIG_ROOT_NFS |
| 369 | ROOT_DEV = Root_NFS; |
| 370 | #else |
| 371 | ROOT_DEV = Root_HDA1; |
| 372 | #endif |
| 373 | } |
| 374 | |
| 375 | /* ************************************************************************ */ |
| 376 | void __init |
| 377 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, |
| 378 | unsigned long r6, unsigned long r7) |
| 379 | { |
| 380 | /* parse_bootinfo must always be called first */ |
| 381 | parse_bootinfo(find_bootinfo()); |
| 382 | |
| 383 | /* |
| 384 | * If we were passed in a board information, copy it into the |
| 385 | * residual data area. |
| 386 | */ |
| 387 | if (r3) { |
| 388 | memcpy((void *) __res, (void *) (r3 + KERNELBASE), |
| 389 | sizeof (bd_t)); |
| 390 | |
| 391 | } |
| 392 | #ifdef CONFIG_SERIAL_TEXT_DEBUG |
| 393 | { |
| 394 | bd_t *binfo = (bd_t *) __res; |
| 395 | struct uart_port p; |
| 396 | |
| 397 | /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */ |
| 398 | settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base, |
| 399 | binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0); |
| 400 | |
| 401 | memset(&p, 0, sizeof (p)); |
| 402 | p.iotype = SERIAL_IO_MEM; |
| 403 | p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET; |
| 404 | p.uartclk = binfo->bi_busfreq; |
| 405 | |
| 406 | gen550_init(0, &p); |
| 407 | |
| 408 | memset(&p, 0, sizeof (p)); |
| 409 | p.iotype = SERIAL_IO_MEM; |
| 410 | p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET; |
| 411 | p.uartclk = binfo->bi_busfreq; |
| 412 | |
| 413 | gen550_init(1, &p); |
| 414 | } |
| 415 | #endif |
| 416 | |
| 417 | #if defined(CONFIG_BLK_DEV_INITRD) |
| 418 | /* |
| 419 | * If the init RAM disk has been configured in, and there's a valid |
| 420 | * starting address for it, set it up. |
| 421 | */ |
| 422 | if (r4) { |
| 423 | initrd_start = r4 + KERNELBASE; |
| 424 | initrd_end = r5 + KERNELBASE; |
| 425 | } |
| 426 | #endif /* CONFIG_BLK_DEV_INITRD */ |
| 427 | |
| 428 | /* Copy the kernel command line arguments to a safe place. */ |
| 429 | |
| 430 | if (r6) { |
| 431 | *(char *) (r7 + KERNELBASE) = 0; |
| 432 | strcpy(cmd_line, (char *) (r6 + KERNELBASE)); |
| 433 | } |
| 434 | |
| 435 | identify_ppc_sys_by_id(mfspr(SPRN_SVR)); |
| 436 | |
| 437 | /* setup the PowerPC module struct */ |
| 438 | ppc_md.setup_arch = mpc85xx_cds_setup_arch; |
| 439 | ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo; |
| 440 | |
| 441 | ppc_md.init_IRQ = mpc85xx_cds_init_IRQ; |
| 442 | ppc_md.get_irq = openpic_get_irq; |
| 443 | |
| 444 | ppc_md.restart = mpc85xx_restart; |
| 445 | ppc_md.power_off = mpc85xx_power_off; |
| 446 | ppc_md.halt = mpc85xx_halt; |
| 447 | |
| 448 | ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory; |
| 449 | |
| 450 | ppc_md.calibrate_decr = mpc85xx_calibrate_decr; |
| 451 | |
| 452 | ppc_md.time_init = todc_time_init; |
| 453 | ppc_md.set_rtc_time = todc_set_rtc_time; |
| 454 | ppc_md.get_rtc_time = todc_get_rtc_time; |
| 455 | |
| 456 | ppc_md.nvram_read_val = todc_direct_read_val; |
| 457 | ppc_md.nvram_write_val = todc_direct_write_val; |
| 458 | |
| 459 | #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG) |
| 460 | ppc_md.progress = gen550_progress; |
| 461 | #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */ |
| 462 | |
| 463 | if (ppc_md.progress) |
| 464 | ppc_md.progress("mpc85xx_cds_init(): exit", 0); |
| 465 | |
| 466 | return; |
| 467 | } |