Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * arch/sh/boards/dreamcast/irq.c |
| 3 | * |
| 4 | * Holly IRQ support for the Sega Dreamcast. |
| 5 | * |
| 6 | * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> |
| 7 | * |
| 8 | * This file is part of the LinuxDC project (www.linuxdc.org) |
| 9 | * Released under the terms of the GNU GPL v2.0 |
| 10 | */ |
| 11 | |
| 12 | #include <linux/irq.h> |
| 13 | |
| 14 | #include <asm/io.h> |
| 15 | #include <asm/irq.h> |
| 16 | #include <asm/dreamcast/sysasic.h> |
| 17 | |
| 18 | /* Dreamcast System ASIC Hardware Events - |
| 19 | |
| 20 | The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving |
| 21 | hardware events from system peripherals and triggering an SH7750 IRQ. |
| 22 | Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are |
| 23 | set in the Event Mask Registers (EMRs). When a hardware event is |
| 24 | triggered, it's corresponding bit in the Event Status Registers (ESRs) |
| 25 | is set, and that bit should be rewritten to the ESR to acknowledge that |
| 26 | event. |
| 27 | |
| 28 | There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event |
| 29 | types can be found in include/asm-sh/dc_sysasic.h. There are three groups |
| 30 | of EMRs that parallel the ESRs. Each EMR group corresponds to an IRQ, so |
| 31 | 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928 triggers |
| 32 | IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9. |
| 33 | |
| 34 | In the kernel, these events are mapped to virtual IRQs so that drivers can |
| 35 | respond to them as they would a normal interrupt. In order to keep this |
| 36 | mapping simple, the events are mapped as: |
| 37 | |
| 38 | 6900/6910 - Events 0-31, IRQ 13 |
| 39 | 6904/6924 - Events 32-63, IRQ 11 |
| 40 | 6908/6938 - Events 64-95, IRQ 9 |
| 41 | |
| 42 | */ |
| 43 | |
| 44 | #define ESR_BASE 0x005f6900 /* Base event status register */ |
| 45 | #define EMR_BASE 0x005f6910 /* Base event mask register */ |
| 46 | |
| 47 | /* Helps us determine the EMR group that this event belongs to: 0 = 0x6910, |
| 48 | 1 = 0x6920, 2 = 0x6930; also determine the event offset */ |
| 49 | #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32) |
| 50 | |
| 51 | /* Return the hardware event's bit positon within the EMR/ESR */ |
| 52 | #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31) |
| 53 | |
| 54 | /* For each of these *_irq routines, the IRQ passed in is the virtual IRQ |
| 55 | (logically mapped to the corresponding bit for the hardware event). */ |
| 56 | |
| 57 | /* Disable the hardware event by masking its bit in its EMR */ |
| 58 | static inline void disable_systemasic_irq(unsigned int irq) |
| 59 | { |
| 60 | unsigned long flags; |
| 61 | __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); |
| 62 | __u32 mask; |
| 63 | |
| 64 | local_irq_save(flags); |
| 65 | mask = inl(emr); |
| 66 | mask &= ~(1 << EVENT_BIT(irq)); |
| 67 | outl(mask, emr); |
| 68 | local_irq_restore(flags); |
| 69 | } |
| 70 | |
| 71 | /* Enable the hardware event by setting its bit in its EMR */ |
| 72 | static inline void enable_systemasic_irq(unsigned int irq) |
| 73 | { |
| 74 | unsigned long flags; |
| 75 | __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); |
| 76 | __u32 mask; |
| 77 | |
| 78 | local_irq_save(flags); |
| 79 | mask = inl(emr); |
| 80 | mask |= (1 << EVENT_BIT(irq)); |
| 81 | outl(mask, emr); |
| 82 | local_irq_restore(flags); |
| 83 | } |
| 84 | |
| 85 | /* Acknowledge a hardware event by writing its bit back to its ESR */ |
| 86 | static void ack_systemasic_irq(unsigned int irq) |
| 87 | { |
| 88 | __u32 esr = ESR_BASE + (LEVEL(irq) << 2); |
| 89 | disable_systemasic_irq(irq); |
| 90 | outl((1 << EVENT_BIT(irq)), esr); |
| 91 | } |
| 92 | |
| 93 | /* After a IRQ has been ack'd and responded to, it needs to be renabled */ |
| 94 | static void end_systemasic_irq(unsigned int irq) |
| 95 | { |
| 96 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) |
| 97 | enable_systemasic_irq(irq); |
| 98 | } |
| 99 | |
| 100 | static unsigned int startup_systemasic_irq(unsigned int irq) |
| 101 | { |
| 102 | enable_systemasic_irq(irq); |
| 103 | |
| 104 | return 0; |
| 105 | } |
| 106 | |
| 107 | static void shutdown_systemasic_irq(unsigned int irq) |
| 108 | { |
| 109 | disable_systemasic_irq(irq); |
| 110 | } |
| 111 | |
| 112 | struct hw_interrupt_type systemasic_int = { |
| 113 | .typename = "System ASIC", |
| 114 | .startup = startup_systemasic_irq, |
| 115 | .shutdown = shutdown_systemasic_irq, |
| 116 | .enable = enable_systemasic_irq, |
| 117 | .disable = disable_systemasic_irq, |
| 118 | .ack = ack_systemasic_irq, |
| 119 | .end = end_systemasic_irq, |
| 120 | }; |
| 121 | |
| 122 | /* |
| 123 | * Map the hardware event indicated by the processor IRQ to a virtual IRQ. |
| 124 | */ |
| 125 | int systemasic_irq_demux(int irq) |
| 126 | { |
| 127 | __u32 emr, esr, status, level; |
| 128 | __u32 j, bit; |
| 129 | |
| 130 | switch (irq) { |
| 131 | case 13: |
| 132 | level = 0; |
| 133 | break; |
| 134 | case 11: |
| 135 | level = 1; |
| 136 | break; |
| 137 | case 9: |
| 138 | level = 2; |
| 139 | break; |
| 140 | default: |
| 141 | return irq; |
| 142 | } |
| 143 | emr = EMR_BASE + (level << 4) + (level << 2); |
| 144 | esr = ESR_BASE + (level << 2); |
| 145 | |
| 146 | /* Mask the ESR to filter any spurious, unwanted interrtupts */ |
| 147 | status = inl(esr); |
| 148 | status &= inl(emr); |
| 149 | |
| 150 | /* Now scan and find the first set bit as the event to map */ |
| 151 | for (bit = 1, j = 0; j < 32; bit <<= 1, j++) { |
| 152 | if (status & bit) { |
| 153 | irq = HW_EVENT_IRQ_BASE + j + (level << 5); |
| 154 | return irq; |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | /* Not reached */ |
| 159 | return irq; |
| 160 | } |