Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * linux/arch/sh/kernel/pci-hs7751rvoip.c |
| 3 | * |
| 4 | * Author: Ian DaSilva (idasilva@mvista.com) |
| 5 | * |
| 6 | * Highly leveraged from pci-bigsur.c, written by Dustin McIntire. |
| 7 | * |
| 8 | * May be copied or modified under the terms of the GNU General Public |
| 9 | * License. See linux/COPYING for more information. |
| 10 | * |
| 11 | * PCI initialization for the Renesas SH7751R HS7751RVoIP board |
| 12 | */ |
| 13 | |
| 14 | #include <linux/config.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/types.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/pci.h> |
| 20 | #include <linux/module.h> |
| 21 | |
| 22 | #include <asm/io.h> |
| 23 | #include "../../../drivers/pci/pci-sh7751.h" |
| 24 | #include <asm/hs7751rvoip/hs7751rvoip.h> |
| 25 | |
| 26 | #define PCIMCR_MRSET_OFF 0xBFFFFFFF |
| 27 | #define PCIMCR_RFSH_OFF 0xFFFFFFFB |
| 28 | |
| 29 | /* |
| 30 | * Only long word accesses of the PCIC's internal local registers and the |
| 31 | * configuration registers from the CPU is supported. |
| 32 | */ |
| 33 | #define PCIC_WRITE(x,v) writel((v), PCI_REG(x)) |
| 34 | #define PCIC_READ(x) readl(PCI_REG(x)) |
| 35 | |
| 36 | /* |
| 37 | * Description: This function sets up and initializes the pcic, sets |
| 38 | * up the BARS, maps the DRAM into the address space etc, etc. |
| 39 | */ |
| 40 | int __init pcibios_init_platform(void) |
| 41 | { |
| 42 | unsigned long bcr1, wcr1, wcr2, wcr3, mcr; |
| 43 | unsigned short bcr2, bcr3; |
| 44 | |
| 45 | /* |
| 46 | * Initialize the slave bus controller on the pcic. The values used |
| 47 | * here should not be hardcoded, but they should be taken from the bsc |
| 48 | * on the processor, to make this function as generic as possible. |
| 49 | * (i.e. Another sbc may usr different SDRAM timing settings -- in order |
| 50 | * for the pcic to work, its settings need to be exactly the same.) |
| 51 | */ |
| 52 | bcr1 = (*(volatile unsigned long *)(SH7751_BCR1)); |
| 53 | bcr2 = (*(volatile unsigned short *)(SH7751_BCR2)); |
| 54 | bcr3 = (*(volatile unsigned short *)(SH7751_BCR3)); |
| 55 | wcr1 = (*(volatile unsigned long *)(SH7751_WCR1)); |
| 56 | wcr2 = (*(volatile unsigned long *)(SH7751_WCR2)); |
| 57 | wcr3 = (*(volatile unsigned long *)(SH7751_WCR3)); |
| 58 | mcr = (*(volatile unsigned long *)(SH7751_MCR)); |
| 59 | |
| 60 | bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */ |
| 61 | (*(volatile unsigned long *)(SH7751_BCR1)) = bcr1; |
| 62 | |
| 63 | bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ |
| 64 | PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */ |
| 65 | PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */ |
| 66 | PCIC_WRITE(SH7751_PCIBCR3, bcr3); /* PCIC BCR3 */ |
| 67 | PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */ |
| 68 | PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */ |
| 69 | PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */ |
| 70 | mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; |
| 71 | PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */ |
| 72 | |
| 73 | /* Enable all interrupts, so we know what to fix */ |
| 74 | PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff); |
| 75 | PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f); |
| 76 | |
| 77 | /* Set up standard PCI config registers */ |
| 78 | PCIC_WRITE(SH7751_PCICONF1, 0xFB900047); /* Bus Master, Mem & I/O access */ |
| 79 | PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ |
| 80 | PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */ |
| 81 | PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */ |
| 82 | PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */ |
| 83 | PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */ |
| 84 | PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */ |
| 85 | PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */ |
| 86 | PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */ |
| 87 | PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */ |
| 88 | |
| 89 | /* Now turn it on... */ |
| 90 | PCIC_WRITE(SH7751_PCICR, 0xa5000001); |
| 91 | |
| 92 | /* |
| 93 | * Set PCIMBR and PCIIOBR here, assuming a single window |
| 94 | * (16M MEM, 256K IO) is enough. If a larger space is |
| 95 | * needed, the readx/writex and inx/outx functions will |
| 96 | * have to do more (e.g. setting registers for each call). |
| 97 | */ |
| 98 | |
| 99 | /* |
| 100 | * Set the MBR so PCI address is one-to-one with window, |
| 101 | * meaning all calls go straight through... use ifdef to |
| 102 | * catch erroneous assumption. |
| 103 | */ |
| 104 | BUG_ON(PCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE); |
| 105 | |
| 106 | PCIC_WRITE(SH7751_PCIMBR, PCIBIOS_MIN_MEM); |
| 107 | |
| 108 | /* Set IOBR for window containing area specified in pci.h */ |
| 109 | PCIC_WRITE(SH7751_PCIIOBR, (PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK)); |
| 110 | |
| 111 | /* All done, may as well say so... */ |
| 112 | printk("SH7751R PCI: Finished initialization of the PCI controller\n"); |
| 113 | |
| 114 | return 1; |
| 115 | } |
| 116 | |
| 117 | int __init pcibios_map_platform_irq(u8 slot, u8 pin) |
| 118 | { |
| 119 | switch (slot) { |
| 120 | case 0: return IRQ_PCISLOT; /* PCI Extend slot */ |
| 121 | case 1: return IRQ_PCMCIA; /* PCI Cardbus Bridge */ |
| 122 | case 2: return IRQ_PCIETH; /* Realtek Ethernet controller */ |
| 123 | case 3: return IRQ_PCIHUB; /* Realtek Ethernet Hub controller */ |
| 124 | default: |
| 125 | printk("PCI: Bad IRQ mapping request for slot %d\n", slot); |
| 126 | return -1; |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | static struct resource sh7751_io_resource = { |
| 131 | .name = "SH7751_IO", |
| 132 | .start = 0x4000, |
| 133 | .end = 0x4000 + SH7751_PCI_IO_SIZE - 1, |
| 134 | .flags = IORESOURCE_IO |
| 135 | }; |
| 136 | |
| 137 | static struct resource sh7751_mem_resource = { |
| 138 | .name = "SH7751_mem", |
| 139 | .start = SH7751_PCI_MEMORY_BASE, |
| 140 | .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, |
| 141 | .flags = IORESOURCE_MEM |
| 142 | }; |
| 143 | |
| 144 | extern struct pci_ops sh7751_pci_ops; |
| 145 | |
| 146 | struct pci_channel board_pci_channels[] = { |
| 147 | { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, |
| 148 | { NULL, NULL, NULL, 0, 0 }, |
| 149 | }; |
| 150 | EXPORT_SYMBOL(board_pci_channels); |