Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * arch/v850/kernel/mb_a_pci.c -- PCI support for Midas lab RTE-MOTHER-A board |
| 3 | * |
| 4 | * Copyright (C) 2001,02,03 NEC Electronics Corporation |
| 5 | * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org> |
| 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General |
| 8 | * Public License. See the file COPYING in the main directory of this |
| 9 | * archive for more details. |
| 10 | * |
| 11 | * Written by Miles Bader <miles@gnu.org> |
| 12 | */ |
| 13 | |
| 14 | #include <linux/config.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/spinlock.h> |
| 20 | #include <linux/pci.h> |
| 21 | |
| 22 | #include <asm/machdep.h> |
| 23 | |
| 24 | /* __nomods_init is like __devinit, but is a no-op when modules are enabled. |
| 25 | This is used by some routines that can be called either during boot |
| 26 | or by a module. */ |
| 27 | #ifdef CONFIG_MODULES |
| 28 | #define __nomods_init /*nothing*/ |
| 29 | #else |
| 30 | #define __nomods_init __devinit |
| 31 | #endif |
| 32 | |
| 33 | /* PCI devices on the Mother-A board can only do DMA to/from the MB SRAM |
| 34 | (the RTE-V850E/MA1-CB cpu board doesn't support PCI access to |
| 35 | CPU-board memory), and since linux DMA buffers are allocated in |
| 36 | normal kernel memory, we basically have to copy DMA blocks around |
| 37 | (this is like a `bounce buffer'). When a DMA block is `mapped', we |
| 38 | allocate an identically sized block in MB SRAM, and if we're doing |
| 39 | output to the device, copy the CPU-memory block to the MB-SRAM block. |
| 40 | When an active block is `unmapped', we will copy the block back to |
| 41 | CPU memory if necessary, and then deallocate the MB SRAM block. |
| 42 | Ack. */ |
| 43 | |
| 44 | /* Where the motherboard SRAM is in the PCI-bus address space (the |
| 45 | first 512K of it is also mapped at PCI address 0). */ |
| 46 | #define PCI_MB_SRAM_ADDR 0x800000 |
| 47 | |
| 48 | /* Convert CPU-view MB SRAM address to/from PCI-view addresses of the |
| 49 | same memory. */ |
| 50 | #define MB_SRAM_TO_PCI(mb_sram_addr) \ |
| 51 | ((dma_addr_t)mb_sram_addr - MB_A_SRAM_ADDR + PCI_MB_SRAM_ADDR) |
| 52 | #define PCI_TO_MB_SRAM(pci_addr) \ |
| 53 | (void *)(pci_addr - PCI_MB_SRAM_ADDR + MB_A_SRAM_ADDR) |
| 54 | |
| 55 | static void pcibios_assign_resources (void); |
| 56 | |
| 57 | struct mb_pci_dev_irq { |
| 58 | unsigned dev; /* PCI device number */ |
| 59 | unsigned irq_base; /* First IRQ */ |
| 60 | unsigned query_pin; /* True if we should read the device's |
| 61 | Interrupt Pin info, and allocate |
| 62 | interrupt IRQ_BASE + PIN. */ |
| 63 | }; |
| 64 | |
| 65 | /* PCI interrupts are mapped statically to GBUS interrupts. */ |
| 66 | static struct mb_pci_dev_irq mb_pci_dev_irqs[] = { |
| 67 | /* Motherboard SB82558 ethernet controller */ |
| 68 | { 10, IRQ_MB_A_LAN, 0 }, |
| 69 | /* PCI slot 1 */ |
| 70 | { 8, IRQ_MB_A_PCI1(0), 1 }, |
| 71 | /* PCI slot 2 */ |
| 72 | { 9, IRQ_MB_A_PCI2(0), 1 } |
| 73 | }; |
| 74 | #define NUM_MB_PCI_DEV_IRQS \ |
| 75 | (sizeof mb_pci_dev_irqs / sizeof mb_pci_dev_irqs[0]) |
| 76 | |
| 77 | |
| 78 | /* PCI configuration primitives. */ |
| 79 | |
| 80 | #define CONFIG_DMCFGA(bus, devfn, offs) \ |
| 81 | (0x80000000 \ |
| 82 | | ((offs) & ~0x3) \ |
| 83 | | ((devfn) << 8) \ |
| 84 | | ((bus)->number << 16)) |
| 85 | |
| 86 | static int |
| 87 | mb_pci_read (struct pci_bus *bus, unsigned devfn, int offs, int size, u32 *rval) |
| 88 | { |
| 89 | u32 addr; |
| 90 | int flags; |
| 91 | |
| 92 | local_irq_save (flags); |
| 93 | |
| 94 | MB_A_PCI_PCICR = 0x7; |
| 95 | MB_A_PCI_DMCFGA = CONFIG_DMCFGA (bus, devfn, offs); |
| 96 | |
| 97 | addr = MB_A_PCI_IO_ADDR + (offs & 0x3); |
| 98 | |
| 99 | switch (size) { |
| 100 | case 1: *rval = *(volatile u8 *)addr; break; |
| 101 | case 2: *rval = *(volatile u16 *)addr; break; |
| 102 | case 4: *rval = *(volatile u32 *)addr; break; |
| 103 | } |
| 104 | |
| 105 | if (MB_A_PCI_PCISR & 0x2000) { |
| 106 | MB_A_PCI_PCISR = 0x2000; |
| 107 | *rval = ~0; |
| 108 | } |
| 109 | |
| 110 | MB_A_PCI_DMCFGA = 0; |
| 111 | |
| 112 | local_irq_restore (flags); |
| 113 | |
| 114 | return PCIBIOS_SUCCESSFUL; |
| 115 | } |
| 116 | |
| 117 | static int |
| 118 | mb_pci_write (struct pci_bus *bus, unsigned devfn, int offs, int size, u32 val) |
| 119 | { |
| 120 | u32 addr; |
| 121 | int flags; |
| 122 | |
| 123 | local_irq_save (flags); |
| 124 | |
| 125 | MB_A_PCI_PCICR = 0x7; |
| 126 | MB_A_PCI_DMCFGA = CONFIG_DMCFGA (bus, devfn, offs); |
| 127 | |
| 128 | addr = MB_A_PCI_IO_ADDR + (offs & 0x3); |
| 129 | |
| 130 | switch (size) { |
| 131 | case 1: *(volatile u8 *)addr = val; break; |
| 132 | case 2: *(volatile u16 *)addr = val; break; |
| 133 | case 4: *(volatile u32 *)addr = val; break; |
| 134 | } |
| 135 | |
| 136 | if (MB_A_PCI_PCISR & 0x2000) |
| 137 | MB_A_PCI_PCISR = 0x2000; |
| 138 | |
| 139 | MB_A_PCI_DMCFGA = 0; |
| 140 | |
| 141 | local_irq_restore (flags); |
| 142 | |
| 143 | return PCIBIOS_SUCCESSFUL; |
| 144 | } |
| 145 | |
| 146 | static struct pci_ops mb_pci_config_ops = { |
| 147 | .read = mb_pci_read, |
| 148 | .write = mb_pci_write, |
| 149 | }; |
| 150 | |
| 151 | |
| 152 | /* PCI Initialization. */ |
| 153 | |
| 154 | static struct pci_bus *mb_pci_bus = 0; |
| 155 | |
| 156 | /* Do initial PCI setup. */ |
| 157 | static int __devinit pcibios_init (void) |
| 158 | { |
| 159 | u32 id = MB_A_PCI_PCIHIDR; |
| 160 | u16 vendor = id & 0xFFFF; |
| 161 | u16 device = (id >> 16) & 0xFFFF; |
| 162 | |
| 163 | if (vendor == PCI_VENDOR_ID_PLX && device == PCI_DEVICE_ID_PLX_9080) { |
| 164 | printk (KERN_INFO |
| 165 | "PCI: PLX Technology PCI9080 HOST/PCI bridge\n"); |
| 166 | |
| 167 | MB_A_PCI_PCICR = 0x147; |
| 168 | |
| 169 | MB_A_PCI_PCIBAR0 = 0x007FFF00; |
| 170 | MB_A_PCI_PCIBAR1 = 0x0000FF00; |
| 171 | MB_A_PCI_PCIBAR2 = 0x00800000; |
| 172 | |
| 173 | MB_A_PCI_PCILTR = 0x20; |
| 174 | |
| 175 | MB_A_PCI_PCIPBAM |= 0x3; |
| 176 | |
| 177 | MB_A_PCI_PCISR = ~0; /* Clear errors. */ |
| 178 | |
| 179 | /* Reprogram the motherboard's IO/config address space, |
| 180 | as we don't support the GCS7 address space that the |
| 181 | default uses. */ |
| 182 | |
| 183 | /* Significant address bits used for decoding PCI GCS5 space |
| 184 | accessess. */ |
| 185 | MB_A_PCI_DMRR = ~(MB_A_PCI_MEM_SIZE - 1); |
| 186 | |
| 187 | /* I don't understand this, but the SolutionGear example code |
| 188 | uses such an offset, and it doesn't work without it. XXX */ |
| 189 | #if GCS5_SIZE == 0x00800000 |
| 190 | #define GCS5_CFG_OFFS 0x00800000 |
| 191 | #else |
| 192 | #define GCS5_CFG_OFFS 0 |
| 193 | #endif |
| 194 | |
| 195 | /* Address bit values for matching. Note that we have to give |
| 196 | the address from the motherboard's point of view, which is |
| 197 | different than the CPU's. */ |
| 198 | /* PCI memory space. */ |
| 199 | MB_A_PCI_DMLBAM = GCS5_CFG_OFFS + 0x0; |
| 200 | /* PCI I/O space. */ |
| 201 | MB_A_PCI_DMLBAI = |
| 202 | GCS5_CFG_OFFS + (MB_A_PCI_IO_ADDR - GCS5_ADDR); |
| 203 | |
| 204 | mb_pci_bus = pci_scan_bus (0, &mb_pci_config_ops, 0); |
| 205 | |
| 206 | pcibios_assign_resources (); |
| 207 | } else |
| 208 | printk (KERN_ERR "PCI: HOST/PCI bridge not found\n"); |
| 209 | |
| 210 | return 0; |
| 211 | } |
| 212 | |
| 213 | subsys_initcall (pcibios_init); |
| 214 | |
| 215 | char __devinit *pcibios_setup (char *option) |
| 216 | { |
| 217 | /* Don't handle any options. */ |
| 218 | return option; |
| 219 | } |
| 220 | |
| 221 | |
| 222 | int __nomods_init pcibios_enable_device (struct pci_dev *dev, int mask) |
| 223 | { |
| 224 | u16 cmd, old_cmd; |
| 225 | int idx; |
| 226 | struct resource *r; |
| 227 | |
| 228 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 229 | old_cmd = cmd; |
| 230 | for (idx = 0; idx < 6; idx++) { |
| 231 | r = &dev->resource[idx]; |
| 232 | if (!r->start && r->end) { |
| 233 | printk(KERN_ERR "PCI: Device %s not available because " |
| 234 | "of resource collisions\n", pci_name(dev)); |
| 235 | return -EINVAL; |
| 236 | } |
| 237 | if (r->flags & IORESOURCE_IO) |
| 238 | cmd |= PCI_COMMAND_IO; |
| 239 | if (r->flags & IORESOURCE_MEM) |
| 240 | cmd |= PCI_COMMAND_MEMORY; |
| 241 | } |
| 242 | if (cmd != old_cmd) { |
| 243 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
| 244 | pci_name(dev), old_cmd, cmd); |
| 245 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 246 | } |
| 247 | return 0; |
| 248 | } |
| 249 | |
| 250 | |
| 251 | /* Resource allocation. */ |
| 252 | static void __devinit pcibios_assign_resources (void) |
| 253 | { |
| 254 | struct pci_dev *dev = NULL; |
| 255 | struct resource *r; |
| 256 | |
| 257 | for_each_pci_dev(dev) { |
| 258 | unsigned di_num; |
| 259 | unsigned class = dev->class >> 8; |
| 260 | |
| 261 | if (class && class != PCI_CLASS_BRIDGE_HOST) { |
| 262 | unsigned r_num; |
| 263 | for(r_num = 0; r_num < 6; r_num++) { |
| 264 | r = &dev->resource[r_num]; |
| 265 | if (!r->start && r->end) |
| 266 | pci_assign_resource (dev, r_num); |
| 267 | } |
| 268 | } |
| 269 | |
| 270 | /* Assign interrupts. */ |
| 271 | for (di_num = 0; di_num < NUM_MB_PCI_DEV_IRQS; di_num++) { |
| 272 | struct mb_pci_dev_irq *di = &mb_pci_dev_irqs[di_num]; |
| 273 | |
| 274 | if (di->dev == PCI_SLOT (dev->devfn)) { |
| 275 | unsigned irq = di->irq_base; |
| 276 | |
| 277 | if (di->query_pin) { |
| 278 | /* Find out which interrupt pin |
| 279 | this device uses (each PCI |
| 280 | slot has 4). */ |
| 281 | u8 irq_pin; |
| 282 | |
| 283 | pci_read_config_byte (dev, |
| 284 | PCI_INTERRUPT_PIN, |
| 285 | &irq_pin); |
| 286 | |
| 287 | if (irq_pin == 0) |
| 288 | /* Doesn't use interrupts. */ |
| 289 | continue; |
| 290 | else |
| 291 | irq += irq_pin - 1; |
| 292 | } |
| 293 | |
| 294 | pcibios_update_irq (dev, irq); |
| 295 | } |
| 296 | } |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | void __devinit pcibios_update_irq (struct pci_dev *dev, int irq) |
| 301 | { |
| 302 | dev->irq = irq; |
| 303 | pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); |
| 304 | } |
| 305 | |
| 306 | void __devinit |
| 307 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
| 308 | struct resource *res) |
| 309 | { |
| 310 | unsigned long offset = 0; |
| 311 | |
| 312 | if (res->flags & IORESOURCE_IO) { |
| 313 | offset = MB_A_PCI_IO_ADDR; |
| 314 | } else if (res->flags & IORESOURCE_MEM) { |
| 315 | offset = MB_A_PCI_MEM_ADDR; |
| 316 | } |
| 317 | |
| 318 | region->start = res->start - offset; |
| 319 | region->end = res->end - offset; |
| 320 | } |
| 321 | |
| 322 | |
| 323 | /* Stubs for things we don't use. */ |
| 324 | |
| 325 | /* Called after each bus is probed, but before its children are examined. */ |
| 326 | void pcibios_fixup_bus(struct pci_bus *b) |
| 327 | { |
| 328 | } |
| 329 | |
| 330 | void |
| 331 | pcibios_align_resource (void *data, struct resource *res, |
| 332 | unsigned long size, unsigned long align) |
| 333 | { |
| 334 | } |
| 335 | |
| 336 | void pcibios_set_master (struct pci_dev *dev) |
| 337 | { |
| 338 | } |
| 339 | |
| 340 | |
| 341 | /* Mother-A SRAM memory allocation. This is a simple first-fit allocator. */ |
| 342 | |
| 343 | /* A memory free-list node. */ |
| 344 | struct mb_sram_free_area { |
| 345 | void *mem; |
| 346 | unsigned long size; |
| 347 | struct mb_sram_free_area *next; |
| 348 | }; |
| 349 | |
| 350 | /* The tail of the free-list, which starts out containing all the SRAM. */ |
| 351 | static struct mb_sram_free_area mb_sram_free_tail = { |
| 352 | (void *)MB_A_SRAM_ADDR, MB_A_SRAM_SIZE, 0 |
| 353 | }; |
| 354 | |
| 355 | /* The free-list. */ |
| 356 | static struct mb_sram_free_area *mb_sram_free_areas = &mb_sram_free_tail; |
| 357 | |
| 358 | /* The free-list of free free-list nodes. (:-) */ |
| 359 | static struct mb_sram_free_area *mb_sram_free_free_areas = 0; |
| 360 | |
| 361 | /* Spinlock protecting the above globals. */ |
| 362 | static DEFINE_SPINLOCK(mb_sram_lock); |
| 363 | |
| 364 | /* Allocate a memory block at least SIZE bytes long in the Mother-A SRAM |
| 365 | space. */ |
| 366 | static void *alloc_mb_sram (size_t size) |
| 367 | { |
| 368 | struct mb_sram_free_area *prev, *fa; |
| 369 | int flags; |
| 370 | void *mem = 0; |
| 371 | |
| 372 | spin_lock_irqsave (mb_sram_lock, flags); |
| 373 | |
| 374 | /* Look for a free area that can contain SIZE bytes. */ |
| 375 | for (prev = 0, fa = mb_sram_free_areas; fa; prev = fa, fa = fa->next) |
| 376 | if (fa->size >= size) { |
| 377 | /* Found one! */ |
| 378 | mem = fa->mem; |
| 379 | |
| 380 | if (fa->size == size) { |
| 381 | /* In fact, it fits exactly, so remove |
| 382 | this node from the free-list. */ |
| 383 | if (prev) |
| 384 | prev->next = fa->next; |
| 385 | else |
| 386 | mb_sram_free_areas = fa->next; |
| 387 | /* Put it on the free-list-entry-free-list. */ |
| 388 | fa->next = mb_sram_free_free_areas; |
| 389 | mb_sram_free_free_areas = fa; |
| 390 | } else { |
| 391 | /* FA is bigger than SIZE, so just |
| 392 | reduce its size to account for this |
| 393 | allocation. */ |
| 394 | fa->mem += size; |
| 395 | fa->size -= size; |
| 396 | } |
| 397 | |
| 398 | break; |
| 399 | } |
| 400 | |
| 401 | spin_unlock_irqrestore (mb_sram_lock, flags); |
| 402 | |
| 403 | return mem; |
| 404 | } |
| 405 | |
| 406 | /* Return the memory area MEM of size SIZE to the MB SRAM free pool. */ |
| 407 | static void free_mb_sram (void *mem, size_t size) |
| 408 | { |
| 409 | struct mb_sram_free_area *prev, *fa, *new_fa; |
| 410 | int flags; |
| 411 | void *end = mem + size; |
| 412 | |
| 413 | spin_lock_irqsave (mb_sram_lock, flags); |
| 414 | |
| 415 | retry: |
| 416 | /* Find an adjacent free-list entry. */ |
| 417 | for (prev = 0, fa = mb_sram_free_areas; fa; prev = fa, fa = fa->next) |
| 418 | if (fa->mem == end) { |
| 419 | /* FA is just after MEM, grow down to encompass it. */ |
| 420 | fa->mem = mem; |
| 421 | fa->size += size; |
| 422 | goto done; |
| 423 | } else if (fa->mem + fa->size == mem) { |
| 424 | struct mb_sram_free_area *next_fa = fa->next; |
| 425 | |
| 426 | /* FA is just before MEM, expand to encompass it. */ |
| 427 | fa->size += size; |
| 428 | |
| 429 | /* See if FA can now be merged with its successor. */ |
| 430 | if (next_fa && fa->mem + fa->size == next_fa->mem) { |
| 431 | /* Yup; merge NEXT_FA's info into FA. */ |
| 432 | fa->size += next_fa->size; |
| 433 | fa->next = next_fa->next; |
| 434 | /* Free NEXT_FA. */ |
| 435 | next_fa->next = mb_sram_free_free_areas; |
| 436 | mb_sram_free_free_areas = next_fa; |
| 437 | } |
| 438 | goto done; |
| 439 | } else if (fa->mem > mem) |
| 440 | /* We've reached the right spot in the free-list |
| 441 | without finding an adjacent free-area, so add |
| 442 | a new free area to hold mem. */ |
| 443 | break; |
| 444 | |
| 445 | /* Make a new free-list entry. */ |
| 446 | |
| 447 | /* First, get a free-list entry. */ |
| 448 | if (! mb_sram_free_free_areas) { |
| 449 | /* There are none, so make some. */ |
| 450 | void *block; |
| 451 | size_t block_size = sizeof (struct mb_sram_free_area) * 8; |
| 452 | |
| 453 | /* Don't hold the lock while calling kmalloc (I'm not |
| 454 | sure whether it would be a problem, since we use |
| 455 | GFP_ATOMIC, but it makes me nervous). */ |
| 456 | spin_unlock_irqrestore (mb_sram_lock, flags); |
| 457 | |
| 458 | block = kmalloc (block_size, GFP_ATOMIC); |
| 459 | if (! block) |
| 460 | panic ("free_mb_sram: can't allocate free-list entry"); |
| 461 | |
| 462 | /* Now get the lock back. */ |
| 463 | spin_lock_irqsave (mb_sram_lock, flags); |
| 464 | |
| 465 | /* Add the new free free-list entries. */ |
| 466 | while (block_size > 0) { |
| 467 | struct mb_sram_free_area *nfa = block; |
| 468 | nfa->next = mb_sram_free_free_areas; |
| 469 | mb_sram_free_free_areas = nfa; |
| 470 | block += sizeof *nfa; |
| 471 | block_size -= sizeof *nfa; |
| 472 | } |
| 473 | |
| 474 | /* Since we dropped the lock to call kmalloc, the |
| 475 | free-list could have changed, so retry from the |
| 476 | beginning. */ |
| 477 | goto retry; |
| 478 | } |
| 479 | |
| 480 | /* Remove NEW_FA from the free-list of free-list entries. */ |
| 481 | new_fa = mb_sram_free_free_areas; |
| 482 | mb_sram_free_free_areas = new_fa->next; |
| 483 | |
| 484 | /* NEW_FA initially holds only MEM. */ |
| 485 | new_fa->mem = mem; |
| 486 | new_fa->size = size; |
| 487 | |
| 488 | /* Insert NEW_FA in the free-list between PREV and FA. */ |
| 489 | new_fa->next = fa; |
| 490 | if (prev) |
| 491 | prev->next = new_fa; |
| 492 | else |
| 493 | mb_sram_free_areas = new_fa; |
| 494 | |
| 495 | done: |
| 496 | spin_unlock_irqrestore (mb_sram_lock, flags); |
| 497 | } |
| 498 | |
| 499 | |
| 500 | /* Maintainence of CPU -> Mother-A DMA mappings. */ |
| 501 | |
| 502 | struct dma_mapping { |
| 503 | void *cpu_addr; |
| 504 | void *mb_sram_addr; |
| 505 | size_t size; |
| 506 | struct dma_mapping *next; |
| 507 | }; |
| 508 | |
| 509 | /* A list of mappings from CPU addresses to MB SRAM addresses for active |
| 510 | DMA blocks (that have been `granted' to the PCI device). */ |
| 511 | static struct dma_mapping *active_dma_mappings = 0; |
| 512 | |
| 513 | /* A list of free mapping objects. */ |
| 514 | static struct dma_mapping *free_dma_mappings = 0; |
| 515 | |
| 516 | /* Spinlock protecting the above globals. */ |
| 517 | static DEFINE_SPINLOCK(dma_mappings_lock); |
| 518 | |
| 519 | static struct dma_mapping *new_dma_mapping (size_t size) |
| 520 | { |
| 521 | int flags; |
| 522 | struct dma_mapping *mapping; |
| 523 | void *mb_sram_block = alloc_mb_sram (size); |
| 524 | |
| 525 | if (! mb_sram_block) |
| 526 | return 0; |
| 527 | |
| 528 | spin_lock_irqsave (dma_mappings_lock, flags); |
| 529 | |
| 530 | if (! free_dma_mappings) { |
| 531 | /* We're out of mapping structures, make more. */ |
| 532 | void *mblock; |
| 533 | size_t mblock_size = sizeof (struct dma_mapping) * 8; |
| 534 | |
| 535 | /* Don't hold the lock while calling kmalloc (I'm not |
| 536 | sure whether it would be a problem, since we use |
| 537 | GFP_ATOMIC, but it makes me nervous). */ |
| 538 | spin_unlock_irqrestore (dma_mappings_lock, flags); |
| 539 | |
| 540 | mblock = kmalloc (mblock_size, GFP_ATOMIC); |
| 541 | if (! mblock) { |
| 542 | free_mb_sram (mb_sram_block, size); |
| 543 | return 0; |
| 544 | } |
| 545 | |
| 546 | /* Get the lock back. */ |
| 547 | spin_lock_irqsave (dma_mappings_lock, flags); |
| 548 | |
| 549 | /* Add the new mapping structures to the free-list. */ |
| 550 | while (mblock_size > 0) { |
| 551 | struct dma_mapping *fm = mblock; |
| 552 | fm->next = free_dma_mappings; |
| 553 | free_dma_mappings = fm; |
| 554 | mblock += sizeof *fm; |
| 555 | mblock_size -= sizeof *fm; |
| 556 | } |
| 557 | } |
| 558 | |
| 559 | /* Get a mapping struct from the freelist. */ |
| 560 | mapping = free_dma_mappings; |
| 561 | free_dma_mappings = mapping->next; |
| 562 | |
| 563 | /* Initialize the mapping. Other fields should be filled in by |
| 564 | caller. */ |
| 565 | mapping->mb_sram_addr = mb_sram_block; |
| 566 | mapping->size = size; |
| 567 | |
| 568 | /* Add it to the list of active mappings. */ |
| 569 | mapping->next = active_dma_mappings; |
| 570 | active_dma_mappings = mapping; |
| 571 | |
| 572 | spin_unlock_irqrestore (dma_mappings_lock, flags); |
| 573 | |
| 574 | return mapping; |
| 575 | } |
| 576 | |
| 577 | static struct dma_mapping *find_dma_mapping (void *mb_sram_addr) |
| 578 | { |
| 579 | int flags; |
| 580 | struct dma_mapping *mapping; |
| 581 | |
| 582 | spin_lock_irqsave (dma_mappings_lock, flags); |
| 583 | |
| 584 | for (mapping = active_dma_mappings; mapping; mapping = mapping->next) |
| 585 | if (mapping->mb_sram_addr == mb_sram_addr) { |
| 586 | spin_unlock_irqrestore (dma_mappings_lock, flags); |
| 587 | return mapping; |
| 588 | } |
| 589 | |
| 590 | panic ("find_dma_mapping: unmapped PCI DMA addr 0x%x", |
| 591 | MB_SRAM_TO_PCI (mb_sram_addr)); |
| 592 | } |
| 593 | |
| 594 | static struct dma_mapping *deactivate_dma_mapping (void *mb_sram_addr) |
| 595 | { |
| 596 | int flags; |
| 597 | struct dma_mapping *mapping, *prev; |
| 598 | |
| 599 | spin_lock_irqsave (dma_mappings_lock, flags); |
| 600 | |
| 601 | for (prev = 0, mapping = active_dma_mappings; |
| 602 | mapping; |
| 603 | prev = mapping, mapping = mapping->next) |
| 604 | { |
| 605 | if (mapping->mb_sram_addr == mb_sram_addr) { |
| 606 | /* This is the MAPPING; deactivate it. */ |
| 607 | if (prev) |
| 608 | prev->next = mapping->next; |
| 609 | else |
| 610 | active_dma_mappings = mapping->next; |
| 611 | |
| 612 | spin_unlock_irqrestore (dma_mappings_lock, flags); |
| 613 | |
| 614 | return mapping; |
| 615 | } |
| 616 | } |
| 617 | |
| 618 | panic ("deactivate_dma_mapping: unmapped PCI DMA addr 0x%x", |
| 619 | MB_SRAM_TO_PCI (mb_sram_addr)); |
| 620 | } |
| 621 | |
| 622 | /* Return MAPPING to the freelist. */ |
| 623 | static inline void |
| 624 | free_dma_mapping (struct dma_mapping *mapping) |
| 625 | { |
| 626 | int flags; |
| 627 | |
| 628 | free_mb_sram (mapping->mb_sram_addr, mapping->size); |
| 629 | |
| 630 | spin_lock_irqsave (dma_mappings_lock, flags); |
| 631 | |
| 632 | mapping->next = free_dma_mappings; |
| 633 | free_dma_mappings = mapping; |
| 634 | |
| 635 | spin_unlock_irqrestore (dma_mappings_lock, flags); |
| 636 | } |
| 637 | |
| 638 | |
| 639 | /* Single PCI DMA mappings. */ |
| 640 | |
| 641 | /* `Grant' to PDEV the memory block at CPU_ADDR, for doing DMA. The |
| 642 | 32-bit PCI bus mastering address to use is returned. the device owns |
| 643 | this memory until either pci_unmap_single or pci_dma_sync_single is |
| 644 | performed. */ |
| 645 | dma_addr_t |
| 646 | pci_map_single (struct pci_dev *pdev, void *cpu_addr, size_t size, int dir) |
| 647 | { |
| 648 | struct dma_mapping *mapping = new_dma_mapping (size); |
| 649 | |
| 650 | if (! mapping) |
| 651 | return 0; |
| 652 | |
| 653 | mapping->cpu_addr = cpu_addr; |
| 654 | |
| 655 | if (dir == PCI_DMA_BIDIRECTIONAL || dir == PCI_DMA_TODEVICE) |
| 656 | memcpy (mapping->mb_sram_addr, cpu_addr, size); |
| 657 | |
| 658 | return MB_SRAM_TO_PCI (mapping->mb_sram_addr); |
| 659 | } |
| 660 | |
| 661 | /* Return to the CPU the PCI DMA memory block previously `granted' to |
| 662 | PDEV, at DMA_ADDR. */ |
| 663 | void pci_unmap_single (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size, |
| 664 | int dir) |
| 665 | { |
| 666 | void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr); |
| 667 | struct dma_mapping *mapping = deactivate_dma_mapping (mb_sram_addr); |
| 668 | |
| 669 | if (size != mapping->size) |
| 670 | panic ("pci_unmap_single: size (%d) doesn't match" |
| 671 | " size of mapping at PCI DMA addr 0x%x (%d)\n", |
| 672 | size, dma_addr, mapping->size); |
| 673 | |
| 674 | /* Copy back the DMA'd contents if necessary. */ |
| 675 | if (dir == PCI_DMA_BIDIRECTIONAL || dir == PCI_DMA_FROMDEVICE) |
| 676 | memcpy (mapping->cpu_addr, mb_sram_addr, size); |
| 677 | |
| 678 | /* Return mapping to the freelist. */ |
| 679 | free_dma_mapping (mapping); |
| 680 | } |
| 681 | |
| 682 | /* Make physical memory consistent for a single streaming mode DMA |
| 683 | translation after a transfer. |
| 684 | |
| 685 | If you perform a pci_map_single() but wish to interrogate the |
| 686 | buffer using the cpu, yet do not wish to teardown the PCI dma |
| 687 | mapping, you must call this function before doing so. At the next |
| 688 | point you give the PCI dma address back to the card, you must first |
| 689 | perform a pci_dma_sync_for_device, and then the device again owns |
| 690 | the buffer. */ |
| 691 | void |
| 692 | pci_dma_sync_single_for_cpu (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size, |
| 693 | int dir) |
| 694 | { |
| 695 | void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr); |
| 696 | struct dma_mapping *mapping = find_dma_mapping (mb_sram_addr); |
| 697 | |
| 698 | /* Synchronize the DMA buffer with the CPU buffer if necessary. */ |
| 699 | if (dir == PCI_DMA_FROMDEVICE) |
| 700 | memcpy (mapping->cpu_addr, mb_sram_addr, size); |
| 701 | else if (dir == PCI_DMA_TODEVICE) |
| 702 | ; /* nothing to do */ |
| 703 | else |
| 704 | panic("pci_dma_sync_single: unsupported sync dir: %d", dir); |
| 705 | } |
| 706 | |
| 707 | void |
| 708 | pci_dma_sync_single_for_device (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size, |
| 709 | int dir) |
| 710 | { |
| 711 | void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr); |
| 712 | struct dma_mapping *mapping = find_dma_mapping (mb_sram_addr); |
| 713 | |
| 714 | /* Synchronize the DMA buffer with the CPU buffer if necessary. */ |
| 715 | if (dir == PCI_DMA_FROMDEVICE) |
| 716 | ; /* nothing to do */ |
| 717 | else if (dir == PCI_DMA_TODEVICE) |
| 718 | memcpy (mb_sram_addr, mapping->cpu_addr, size); |
| 719 | else |
| 720 | panic("pci_dma_sync_single: unsupported sync dir: %d", dir); |
| 721 | } |
| 722 | |
| 723 | |
| 724 | /* Scatter-gather PCI DMA mappings. */ |
| 725 | |
| 726 | /* Do multiple DMA mappings at once. */ |
| 727 | int |
| 728 | pci_map_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len, int dir) |
| 729 | { |
| 730 | BUG (); |
| 731 | return 0; |
| 732 | } |
| 733 | |
| 734 | /* Unmap multiple DMA mappings at once. */ |
| 735 | void |
| 736 | pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len,int dir) |
| 737 | { |
| 738 | BUG (); |
| 739 | } |
| 740 | |
| 741 | /* Make physical memory consistent for a set of streaming mode DMA |
| 742 | translations after a transfer. The same as pci_dma_sync_single_* but |
| 743 | for a scatter-gather list, same rules and usage. */ |
| 744 | |
| 745 | void |
| 746 | pci_dma_sync_sg_for_cpu (struct pci_dev *dev, struct scatterlist *sg, int sg_len, |
| 747 | int dir) |
| 748 | { |
| 749 | BUG (); |
| 750 | } |
| 751 | |
| 752 | void |
| 753 | pci_dma_sync_sg_for_device (struct pci_dev *dev, struct scatterlist *sg, int sg_len, |
| 754 | int dir) |
| 755 | { |
| 756 | BUG (); |
| 757 | } |
| 758 | |
| 759 | |
| 760 | /* PCI mem mapping. */ |
| 761 | |
| 762 | /* Allocate and map kernel buffer using consistent mode DMA for PCI |
| 763 | device. Returns non-NULL cpu-view pointer to the buffer if |
| 764 | successful and sets *DMA_ADDR to the pci side dma address as well, |
| 765 | else DMA_ADDR is undefined. */ |
| 766 | void * |
| 767 | pci_alloc_consistent (struct pci_dev *pdev, size_t size, dma_addr_t *dma_addr) |
| 768 | { |
| 769 | void *mb_sram_mem = alloc_mb_sram (size); |
| 770 | if (mb_sram_mem) |
| 771 | *dma_addr = MB_SRAM_TO_PCI (mb_sram_mem); |
| 772 | return mb_sram_mem; |
| 773 | } |
| 774 | |
| 775 | /* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must |
| 776 | be values that were returned from pci_alloc_consistent. SIZE must be |
| 777 | the same as what as passed into pci_alloc_consistent. References to |
| 778 | the memory and mappings assosciated with CPU_ADDR or DMA_ADDR past |
| 779 | this call are illegal. */ |
| 780 | void |
| 781 | pci_free_consistent (struct pci_dev *pdev, size_t size, void *cpu_addr, |
| 782 | dma_addr_t dma_addr) |
| 783 | { |
| 784 | void *mb_sram_mem = PCI_TO_MB_SRAM (dma_addr); |
| 785 | free_mb_sram (mb_sram_mem, size); |
| 786 | } |
| 787 | |
| 788 | |
| 789 | /* symbol exports (for modules) */ |
| 790 | |
| 791 | EXPORT_SYMBOL (pci_map_single); |
| 792 | EXPORT_SYMBOL (pci_unmap_single); |
| 793 | EXPORT_SYMBOL (pci_alloc_consistent); |
| 794 | EXPORT_SYMBOL (pci_free_consistent); |
| 795 | EXPORT_SYMBOL (pci_dma_sync_single_for_cpu); |
| 796 | EXPORT_SYMBOL (pci_dma_sync_single_for_device); |